From nobody Mon Nov 25 13:34:55 2024 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2052.outbound.protection.outlook.com [40.107.95.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0C68215C67; Fri, 25 Oct 2024 23:51:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.95.52 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900263; cv=fail; b=iHCiV+gVSqVCASLRK251nVjznx+jQk6AwT/JjhBdteP331YRi5MwmOJYSIYJe8Y0mpuRXDnLk3R/wlZPOz75IoeEEuNuNq9ZwQy6W2vunwM7A2t832DQFjgS8tcSjMGVyP2GOkdHQECkW/z6x6zYhR1N3tBqDs8IDoXoejck/4M= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900263; c=relaxed/simple; bh=FOBlebnyDihh8AbKGQ7xYR8v5Q80CG+iYvdsdbC5ru0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SO3/rZf88hZfccx0p+s1KssfnuBVo8fr5iL/Jg7Bh263fazUU504JPdIHNgauIYV0bwhuN2jwNus4SetJdouo72+ybEUJhQBNA5zgKujKdDHaoPfb22yKVg4F1tDo9E+v6LGYcJCJ+vPRaWto+Q+pobro/NYqL8/mn9iiSAybTI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=mchuk+eS; arc=fail smtp.client-ip=40.107.95.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="mchuk+eS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OAlvD6eZtCSevCXeLSNPXv2V+C3j+1HI/u4J9LwpZmor2Z0NFPTDxCS6YXV4n8a9m2DjLUqFXm2gTH6JIwLCi4zT3cDdQQ2SpzYeEK9SfqaSRxoZpjqb1AVF4WrSPv/ayjhiWeGmWO9QvKsuD+XJD366tZiPSeyVn1X9+D/R+yS/skq04y08Z9aJ0dDk/rW06UncBkxQCPzW/h6C+mP6sNK0UykW3nF76VQnEkWBQdGl6IUUriG534ehqwdusV/6/QvCxrkS3eYyUqLi1OiIog8GHz7icmD8fGXpPXvnbB2Ro8/oSuMU1Wpz1Q16BLWUgtC/y9Cz87bBdboMoYxvCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0u2vSK34F1wYUBkrCQv22GvR6cRo+SHm4fs7kHqisyY=; b=PjV2lwgYaEI/WOn7T6s1WO/kU77dDxi3eFzeBSmvEC9+0TC8v/rhJDBmzoZ1RUmguZRU8Qvi/M0NTS38fDcHQ0KoZzmA5d8Aa2FWczrqQDR4hFz3LSGzMR6L8vNF9owjhS+JpsENT56aRjPE09XR7iko/gmRdvn8oZI1VYfph3fd9D5Z47L7a5XtIQJbRoz6tmdQrGNSn1NXb0wPEQdXjF+UkBtYiTXgRTFja1vC85n4qg9+i0YEvG4NgL/J16/702UpP0LPVdLN3OyRTdzQLOEc8aJ3s8uRK8aSm6F9eZVPBAgv6agwZPrBy/W86O/HmIybzB/oiSFtFXKchOOQ+Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0u2vSK34F1wYUBkrCQv22GvR6cRo+SHm4fs7kHqisyY=; b=mchuk+eSS4zTZmVDAdKUAAiTcc1ZxTKhy/J1vBPE4WJeZ0EHVuBSu8j5i6Zc36ZUZrdHFLUKQZBxxmmhAyotJMl610N89ZOlV3oisedGc3LKZpaq6SnpOMknV0YunjoGeh/Zln1uSwddGO4BPXlhMgm+UBykKXfftIY/Pg/a8UKpVplwD+9ksbGsSUta2HwpKKfwlXpmYj+gCqnT8hQXwqc0Z9+Q5M/gHBqXBvp14Rh5Pk+Ko0GiCPR6ilHKmm/8my/kbfNu2ukQ1VjoRDizFVXEoyXXgQIaOlenLwNAZaXLBEnpuoZVAjHfJSIXkW5EHagRSiQsDMIF7JNfjgKbTg== Received: from BY5PR03CA0013.namprd03.prod.outlook.com (2603:10b6:a03:1e0::23) by BL4PR12MB9480.namprd12.prod.outlook.com (2603:10b6:208:58d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20; Fri, 25 Oct 2024 23:50:57 +0000 Received: from CO1PEPF000075ED.namprd03.prod.outlook.com (2603:10b6:a03:1e0:cafe::54) by BY5PR03CA0013.outlook.office365.com (2603:10b6:a03:1e0::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.17 via Frontend Transport; Fri, 25 Oct 2024 23:50:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF000075ED.mail.protection.outlook.com (10.167.249.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:50:57 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:49 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:48 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:47 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 01/13] iommufd/viommu: Add IOMMUFD_OBJ_VDEVICE and IOMMU_VDEVICE_ALLOC ioctl Date: Fri, 25 Oct 2024 16:50:30 -0700 Message-ID: <53025c827c44d68edb6469bfd940a8e8bc6147a5.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|BL4PR12MB9480:EE_ X-MS-Office365-Filtering-Correlation-Id: a86f6a58-8eb0-44da-268e-08dcf54fdf1a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?joZ2axU1RRVx9pcVFnSeyWXY7HXZvNSeLC038O4J1BDrC/R1iDFA9w4Z6Ef+?= =?us-ascii?Q?erCGRGsi7Z6JOKNNV9iW/O/yTTl2q/nMYBWhCTqSDSzQzEo/ZU2iOum5ng6m?= =?us-ascii?Q?AsAsd33hZ5U1TZ6H4/cPe7rAHCEMHO286HocU9UW9+vPsNG2YuqmkkzqaSNu?= =?us-ascii?Q?nZUovUYjLhPPl1pA8s1k7Jap8aFgarpxH7yU20+ARjH4xUh4jz8Rfo7tzlW7?= =?us-ascii?Q?b3caN5YYdrqPVU9aXrV+WR4T0aRq8fiDl3135U/dJtXhDaLNdiv7+bNjTjRn?= =?us-ascii?Q?LwPiMiqQKPYDOmKMgXjvW+xBFaBPDGScaQpezjkWT7h3TeOmTbnXgw78JqQf?= =?us-ascii?Q?zx1WKyr36RuqKcuQk0LdxvcqCSIRE/gWTpVBFN+1nAUqZ8ZZKxgrggxBfCRN?= =?us-ascii?Q?/yzsjNKTnCxAujeHh4TU919AryhB1ILOVF+/v3oBykSbvcy6Nt3wnhtdWW5I?= =?us-ascii?Q?atgo8jw/d7IqQYznwQnWlm+LygbKSFAPRqZIP+yKBT8NXdl5rXpA35pKxHwm?= =?us-ascii?Q?EQXcl1PzfYdXMMeXUOcC2hUoBkl/d+2SemL4did7TWcDZtK6MPA53gm8L7kK?= =?us-ascii?Q?peKdD23oWLNV3HC8/nOPEGGj3oOVYJTdLEy0zdM2W2+z8D6yOclM+dSV2vhM?= =?us-ascii?Q?0QoqjASjPLFoDWGtnJ3JGaKakO/svyAff08brNxMqjBCSmuCkpVoDuGOSl6k?= =?us-ascii?Q?hHmEOk9wIKvyDBNQlrPDYinP2aVK0T+UDtVQo4T23+GBrpP9Qy9xe3Ps9F5d?= =?us-ascii?Q?8GAlP6cHOJ4poxEfexCzLDpNQNtriH1Y4Azrc/b+5o93fZrQe6EyAiQmoxPn?= =?us-ascii?Q?bNm4hj5AzI2U6o9cejfS1QycoSWtNnrusBxnx+MnpZz6JE8/cUwvf+8yWXnV?= =?us-ascii?Q?0/WLm59CxO1lJHW7aWRl7y8WyYAdh58j9loMULKTnzSKTHucptzBHDV//ucR?= =?us-ascii?Q?yFl1Hhx7EHpUc11MwBbY7T1AMzNLOd0vNr34au44BP4j6mQhkB6cs5t9zrxJ?= =?us-ascii?Q?bN9qvP2FHIsdNl2BIIhCdt1F8NcI9v26gCNKIOQaPWOd02PugTW5DDwSLtYc?= =?us-ascii?Q?hplDr8PZ90iCTcxc47yWy7ycm5WcfYQssntLdrHM8fVw5WkS576Y2lpqGY74?= =?us-ascii?Q?CqYs4KvuBzNc73hYIUoxiqEvryDJx/ENdZrAQLugfTTnM4oHDZcpHg2pjEu3?= =?us-ascii?Q?piBsp+VvekcW+ZHSZ45L3FvLoE4cUXmvSneuc7QDf9PI/jqI9bgrBxj9m8vM?= =?us-ascii?Q?/+w4a2zt1NMBIVTn5l6qVgMshjLQ9k40SsKdc584KrJ9iDz8dFTXyo6Qwda9?= =?us-ascii?Q?YpwF+rkx8Qo2yvBkdWESpJgXVOw9MO0jvZYTI74DojuBVhKQYBfG9cNExxZ7?= =?us-ascii?Q?ZzE54a3pbpddEO/op+2G7aBDwV0ZTM7GOUcnYcTVzUi7qAtCUw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:50:57.3084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a86f6a58-8eb0-44da-268e-08dcf54fdf1a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9480 Content-Type: text/plain; charset="utf-8" Introduce a new IOMMUFD_OBJ_VDEVICE to represent a physical device, i.e. iommufd_device (idev) object, against an iommufd_viommu (vIOMMU) object in the VM. This vDEVICE object (and its structure) holds all the information and attributes in a VM, regarding the device related to the vIOMMU. As an initial patch, add a per-vIOMMU virtual ID. This can be: - Virtual StreamID on a nested ARM SMMUv3, an index to a Stream Table - Virtual DeviceID on a nested AMD IOMMU, an index to a Device Table - Virtual ID on a nested Intel VT-D IOMMU, an index to a Context Table Potentially, this vDEVICE structure would hold some vData for Confidential Compute Architecture (CCA). Use this virtual ID to index an "vdevs" xarray that belongs to a vIOMMU object. Add a new ioctl for vDEVICE allocations. Since a vDEVICE is a connection of an iommufd_device object and an iommufd_viommu object, require both as the ioctl inputs and take refcounts in the ioctl handler. Then, let the idev structure hold the allocated vdev pointer with a proper locking protection. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/iommufd_private.h | 20 +++++ include/linux/iommufd.h | 3 + include/uapi/linux/iommufd.h | 26 ++++++ drivers/iommu/iommufd/device.c | 11 +++ drivers/iommu/iommufd/main.c | 7 ++ drivers/iommu/iommufd/viommu.c | 101 ++++++++++++++++++++++++ 6 files changed, 168 insertions(+) diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index 8c9ab35eaea5..365cf5a56cdf 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -391,6 +391,7 @@ struct iommufd_device { struct iommufd_object obj; struct iommufd_ctx *ictx; struct iommufd_group *igroup; + struct iommufd_vdevice *vdev; struct list_head group_item; /* always the physical device */ struct device *dev; @@ -505,8 +506,27 @@ static inline int iommufd_hwpt_replace_device(struct i= ommufd_device *idev, return iommu_group_replace_domain(idev->igroup->group, hwpt->domain); } =20 +static inline struct iommufd_viommu * +iommufd_get_viommu(struct iommufd_ucmd *ucmd, u32 id) +{ + return container_of(iommufd_get_object(ucmd->ictx, id, + IOMMUFD_OBJ_VIOMMU), + struct iommufd_viommu, obj); +} + int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd); void iommufd_viommu_destroy(struct iommufd_object *obj); +int iommufd_vdevice_alloc_ioctl(struct iommufd_ucmd *ucmd); +void iommufd_vdevice_destroy(struct iommufd_object *obj); +void iommufd_vdevice_abort(struct iommufd_object *obj); + +struct iommufd_vdevice { + struct iommufd_object obj; + struct iommufd_ctx *ictx; + struct iommufd_device *idev; + struct iommufd_viommu *viommu; + u64 id; /* per-vIOMMU virtual ID */ +}; =20 #ifdef CONFIG_IOMMUFD_TEST int iommufd_test(struct iommufd_ucmd *ucmd); diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 083ceb209704..e6cd288e8b83 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -31,6 +31,7 @@ enum iommufd_object_type { IOMMUFD_OBJ_ACCESS, IOMMUFD_OBJ_FAULT, IOMMUFD_OBJ_VIOMMU, + IOMMUFD_OBJ_VDEVICE, #ifdef CONFIG_IOMMUFD_TEST IOMMUFD_OBJ_SELFTEST, #endif @@ -89,6 +90,8 @@ struct iommufd_viommu { =20 const struct iommufd_viommu_ops *ops; =20 + struct xarray vdevs; + unsigned int type; }; =20 diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 56c742106a45..b699ecb7aa9c 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -52,6 +52,7 @@ enum { IOMMUFD_CMD_HWPT_INVALIDATE =3D 0x8d, IOMMUFD_CMD_FAULT_QUEUE_ALLOC =3D 0x8e, IOMMUFD_CMD_VIOMMU_ALLOC =3D 0x8f, + IOMMUFD_CMD_VDEVICE_ALLOC =3D 0x90, }; =20 /** @@ -896,4 +897,29 @@ struct iommu_viommu_alloc { __u32 out_viommu_id; }; #define IOMMU_VIOMMU_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VIOMMU_ALLOC) + +/** + * struct iommu_vdevice_alloc - ioctl(IOMMU_VDEVICE_ALLOC) + * @size: sizeof(struct iommu_vdevice_alloc) + * @viommu_id: vIOMMU ID to associate with the virtual device + * @dev_id: The pyhsical device to allocate a virtual instance on the vIOM= MU + * @__reserved: Must be 0 + * @virt_id: Virtual device ID per vIOMMU, e.g. vSID of ARM SMMUv3, vDevic= eID + * of AMD IOMMU, and vID of a nested Intel VT-d to a Context Tab= le. + * @out_vdevice_id: Output virtual instance ID for the allocated object + * @__reserved2: Must be 0 + * + * Allocate a virtual device instance (for a physical device) against a vI= OMMU. + * This instance holds the device's information (related to its vIOMMU) in= a VM. + */ +struct iommu_vdevice_alloc { + __u32 size; + __u32 viommu_id; + __u32 dev_id; + __u32 __reserved; + __aligned_u64 virt_id; + __u32 out_vdevice_id; + __u32 __reserved2; +}; +#define IOMMU_VDEVICE_ALLOC _IO(IOMMUFD_TYPE, IOMMUFD_CMD_VDEVICE_ALLOC) #endif diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index 5fd3dd420290..e50113305a9c 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -277,6 +277,17 @@ EXPORT_SYMBOL_NS_GPL(iommufd_ctx_has_group, IOMMUFD); */ void iommufd_device_unbind(struct iommufd_device *idev) { + u32 vdev_id =3D 0; + + /* idev->vdev object should be destroyed prior, yet just in case.. */ + mutex_lock(&idev->igroup->lock); + if (idev->vdev) + vdev_id =3D idev->vdev->obj.id; + mutex_unlock(&idev->igroup->lock); + /* Relying on xa_lock against a race with iommufd_destroy() */ + if (vdev_id) + iommufd_object_remove(idev->ictx, NULL, vdev_id, 0); + iommufd_object_destroy_user(idev->ictx, &idev->obj); } EXPORT_SYMBOL_NS_GPL(iommufd_device_unbind, IOMMUFD); diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index ab5ee325d809..696ac9e0e74b 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -322,6 +322,7 @@ union ucmd_buffer { struct iommu_option option; struct iommu_vfio_ioas vfio_ioas; struct iommu_viommu_alloc viommu; + struct iommu_vdevice_alloc vdev; #ifdef CONFIG_IOMMUFD_TEST struct iommu_test_cmd test; #endif @@ -375,6 +376,8 @@ static const struct iommufd_ioctl_op iommufd_ioctl_ops[= ] =3D { __reserved), IOCTL_OP(IOMMU_VIOMMU_ALLOC, iommufd_viommu_alloc_ioctl, struct iommu_viommu_alloc, out_viommu_id), + IOCTL_OP(IOMMU_VDEVICE_ALLOC, iommufd_vdevice_alloc_ioctl, + struct iommu_vdevice_alloc, __reserved2), #ifdef CONFIG_IOMMUFD_TEST IOCTL_OP(IOMMU_TEST_CMD, iommufd_test, struct iommu_test_cmd, last), #endif @@ -513,6 +516,10 @@ static const struct iommufd_object_ops iommufd_object_= ops[] =3D { [IOMMUFD_OBJ_VIOMMU] =3D { .destroy =3D iommufd_viommu_destroy, }, + [IOMMUFD_OBJ_VDEVICE] =3D { + .destroy =3D iommufd_vdevice_destroy, + .abort =3D iommufd_vdevice_abort, + }, #ifdef CONFIG_IOMMUFD_TEST [IOMMUFD_OBJ_SELFTEST] =3D { .destroy =3D iommufd_selftest_destroy, diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c index eb41e15ebab1..2b9a9a80298d 100644 --- a/drivers/iommu/iommufd/viommu.c +++ b/drivers/iommu/iommufd/viommu.c @@ -12,6 +12,7 @@ void iommufd_viommu_destroy(struct iommufd_object *obj) if (viommu->ops && viommu->ops->free) viommu->ops->free(viommu); refcount_dec(&viommu->hwpt->common.obj.users); + xa_destroy(&viommu->vdevs); } =20 int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) @@ -70,6 +71,7 @@ int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucmd) */ viommu->iommu_dev =3D __iommu_get_iommu_dev(idev->dev); =20 + xa_init(&viommu->vdevs); refcount_inc(&viommu->hwpt->common.obj.users); =20 cmd->out_viommu_id =3D viommu->obj.id; @@ -87,3 +89,102 @@ int iommufd_viommu_alloc_ioctl(struct iommufd_ucmd *ucm= d) iommufd_put_object(ucmd->ictx, &idev->obj); return rc; } + +void iommufd_vdevice_abort(struct iommufd_object *obj) +{ + struct iommufd_vdevice *old, + *vdev =3D container_of(obj, struct iommufd_vdevice, obj); + struct iommufd_viommu *viommu =3D vdev->viommu; + struct iommufd_device *idev =3D vdev->idev; + + lockdep_assert_held(&idev->igroup->lock); + + old =3D xa_cmpxchg(&viommu->vdevs, vdev->id, vdev, NULL, GFP_KERNEL); + if (old) + WARN_ON(old !=3D vdev); + + refcount_dec(&viommu->obj.users); + refcount_dec(&idev->obj.users); + idev->vdev =3D NULL; +} + +void iommufd_vdevice_destroy(struct iommufd_object *obj) +{ + struct iommufd_vdevice *vdev =3D + container_of(obj, struct iommufd_vdevice, obj); + + mutex_lock(&vdev->idev->igroup->lock); + iommufd_vdevice_abort(obj); + mutex_unlock(&vdev->idev->igroup->lock); +} + +int iommufd_vdevice_alloc_ioctl(struct iommufd_ucmd *ucmd) +{ + struct iommu_vdevice_alloc *cmd =3D ucmd->cmd; + struct iommufd_vdevice *vdev, *curr; + struct iommufd_viommu *viommu; + struct iommufd_device *idev; + u64 virt_id =3D cmd->virt_id; + int rc =3D 0; + + if (virt_id > ULONG_MAX) + return -EINVAL; + + viommu =3D iommufd_get_viommu(ucmd, cmd->viommu_id); + if (IS_ERR(viommu)) + return PTR_ERR(viommu); + + idev =3D iommufd_get_device(ucmd, cmd->dev_id); + if (IS_ERR(idev)) { + rc =3D PTR_ERR(idev); + goto out_put_viommu; + } + + mutex_lock(&idev->igroup->lock); + if (idev->vdev) { + rc =3D -EEXIST; + goto out_unlock_igroup; + } + + vdev =3D iommufd_object_alloc(ucmd->ictx, vdev, IOMMUFD_OBJ_VDEVICE); + if (IS_ERR(vdev)) { + rc =3D PTR_ERR(vdev); + goto out_unlock_igroup; + } + + rc =3D iommufd_verify_unfinalized_object(ucmd->ictx, &vdev->obj); + if (rc) { + kfree(vdev); + goto out_unlock_igroup; + } + + vdev->idev =3D idev; + vdev->id =3D virt_id; + vdev->viommu =3D viommu; + + idev->vdev =3D vdev; + refcount_inc(&idev->obj.users); + refcount_inc(&viommu->obj.users); + + curr =3D xa_cmpxchg(&viommu->vdevs, virt_id, NULL, vdev, GFP_KERNEL); + if (curr) { + rc =3D xa_err(curr) ?: -EBUSY; + goto out_abort; + } + + cmd->out_vdevice_id =3D vdev->obj.id; + rc =3D iommufd_ucmd_respond(ucmd, sizeof(*cmd)); + if (rc) + goto out_abort; + iommufd_object_finalize(ucmd->ictx, &vdev->obj); + goto out_unlock_igroup; + +out_abort: + iommufd_object_abort_and_destroy(ucmd->ictx, &vdev->obj); +out_unlock_igroup: + mutex_unlock(&idev->igroup->lock); + iommufd_put_object(ucmd->ictx, &idev->obj); +out_put_viommu: + iommufd_put_object(ucmd->ictx, &viommu->obj); + return rc; +} --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2074.outbound.protection.outlook.com [40.107.101.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0C41218955; Fri, 25 Oct 2024 23:51:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.74 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900266; cv=fail; b=e4JdjBQJ3kz5VyzYmcAVcjNnb8XAKKYWqQzMVWbkwR2wsI++XlZKayQxjajGB64U+7SMUjcYYyOzemOyaROH8OLAcnmxsVT1YQoQEyN/Bo4k64v7XrMVo3wSl19ay/tvCLxZXqFuEHWobfSQjvtCkT8eVB/mDcht2RhJ5C2bipM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900266; c=relaxed/simple; bh=Lri1otdXvKxp0kKq+HmoBK6cX2c+jINqrCYIy8o9GDI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U6YVkOBWGNqG4YJAvyNWjh1gxqDn1USllr7s7sI4ugcFW5dGeZA+WbnRJFONqhLHe16o6X/FrH3k/kac34pMAmcAeG+qf9LjhI5A6csT19U3MQvi/lKRcPDjjqQYyFwG+d4U4EC4kXHgNdSsALeAgc+bnWQDrmpfdLzi7mPYMhc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=GI2Na+ua; arc=fail smtp.client-ip=40.107.101.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="GI2Na+ua" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=a1A9fMuZhQdvXhjSGciCLlsH6ebMFdwgsrsbTHtob7AwtG2S7e1/jT9tJaFNpjPdxpkAFkRkZBpmxT8VkTLjMbkcFiubhOlr/yy6mGv0XI33YKqg2qzjbxOBerTwBBw8uJ4KVKSKr9/eUBEQQ9IwSLIwkK1z+NOhzYPnhWnKNIf8tBjO9ghE5WuSQgVY1pMFC8D65hm99NPMAS/uAbrQAOFZs+5gb4dRRIhQGb/AI9NHErFL1aQTHbGWAagbcsP4aXCtLk0DfaOi3mGPrx8tNzGtKXmKhgNjsiExoM7wCHbyrGWLajusAqqDBd5Z9BCYB5sNJ7oh7pd2lB3wI3b/SQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=eOVbhKjzMHtKwFiz7VIxmXTimA3jrruMi1sombXt4SM=; b=cqm3LXRtDGjRUh5OMjn4qP9d8NUi8ajTRBEceF+aezrFDS/nPUk8hvGwRuj58Ycu/5tb6cdYcB3PhEZcVac4pGRqs/7660NCIjA4iR/qyEA2g3wuPGN3FgtGNOMProVPRCXa5iSqkEzcElbCrbaIpaAHsU2ThP0oGB2Lb7ZkFmpptxPnOFpuU9rdO+0dyxPejqP30oqwpjcBtlhOq7SaS1a5jkS7se19bD0F9Wkx+NHRYDZP3uOsaRwp45Jhk9ndDcVLNmUYqywpzb3P4HocZhXDxO10s6Uis+ajPeOro0d12dMbSThyoduRMnIvm2wzHwGUduxyNhyw7kzoBOxqTQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=eOVbhKjzMHtKwFiz7VIxmXTimA3jrruMi1sombXt4SM=; b=GI2Na+ualkab/6ReDdOnIV2ffM3DNoj4iBSsBsNNi4XRwajNrPDITmbCUFBS1dVZai9M3n2tW63GFx1RpLNGYi+DLR+kn6cWdhKLbfbiR1oRskgzh9NWnSab4gj8Z9R4rIYB3qVvC5+Oo2ofmHNV8wIxZ3ElPxlu6eLcUhQz0wvLSlCsGR/i66ieZhjGH6ryhV7lFCufjensB8eOtA6h/6pbLtef+FZJVDuSYR4i7TDPiAmKCBOy6QAwIllXUNeivieKnwGTK4YsAP3uKwdVGr2TFcmeb6aXVJDTqucQdj25exMnSkDgAI0wdgNKNojgKg8povP5HEEALlErlEbVdg== Received: from MW4P222CA0024.NAMP222.PROD.OUTLOOK.COM (2603:10b6:303:114::29) by SN7PR12MB7372.namprd12.prod.outlook.com (2603:10b6:806:29b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.21; Fri, 25 Oct 2024 23:50:59 +0000 Received: from SJ1PEPF000023D0.namprd02.prod.outlook.com (2603:10b6:303:114:cafe::29) by MW4P222CA0024.outlook.office365.com (2603:10b6:303:114::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8069.29 via Frontend Transport; Fri, 25 Oct 2024 23:50:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023D0.mail.protection.outlook.com (10.167.244.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:50:59 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:50 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:50 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:49 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 02/13] iommufd/selftest: Add IOMMU_VDEVICE_ALLOC test coverage Date: Fri, 25 Oct 2024 16:50:31 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D0:EE_|SN7PR12MB7372:EE_ X-MS-Office365-Filtering-Correlation-Id: 2faf49b8-196b-49a8-6d10-08dcf54fe01b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?X3AyOBWUvZhMSOHmPhaEqE0XMs4n2n/tPdVw4Hy8NA4EJ47JRbP71+W+Qvzm?= =?us-ascii?Q?YUOIloIUnauWEFIm9ksDu9Q9B1MQWXrzK/Khz2VbpliTV1sUsqTi2YFUYQo6?= =?us-ascii?Q?NZDnfxe8YGTQzCmQXr9cIlDw+dg+Je555tHwy/JY+Z64fiNEUk6h0BfC6f4c?= =?us-ascii?Q?ZSJ9FY+8SDbqftjqCBNuzsFWk1YaenHuppe0uU0ebUwreS6bBFphjXzLH8SA?= =?us-ascii?Q?aCzmtjqAQl5xhwampW0gJ2G/VRksfj6kTmQOU957MBJG/B7bnkqc3SfmgMAS?= =?us-ascii?Q?eIEafJhSJRnC8GT1CflSEHsZIgtUZYvW5DydlbV1BvJmAR/vAMBMAQQKZjXr?= =?us-ascii?Q?wP5PzyMXl9HCoVXeEGUD28msr9mSYFD2vFMHnsjRWtledfbLFBxZKyGivsUt?= =?us-ascii?Q?cO0BDo41vdR0PTm1wMUj4/UTApm1tgPpJOwhmm+6Km9qomQf9A+zXi/6IEh7?= =?us-ascii?Q?yU2S1SStSMUhgH418TloFXES94vt6SzRtwDrPK/FmBcHxSCxHSZFXtW6mNgM?= =?us-ascii?Q?59CN01s8gqNPYKJzCvxerDTCfGuxZfdMSiMq7w2lHUHx3oJaTvMg3fXEcVLH?= =?us-ascii?Q?G8D2p9s/EjUiirst5lP4nrfVTl1IJhGYCN3SpbcoYRtT9rUPRg9tH2KKFgd4?= =?us-ascii?Q?lACJODTU9qdOcgGeLNAozXlSU+s9gwc6l2UqMvIMKNekgsPdyFzYoNWvLKdt?= =?us-ascii?Q?RNmsJDjn5cXsmT8l1nvEZXA0Wx0+NAVCCylQIaSQvJ3N9TSlVGPm5JY7SQXM?= =?us-ascii?Q?5uxTIfTht9YPKpJrR6MYzsO2sn5f5GrMENBjVRJQvvaCyDS1XOhG40HSK3Yp?= =?us-ascii?Q?KuC3RMpNmns8H0tx2Fu27biIhar6eWOMuOxtHdfh6Ryq0wVFQyCpbF7Y1OzF?= =?us-ascii?Q?WNIZGfcPm2ovlwik1Fr3ED6nAPUhHBxQuSXcoQSto9dSEnPdORVHh60Apd5r?= =?us-ascii?Q?BHmJc3+PLnll9nj/44ZPH4FwSf0VNQoqWfhjER7+G1vNNoTMNIPXCZEh+Gvl?= =?us-ascii?Q?JEyXqt6Cwszk2S6S9EsjdXINDe+YxxjAhniZ7dKqvX654qFh9sK4wRG4BpE2?= =?us-ascii?Q?kPnZPpXi8ckuVjeVGJKgp+dp+fJvoRglc0XPtk++AeYN+yqPFW3asqptRlf7?= =?us-ascii?Q?T09S+2faU8jGhLWZUFCofjJU47sU7cpGfm01bipiRJVT4hRlVZQjI2aFSQ5I?= =?us-ascii?Q?VSBRFIbdPy1RASLVbFTYt4iZFHC90v3iGoDiXpbsCSH4z8wwzP4CRArfHXC9?= =?us-ascii?Q?wlvKP58Ixvky/e6oIg/3F3Nv5oVF+ja+Dxdyhd5vXMozpm9nmzCaVl7zUSgU?= =?us-ascii?Q?yRXDHAIV+KzHI9Plw7vNuGeeWSogeiO4u/Vzg9Qe30Lsf8IwbMJ6tCA1UiS5?= =?us-ascii?Q?F8QGPnvwDhbf4go4BeX4j/VA4lc/SKmskXAadEVnIR//I/yejw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:50:59.0570 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2faf49b8-196b-49a8-6d10-08dcf54fe01b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7372 Content-Type: text/plain; charset="utf-8" Add a vdevice_alloc op to the viommu mock_viommu_ops for the coverage of IOMMU_VIOMMU_TYPE_SELFTEST allocations. Then, add a vdevice_alloc TEST_F to cover the IOMMU_VDEVICE_ALLOC ioctl. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian --- tools/testing/selftests/iommu/iommufd_utils.h | 27 +++++++++++++++++++ tools/testing/selftests/iommu/iommufd.c | 20 ++++++++++++++ .../selftests/iommu/iommufd_fail_nth.c | 4 +++ 3 files changed, 51 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/= selftests/iommu/iommufd_utils.h index ca09308dad6a..5b17d7b2ac5c 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -790,3 +790,30 @@ static int _test_cmd_viommu_alloc(int fd, __u32 device= _id, __u32 hwpt_id, EXPECT_ERRNO(_errno, \ _test_cmd_viommu_alloc(self->fd, device_id, hwpt_id, \ type, 0, viommu_id)) + +static int _test_cmd_vdevice_alloc(int fd, __u32 viommu_id, __u32 idev_id, + __u64 virt_id, __u32 *vdev_id) +{ + struct iommu_vdevice_alloc cmd =3D { + .size =3D sizeof(cmd), + .dev_id =3D idev_id, + .viommu_id =3D viommu_id, + .virt_id =3D virt_id, + }; + int ret; + + ret =3D ioctl(fd, IOMMU_VDEVICE_ALLOC, &cmd); + if (ret) + return ret; + if (vdev_id) + *vdev_id =3D cmd.out_vdevice_id; + return 0; +} + +#define test_cmd_vdevice_alloc(viommu_id, idev_id, virt_id, vdev_id) = \ + ASSERT_EQ(0, _test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, \ + virt_id, vdev_id)) +#define test_err_vdevice_alloc(_errno, viommu_id, idev_id, virt_id, vdev_i= d) \ + EXPECT_ERRNO(_errno, \ + _test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, \ + virt_id, vdev_id)) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selfte= sts/iommu/iommufd.c index b48b22d33ad4..93255403dee4 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -129,6 +129,7 @@ TEST_F(iommufd, cmd_length) TEST_LENGTH(iommu_option, IOMMU_OPTION, val64); TEST_LENGTH(iommu_vfio_ioas, IOMMU_VFIO_IOAS, __reserved); TEST_LENGTH(iommu_viommu_alloc, IOMMU_VIOMMU_ALLOC, out_viommu_id); + TEST_LENGTH(iommu_vdevice_alloc, IOMMU_VDEVICE_ALLOC, __reserved2); #undef TEST_LENGTH } =20 @@ -2473,4 +2474,23 @@ TEST_F(iommufd_viommu, viommu_auto_destroy) { } =20 +TEST_F(iommufd_viommu, vdevice_alloc) +{ + uint32_t viommu_id =3D self->viommu_id; + uint32_t dev_id =3D self->device_id; + uint32_t vdev_id =3D 0; + + if (dev_id) { + /* Set vdev_id to 0x99, unset it, and set to 0x88 */ + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x99, &vdev_id); + test_err_vdevice_alloc(EEXIST, viommu_id, dev_id, 0x99, + &vdev_id); + test_ioctl_destroy(vdev_id); + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x88, &vdev_id); + test_ioctl_destroy(vdev_id); + } else { + test_err_vdevice_alloc(ENOENT, viommu_id, dev_id, 0x99, NULL); + } +} + TEST_HARNESS_MAIN diff --git a/tools/testing/selftests/iommu/iommufd_fail_nth.c b/tools/testi= ng/selftests/iommu/iommufd_fail_nth.c index e9a980b7729b..28f11b26f836 100644 --- a/tools/testing/selftests/iommu/iommufd_fail_nth.c +++ b/tools/testing/selftests/iommu/iommufd_fail_nth.c @@ -583,6 +583,7 @@ TEST_FAIL_NTH(basic_fail_nth, device) uint32_t idev_id; uint32_t hwpt_id; uint32_t viommu_id; + uint32_t vdev_id; __u64 iova; =20 self->fd =3D open("/dev/iommu", O_RDWR); @@ -635,6 +636,9 @@ TEST_FAIL_NTH(basic_fail_nth, device) IOMMU_VIOMMU_TYPE_SELFTEST, 0, &viommu_id)) return -1; =20 + if (_test_cmd_vdevice_alloc(self->fd, viommu_id, idev_id, 0, &vdev_id)) + return -1; + return 0; } =20 --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2043.outbound.protection.outlook.com [40.107.100.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5961215C6B; Fri, 25 Oct 2024 23:51:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.43 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900271; cv=fail; b=FKHtJAGPBimHIxGAlhh791d3QenXJJWLuhkfiowVBHChtXVDjXjndqjqnZgg5+klvq1K31OTt2IIlwnGRIbfMOX3RDjJyjXBjihYR6g7NGWNIFYt81FXhKy0mmkgWKli9slGn0WFUPYDxUFpvrXBZhSNzdt+7VtQj2QQORmY5zM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900271; c=relaxed/simple; bh=o8uhP+J65A23rmuNLrlxuApcD270ErM1VWdSWE25220=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I4mnDR1u/h0eHMC8SpimXrkKTWozYzGsLAnUyCVli2Y3lwZjhPtTnFnXL0gBiQxM/FYCMDcOc6taCY74RoDULBxLVbOx0vsFvbxBRGt+Cu7L5NUPOncjwmSxLPFaAYKnnMXQtE1u8Pg69xKoyt5CFyKomjJnGnEEgrLsA/Fln5U= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=HIiY24GN; arc=fail smtp.client-ip=40.107.100.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="HIiY24GN" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DgIWO7iStfvtZVnzsrcgpk6pCSlJwZnmdAhZGnCU8/f6+7dQYOTSZJaMiYH5ztPZw83d3m+YgsJ82IXN7IfYtKsN+y7Pwa/TFKhwlV5aycHZUbOwc0ACT0hqy6pCnuKkKr3SrM45lPTCiVdzzSQv2BQAs6HKRlowgJP24AJ9QtPot6DqahMHckAb6SYE5bMN3y2dwKVjCcDhX6szWQFGeZnFjEy7jAa/bXF5t89QbFDbhp3J2/wZkc1/pLVniiF3Q+Hp27tyCovvPHaPtlUYbiQQKiDpHnEbtApHHT4vIxsWQtrepoVavudvdL51yaAdeKBuvOjX2IHQCIyEPvhhiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yaerqgkx1SDByzbEftWJcr3XJ9L+0hT8ZgnECFVw/qk=; b=mdtseqhMUoO5HXCH663XYGvV/FZLGZqWbaO6PvyGr5CAzR9YgZ1S8sP/XA3jjdmIe5SO/n9iquXfEvXHixBm970SFXFAol8h/gKOOec70wNQZQ07ne1x/rCJZ7yaErOSDrfJoeaefZm4gBZX94in1biOKgsq1p6ZARkrsgVtu/dk7Azq6R0fK7akIehVkq6UpCygZaWfRFRNeOOQrjaDJhfxAmK+nScAKwYYbzwFeKkwZbL5KNeaiZXaXLZzNjIYTgRDgO4wuv9i3GpQ3NzXvebfk9ooTPZ4cgmVwx81M/lP6Rzw02dO/7o7Z6P136KsN0iEZTPqTVdBmgHU/u2WQQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yaerqgkx1SDByzbEftWJcr3XJ9L+0hT8ZgnECFVw/qk=; b=HIiY24GNUDwMs0SSluguN4sPwP91pdE/ofBLMfgEP9YxdJYWsaOeAbhnf/d0a+cVc+rMPROJPO9+V18kCmR9/VuUBEmZyiKWE8WhfsAhZS0qk06C86/bhf5SL/fwMVDXgeyRakI5SkrN6whcY+Ao4wa/wD9BaUMsYJ+nOnXqSK+ikZPOiGUKYf5onfUmhHfvLUW3Q1WTngKO9McULO62ak8SyEi95CSejKtFoqU0xqclwhzzvGqVyJE9Hnh0OLB8giF6ZXL1yuv+eaNqZ9j6fhSYy6rXsHQNrqCS/vPMdeNS2GUfLeAAb23frsydI89Borl5fIf4bFkV8pdK7JBfHA== Received: from MW4PR03CA0266.namprd03.prod.outlook.com (2603:10b6:303:b4::31) by PH7PR12MB6980.namprd12.prod.outlook.com (2603:10b6:510:1ba::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.17; Fri, 25 Oct 2024 23:51:00 +0000 Received: from CO1PEPF000075EE.namprd03.prod.outlook.com (2603:10b6:303:b4:cafe::c4) by MW4PR03CA0266.outlook.office365.com (2603:10b6:303:b4::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.22 via Frontend Transport; Fri, 25 Oct 2024 23:51:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF000075EE.mail.protection.outlook.com (10.167.249.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:50:59 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:52 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:51 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:50 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 03/13] iommu/viommu: Add cache_invalidate to iommufd_viommu_ops Date: Fri, 25 Oct 2024 16:50:32 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075EE:EE_|PH7PR12MB6980:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f9af7a3-dbd6-4107-3bc2-08dcf54fe0aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|7416014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?t0wqGYWZmbAXttT5DXVjhCiWBx1q+TNk2gvgk/lni8XdjDXEUZuc8gRoviC0?= =?us-ascii?Q?K18d25FZe2+8pNRiuF8D2KbKMNX3D7ZD2sw3/hF6j3J9aoZHlNg1snFEcStj?= =?us-ascii?Q?Fa8jq6hIvvpjxLUVyB8F8pZRfzWOW3lV1mNjE0mGy7S7g8Lk/rMW6NbbqBtj?= =?us-ascii?Q?jFFpqvMISbiM3zqP8ydzt4VtfwirbHG5anx7N/Qs1TnlsyfIIrEF1gn0AxFK?= =?us-ascii?Q?7gsKj6oU2fAkDsJpLVbtSoVeV8SYfaHgQ0Oa6xTmrzDRY22bFwzPhkDad89i?= =?us-ascii?Q?LxnYgeg0S1UMn0XEjdn6Bo7yJSFoLGv8YFqqsWZwFB/Zny7bfzTDoIxPd/w3?= =?us-ascii?Q?7lhLuU78iVR6cthRPZdYiRWplNYfy5v+kVYTCymO4BCDfXiWQaQTGf3E+Cwd?= =?us-ascii?Q?63i8Av4RICmfS9ueWgUeUEbcU1frLz0t898w2CtDgEp02BBjF1n7nOAteAi8?= =?us-ascii?Q?iGkQPOIjJWeaL5Dun4YXvSGlz5iAzvbESr5G8EMF57ne28cdn3cQX2azJwgx?= =?us-ascii?Q?rq2GjzQ6Xyypi/Trx19I85vfoV9b2ehPWR/DO+yLPjpxrzc0lq08TZ9DEFVD?= =?us-ascii?Q?myR5ZXJ8TRpSm8oSG7YT+q4FKx/kTGTR1/50YO0P1cKQmSvo7sxAHXDrmzTh?= =?us-ascii?Q?gW2uHxFvRWOg9qD/xGFzL1ns7HV2cMz4TQql6/eAnFuvQea5HqaoVseFfWS+?= =?us-ascii?Q?m9vFI/DuPvT9DV6roWSdGGJBrVQGM7WdZT43VDYOUPQP/621cuHRDwrrHaYB?= =?us-ascii?Q?Rf3CzfkWZ1CMzl3toj2lh9ZWy+H+euIj5XLEkW2MPv+ESKyF2id/Vu91r6pF?= =?us-ascii?Q?q21yMktapJX56+mP9Nadq4o6TT22iwx+qwMtgkpAsdrlMAdUXOiU2T5uVrcF?= =?us-ascii?Q?7k2gnLcS7K9jXYCrGHtWkf+jJSlZQKq65jlwTjLmkCHlXSCP+G3zo95Rn7hG?= =?us-ascii?Q?f/ROLDe4C/FGUHamXTJNpnEttlC+F8mUUdmrHZJTsVTdXyDLwSbMOzfPLRmH?= =?us-ascii?Q?WXSpDgBMcGPR4nOfGxzRDBbkdJfDK12L/5uCBYoPzIj4WGaD4lsKBhfmsuR7?= =?us-ascii?Q?wzSJ257FNJl4oMjhm0dHjjN7Fgct9lZbPXw79VtF8p6WKvxp+jarhGzxDR2x?= =?us-ascii?Q?bDjH9QtwUBzRQU7XEc4JIX/TFD7ZIrU0OcPUNI/ebw9Au/6IFQLBHLW9Ig4Z?= =?us-ascii?Q?NLt7ULUVgJy2Jcb1YL6MRpQvJmfeLtpAPBz44zhHWmkU8hm05x8Sucu78LWP?= =?us-ascii?Q?JUzkqmnvffjonR+SPp2pJC410uaJpJZonHnD3f4fvlvtFPOjkQspiRCEwVhx?= =?us-ascii?Q?NmsMLpGIQFDf9CEA/z1DYPrW+Jw9Rv/SRZkUfi2gx80xOqdlsVGJBN+ZcnAO?= =?us-ascii?Q?IAB8fZMzXAE8Ho8pJ04dlK6suYeBOhYfGVOzeygFamH+9e8d7A=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(7416014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:50:59.9460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f9af7a3-dbd6-4107-3bc2-08dcf54fe0aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6980 Content-Type: text/plain; charset="utf-8" This per-vIOMMU cache_invalidate op is like the cache_invalidate_user op in struct iommu_domain_ops, but wider, supporting device cache (e.g. PCI ATC invaldiations). Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- include/linux/iommufd.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index e6cd288e8b83..0287a6d00192 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -15,6 +15,7 @@ struct device; struct file; struct iommu_group; struct iommu_user_data; +struct iommu_user_data_array; struct iommufd_access; struct iommufd_ctx; struct iommufd_device; @@ -104,12 +105,21 @@ struct iommufd_viommu { * must be defined in include/uapi/linux/iommufd.h. * It must fully initialize the new iommu_domain bef= ore * returning. Upon failure, ERR_PTR must be returned. + * @cache_invalidate: Flush hardware cache used by a vIOMMU. It can be use= d for + * any IOMMU hardware specific cache: TLB and device ca= che. + * The @array passes in the cache invalidation requests= , in + * form of a driver data structure. A driver must updat= e the + * array->entry_num to report the number of handled req= uests. + * The data structure of the array entry must be define= d in + * include/uapi/linux/iommufd.h */ struct iommufd_viommu_ops { void (*free)(struct iommufd_viommu *viommu); struct iommu_domain *(*alloc_domain_nested)( struct iommufd_viommu *viommu, const struct iommu_user_data *user_data); + int (*cache_invalidate)(struct iommufd_viommu *viommu, + struct iommu_user_data_array *array); }; =20 #if IS_ENABLED(CONFIG_IOMMUFD) --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2079.outbound.protection.outlook.com [40.107.96.79]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31FC921B87F; Fri, 25 Oct 2024 23:51:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.79 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900269; cv=fail; b=cqSdUa8hXuuOAjwAPxlItlZVkFWtZ42WmnEUuK0bFJDEVUYSCnGH0Srz3Un7VTsTmcFRcgxoEp59uxvd2WiR7Qpik5qhRbf6oRSg8cv+dz452GjWFv79FnU8QQDjqJwmbnRUnhGgL7UpBnBDObtU9/tJM6NzdDyHeKysD9RdfyI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900269; c=relaxed/simple; bh=m6NtazFjDOoXVE0z95akjspYa6tLq34tcpq+ACpra6w=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=plxtq5g81DQWchVQuNDD66vQvb10G3iy8gQDRAuAb3xmvLgCa0gDwmRtqulE/LOlC4PByqKxWbC/ENkjcX6u2RC59cIYEHroPVUnua42lKWx5RPXrxt74d3QOUxGk6sIl5uRLxaJQ02qnF2VN4/5wFNt5UFPaTKvcDFoyY1PuLM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=eyIUIYoX; arc=fail smtp.client-ip=40.107.96.79 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="eyIUIYoX" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=OlswzoNOLPR/fEoljbJiwrWqUHHgqwqLrj1YOy6TMomV+lXapeBTGYg14X/sTRCzW/lsdQ3k7ZoJjGwM5Ce5+pnftU5v8jgLcbWjQxoY2UahvlDm7Z5ShYZ601eRkW9HJJi1TaaznhCtpEw8vui+J+6eOvmW9ZAAWqTQXTQO6KpCODLKcCFNqdjXsMbk6bQ9z9QQ2r0u3YggEHDYUqX5C69xUrsQ8i0nNT81k3ZXzKtVn2ugSpZb7PCjuTYI8HdfbB3Tzdya3d+1qVKU5Bf1JvVbXOzTbZygv1zksLZVtM10KgqyRfk0669acx89tyZtvsb8oYKn83rZdUwGagvvbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nv9bI/lX4Seevvti8f+iWh8jttgs/bT+cLQvhyiew1I=; b=Yl5Omdm/69X0RwpEdOoTOTut/hdgttw/rjWmLc0GSa7pucY57oo9IZO4w4FZrF8oeT2xzjrqdAdgD9gpyhq7MeWbiyLvNrxFMzZTkviacX7Ti1oWbzYaIiplSJYpj9k+frE/fkJozhqJq/Av2riGo6xa7afHIqNQvrDBteSf24mppUe/iiB2VthD2+ToDBemdl+/jvRHKTpkVJfp5PaCijyuHnleFHRkeVvjJ6vey4ShFe7Qd/wGsuj6f4DDXp7L0ZgaeBmVsBXe3hORL8PEeR7aHufApmwtu9zzLaMmzKxf8jRyHXmVLsuTVJ4x85VotSv8kn/jW5Q+quIioJs/4w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nv9bI/lX4Seevvti8f+iWh8jttgs/bT+cLQvhyiew1I=; b=eyIUIYoXsz+bPhuZchNQUoQS07rThApbMoX+ewk4uR0tZV3iCJIJg8H3hZoCrgsj0/0vMgFY3CumBIV0IhBNl2lrTCzZvpZc0RWoC6OaseHIVIb7bC3LuvxDUTCoMAL0gxGMf7FR3tUePZaHi+0FJfdnbfkaENAAs4zqieJRGvInTMWm1D4SqVLG1hNWczi/dzuE1tIRd7mEqFH+g3ActHhxVhTED1GztdMDF2veRkboNrLgQzMchAAy8FhPfOw6TB5/a1ppGuvO+CwQNRd2EA5b37TTJCuC8ucYV27rg0oYeygips0w8rf/JrZ3qtuufGctPkbet/ljyiRqhESfLQ== Received: from BY3PR10CA0004.namprd10.prod.outlook.com (2603:10b6:a03:255::9) by CH2PR12MB4136.namprd12.prod.outlook.com (2603:10b6:610:a4::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.21; Fri, 25 Oct 2024 23:51:03 +0000 Received: from SJ1PEPF000023D2.namprd02.prod.outlook.com (2603:10b6:a03:255:cafe::ba) by BY3PR10CA0004.outlook.office365.com (2603:10b6:a03:255::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.18 via Frontend Transport; Fri, 25 Oct 2024 23:51:03 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023D2.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:03 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:53 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:53 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:52 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 04/13] iommufd/hw_pagetable: Enforce invalidation op on vIOMMU-based hwpt_nested Date: Fri, 25 Oct 2024 16:50:33 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|CH2PR12MB4136:EE_ X-MS-Office365-Filtering-Correlation-Id: 55ce9c59-22c8-43f8-26b5-08dcf54fe287 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?p6/rKJaEZDv8AT/9ZxYAC14rpxf17jpIPGw9/j0r5AKrI7RxUtWpoVCNAjo2?= =?us-ascii?Q?+SvPytIM9okePm0LGYzvCoZD5qBYZIRNRFfhxDCRmnMws+VLknDLsEhaZYhB?= =?us-ascii?Q?+Yc6ZYBc9m9bLtbM6vT9ygAB8yX6XEWAMUcRTTDcoChRQJWBYi4cXATUqUX7?= =?us-ascii?Q?SwZJWZiBAiwDNcg+arjB4q9giSM0hf21/9cpzTLnvyeYanIja6Qk4x+cQLWa?= =?us-ascii?Q?dXE/F84reOTyebYbtOv5V491JiJZOQd/og5ldO/5QVM9vnHFP8NQkNLtZEmA?= =?us-ascii?Q?bECx47oPdrBllW2bD1oy7IokTl1GgRbw6Q5dsYEC6oKZ/0e1iKqye/brTriu?= =?us-ascii?Q?aVZKfgpo1Buoilf35iCc+EsfSaDhUkQy4GUBGo++9X1cRMO1tCz1Dwm//Zqc?= =?us-ascii?Q?eZolZvypEnkNMYXDEGUBv7Fbtl3MoLIwhOsoCpkduPMhBgBecjxkMJNpPPWU?= =?us-ascii?Q?xF470LcWpOKH/f3SGFCL/7yvNewpM6so7v3ET5K6bJP0ef+jlAEFqyICgBBn?= =?us-ascii?Q?qHt7PlRzRFLi6XFtwmq0QX0476kps0Pyc9QoUo/yxZzHwp56G9AS2vrcOnvb?= =?us-ascii?Q?sNpxZXPd4A8umdvfI1uudeiChxr2SX2mvM+g07CjmoA8ysLGr6Kt9VrRxHZg?= =?us-ascii?Q?eEKg4EIVXpdRrb1FkVOKh9ijnb+GbqJqK1430NPH9gRno9zsoCj84lHc3aTO?= =?us-ascii?Q?jvIDZXpYLsF140BD8ba5zCJ5uN9PlkxWTEi1m5QKrPEmCb6lWBElz6FM6ed/?= =?us-ascii?Q?2HWKYK1HHe4ddDebj2vjr+CQ8Wm+UeOjDV4fVYBr1b3iCip+iM2MTvBRLJ7f?= =?us-ascii?Q?bIIdzjuGxEDyRXlOpXJwM878O5qu5YzpJqxGWte0BWPl/0HrEOM46Ps7/90g?= =?us-ascii?Q?jHdlfPtbtLMzDae/q4GEQ29n5kO2fXNiqebUZ9aguorJs7FJxCr+d6ZrhSgo?= =?us-ascii?Q?JinMoy1lrOH0MWmHT65Z9JewiH0GIIwGdu2K0BMez1CYT/P0IWFXpjEV+8Nj?= =?us-ascii?Q?lWoe41r3iv/JjOzAcjn9UPiWITPaDj23KAGd0gageGfd2YcKw/V7BkJ9GZUS?= =?us-ascii?Q?KlBh6XBlxVPvX3v7GcJWV33D+GdSyUbO1kbcH5vZ7oBOfdJ76CDdiJx8b9jC?= =?us-ascii?Q?3Ea4Ib8hQp8SQx5QJI05RZilOxysRtSR8M4wQqVMpdzhGkMb2KvSoZypyFNJ?= =?us-ascii?Q?cLDrJylMeKZSgwC9hNG1D5TBdImzD44jVG7EfJK+FSxDGm5rkTQ0bppxoJ7y?= =?us-ascii?Q?ovzPSHzA/JsPtsC8sdHc04ty81Dq5oAU9+0BwcZZIjVK/iRbTGNTSVlUrrXx?= =?us-ascii?Q?zLZxyUaN3MQLBC0gqAhFd+GSmy27BbWBV49eZE4vuFyEYVSN8sfP5YkC6f20?= =?us-ascii?Q?rqy594OkJIjXKa0BNVaEkQIwWFDRUsrJ22XUrT+ps9JNSg2RlA=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:03.1341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 55ce9c59-22c8-43f8-26b5-08dcf54fe287 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4136 Content-Type: text/plain; charset="utf-8" A vIOMMU-based hwpt_nested requires a cache invalidation op too, either using the one in iommu_domain_ops or the one in viommu_ops. Enforce that upon the allocated hwpt_nested. Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe Reviewed-by: Kevin Tian --- drivers/iommu/iommufd/hw_pagetable.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index 1df5d40c93df..fd260a67b82c 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -302,7 +302,9 @@ iommufd_viommu_alloc_hwpt_nested(struct iommufd_viommu = *viommu, u32 flags, } hwpt->domain->owner =3D viommu->iommu_dev->ops; =20 - if (WARN_ON_ONCE(hwpt->domain->type !=3D IOMMU_DOMAIN_NESTED)) { + if (WARN_ON_ONCE(hwpt->domain->type !=3D IOMMU_DOMAIN_NESTED || + (!viommu->ops->cache_invalidate && + !hwpt->domain->ops->cache_invalidate_user))) { rc =3D -EINVAL; goto out_abort; } --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2046.outbound.protection.outlook.com [40.107.95.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11BD321C2F3; Fri, 25 Oct 2024 23:51:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.95.46 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900273; cv=fail; b=THpZu9xf2wTaQVoIhGFTF/bSk5UGua+FjnP9I60xRssdNyaeL6WSHQ6VTJ6KXxPT3GgNTYYhDGe57ahfo9a4uZKezfXIH0ip+mjFBs0EqCcw2iDwiQdrzJrlGrxEPdv0Dstm/9BuPd3ucwE2E6vePgNKiWir+Fkjh+NEqleVrcw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900273; c=relaxed/simple; bh=HpqTs2OCbl24wRfwf4gdplJz6Ywx4+00k9/ObzFdXdc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ohorxtwti9k+dG8c/2BJouUWN4PyfFo6/U3WBX60YW1lZewYkkEP6k2tVT0NY1+SNruyIwpnnna3D8Z2vETc1iDnWKUhtZO25Ik5VKy6OJen/Ov82EVGlcYIwci7vZ0S5zl6J99xSQ4qI1V8kfgOVbJTMLha176E4rJRyPUqWyY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=asdZxB+Z; arc=fail smtp.client-ip=40.107.95.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="asdZxB+Z" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KxiDr3WRUoJykaYyN+5GusFOKmhJz4WONkWEDgLw0G2H8HWAXY5Q1P92sZycD2dgA25Tjq6h/csb3sYK+NBCXr9yOb/6cRm2cRaCJoFfEESMjoFsxErFMr2db2imgiM6r0ZSmkXhhCSiyQPrspbJDTezSzCMMibMrNRMlH8DsVbEgZwaiJlhTBCudsbn/HHVgX314Rt3rR8lZZI3XNDkC7wGiEqLfcWrdBxjpD2lHj6uhWJFFdhUFqxLIaNmNRayL7cFrHgS8QBq935TBLQNtudWvG499Y27a5UyiwIM9CBByvqGK9pz7TbDE3+RhrGsfMqPbeCvI3krqWtarMMAyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=M5xvtaY7clknzZUM/12glWweJr8m63Ne68v3ESXh+c4=; b=i6k9R7hhbVuWFm1sD/FGEhwAxNK3g9dXreTr/LRRvU/zQq3dkkHl6jC+4qAC0umZ2bRljgbyki6YjZDritaIGysCJX8Lz955jrIy5Hsuu+xi9/9rTNp2dbZ7f8f4fwyHUJcRcAClI4rDrZDixUMoT2yjuE9rp4slvM2FCff60xwwbE2kgUENrNRWzD5/hmoQilosbN2raiiIDJerRvz9Ftkc9QLZyDArQhcxry9LYw4U7vYLL4l+syoYaR6yGtRZxT9QmRm6TG9/xSfTi9nRtPv8K1aQBZ1heTaonwzMIwX3ZUxDwujSR6HDLjHBGS+9pg/58FMUGpc94jEZUpYxkg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=M5xvtaY7clknzZUM/12glWweJr8m63Ne68v3ESXh+c4=; b=asdZxB+ZFORHPmh21bSJsPCUb+C1zy/y+fpre7/zP1JASRWDRvrs7uY8Kv6ftr8nKYyGf5Omq+S/NcR1p2xmlNuyXVeFr9i/PNwGZOVa0nA6s3n3iRHyYtYNrNt8eD/lv1a6Yu3rCL+UlOChK+pD0k2at3QMYCBSlfz9Zxg3CdVk701FMcIAhVtBD4Gu6MxEmd6MebHo5siE9WLyWYBcbSPaxHywmgJs3+L0sqHhg+EIvCkWflIWMgAqD4IEaYkr0MDkopGXw7g4rPP+8qonGCjDMlb/O/hljxj1Y62qaFAtLa/m25GM6o8bR/2t0XR5CHRnh2TJpjCOrkJSPuJFSA== Received: from BYAPR05CA0092.namprd05.prod.outlook.com (2603:10b6:a03:e0::33) by DS0PR12MB8456.namprd12.prod.outlook.com (2603:10b6:8:161::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20; Fri, 25 Oct 2024 23:51:04 +0000 Received: from SJ1PEPF000023CF.namprd02.prod.outlook.com (2603:10b6:a03:e0:cafe::73) by BYAPR05CA0092.outlook.office365.com (2603:10b6:a03:e0::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.8 via Frontend Transport; Fri, 25 Oct 2024 23:51:04 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:04 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:55 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:54 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:53 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 05/13] iommufd: Allow hwpt_id to carry viommu_id for IOMMU_HWPT_INVALIDATE Date: Fri, 25 Oct 2024 16:50:34 -0700 Message-ID: <6b8bb8f2319bf26ead928321f609105e4e5eecf4.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|DS0PR12MB8456:EE_ X-MS-Office365-Filtering-Correlation-Id: 666c01af-2ce1-4125-6306-08dcf54fe366 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xg6YK6l24WISqCsi5u3fs4tN8/XcFjP9sM+WDeXKv8xTPRw62AKtTmJOtAUW?= =?us-ascii?Q?GYb3PShax5+OQhqnJuCwJNDQvAK60VzvqqMLzBy+CPuD9dsJjoEe20aM7JOR?= =?us-ascii?Q?PDSlxcDeBDaOC7CTuHv52lSPX7Ag7wfIEF8u+J4/xg0p0Op7jLdk9ihrvWNL?= =?us-ascii?Q?lT/jkMOSggOlY6GbrO1QRMvY8uz91h0WGSy8rZdTwLmm//HKdFk8RJQdhqBj?= =?us-ascii?Q?IEe3+z5CYJ5mSPa7hjL8RPXAbjwKR8+KenAMFErUq1KyV5RDLANnaH0mIhNV?= =?us-ascii?Q?GQVcPF7wcF1dEH6fstxmq4Ap+0vizkcp17AyvdBa/rNp++PUc+ScaDIsi2v+?= =?us-ascii?Q?4UQypmPngM1jBBXAkcN1/aR/F00wLqGbvQ7jALSEE0e7h+WsoA4kIgIGg/oG?= =?us-ascii?Q?jbIxlfDuhZirTzGdmJSCF/+OX0mYjQen1mouWona88uSXOGy88lrWkvhoezw?= =?us-ascii?Q?K9Ln8/g8XiJ9haplhlouCdurPe607YnIQsgV5YmyP1khOd8qrd6A3OhC85Zj?= =?us-ascii?Q?f93+snn/stzZHdChiyAu8Uz69c9aPW9UgiEJFZWmvvYr1Xpdir/EyttRDeTd?= =?us-ascii?Q?+jWMUT7J8S9V3gQ9lsQX48/xAHVMePpwkFSJ/wF7NRAuirpDpiGGwgmoPrXO?= =?us-ascii?Q?XchI7Bs77R6cIaaRXsycu/Nlp3Ems9xdNwKgh+d1wNYuSDzVzFS8zQaMdjMJ?= =?us-ascii?Q?Onim0thn8PZvZfk7Vuz++i/8dFTdYxtLAfKNDoPq+yGaEP0YDKJXWHPZM0Gc?= =?us-ascii?Q?wvq47ZgAc/f6IHWHzk01Hc9Tlo3l4APKczyL6T5EwbDti/mZHJT1tvJ30pDN?= =?us-ascii?Q?BZbyrXT0oP+BpcQmt+BCR2UkE76sadeSG0bTy+bGWlaKRGn+oKmCznhZupG5?= =?us-ascii?Q?GHvWBG4tsmBiXpy/tJvGWay3RSlKKis70iPAMYCaJrMfoRuizMi8+LY+RxdY?= =?us-ascii?Q?CKBbhU/i7/8FP0Tx5IDeoU80JZc6t41jsOQ3JCFgcuvc0nvUeMCDdsj4ngVT?= =?us-ascii?Q?ja67qTyi1jh3PmrRqawSflo1hwiFL7Xd1XLcbCsRDhHdUoOv6BQQCSaBgMeg?= =?us-ascii?Q?1JOwwEq4BN/K+TiiVStUDn8K+lr57QG8GIKkFfJ9SmuO1TjuB/b6IAR4tqNq?= =?us-ascii?Q?rmEmTxci4QwW4FGvezw/gMbZU6+fL7MeId4Pxyz2q7TAoPEd0f8zCHTe6lm6?= =?us-ascii?Q?xD1JQBN2VEjxWxRg0hnZ2iHCuyO4O6+Q915PVijgZEBZvK31tSNlIQK/ysLA?= =?us-ascii?Q?tU+hyr515VGwd98PuBRIZbCW3Ki4iuG9ksnTNAbrhF0FkCKthR/tM+7I/MrM?= =?us-ascii?Q?vRm9vTD7LXRQPlvOw5aEPV986yMPsiG7fuAQ8oi6Tyt4SBvwvepczITk8ON2?= =?us-ascii?Q?gJqBAK8DCj4xl22jUZak1Wrcnk21Zx/rVzYhqnmBE/nnqtDqmg=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:04.5814 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 666c01af-2ce1-4125-6306-08dcf54fe366 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8456 Content-Type: text/plain; charset="utf-8" With a vIOMMU object, use space can flush any IOMMU related cache that can be directed via a vIOMMU object. It is similar to the IOMMU_HWPT_INVALIDATE uAPI, but can cover a wider range than IOTLB, e.g. device/desciprtor cache. Allow hwpt_id of the iommu_hwpt_invalidate structure to carry a viommu_id, and reuse the IOMMU_HWPT_INVALIDATE uAPI for vIOMMU invalidations. Drivers can define different structures for vIOMMU invalidations v.s. HWPT ones. Update the uAPI, kdoc, and selftest case accordingly. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- include/uapi/linux/iommufd.h | 9 ++++--- drivers/iommu/iommufd/hw_pagetable.c | 32 +++++++++++++++++++------ tools/testing/selftests/iommu/iommufd.c | 4 ++-- 3 files changed, 33 insertions(+), 12 deletions(-) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index b699ecb7aa9c..c2c5f49fdf17 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -730,7 +730,7 @@ struct iommu_hwpt_vtd_s1_invalidate { /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) - * @hwpt_id: ID of a nested HWPT for cache invalidation + * @hwpt_id: ID of a nested HWPT or a vIOMMU, for cache invalidation * @data_uptr: User pointer to an array of driver-specific cache invalidat= ion * data. * @data_type: One of enum iommu_hwpt_invalidate_data_type, defining the d= ata @@ -741,8 +741,11 @@ struct iommu_hwpt_vtd_s1_invalidate { * Output the number of requests successfully handled by kerne= l. * @__reserved: Must be 0. * - * Invalidate the iommu cache for user-managed page table. Modifications o= n a - * user-managed page table should be followed by this operation to sync ca= che. + * Invalidate iommu cache for user-managed page table or vIOMMU. Modificat= ions + * on a user-managed page table should be followed by this operation, if a= HWPT + * is passed in via @hwpt_id. Other caches, such as device cache or descri= ptor + * cache can be flushed if a vIOMMU is passed in via the @hwpt_id field. + * * Each ioctl can support one or more cache invalidation requests in the a= rray * that has a total size of @entry_len * @entry_num. * diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index fd260a67b82c..5301ba69fb8a 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -483,7 +483,7 @@ int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) .entry_len =3D cmd->entry_len, .entry_num =3D cmd->entry_num, }; - struct iommufd_hw_pagetable *hwpt; + struct iommufd_object *pt_obj; u32 done_num =3D 0; int rc; =20 @@ -497,17 +497,35 @@ int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) goto out; } =20 - hwpt =3D iommufd_get_hwpt_nested(ucmd, cmd->hwpt_id); - if (IS_ERR(hwpt)) { - rc =3D PTR_ERR(hwpt); + pt_obj =3D iommufd_get_object(ucmd->ictx, cmd->hwpt_id, IOMMUFD_OBJ_ANY); + if (IS_ERR(pt_obj)) { + rc =3D PTR_ERR(pt_obj); goto out; } + if (pt_obj->type =3D=3D IOMMUFD_OBJ_HWPT_NESTED) { + struct iommufd_hw_pagetable *hwpt =3D + container_of(pt_obj, struct iommufd_hw_pagetable, obj); + + rc =3D hwpt->domain->ops->cache_invalidate_user(hwpt->domain, + &data_array); + } else if (pt_obj->type =3D=3D IOMMUFD_OBJ_VIOMMU) { + struct iommufd_viommu *viommu =3D + container_of(pt_obj, struct iommufd_viommu, obj); + + if (!viommu->ops || !viommu->ops->cache_invalidate) { + rc =3D -EOPNOTSUPP; + goto out_put_pt; + } + rc =3D viommu->ops->cache_invalidate(viommu, &data_array); + } else { + rc =3D -EINVAL; + goto out_put_pt; + } =20 - rc =3D hwpt->domain->ops->cache_invalidate_user(hwpt->domain, - &data_array); done_num =3D data_array.entry_num; =20 - iommufd_put_object(ucmd->ictx, &hwpt->obj); +out_put_pt: + iommufd_put_object(ucmd->ictx, pt_obj); out: cmd->entry_num =3D done_num; if (iommufd_ucmd_respond(ucmd, sizeof(*cmd))) diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selfte= sts/iommu/iommufd.c index 93255403dee4..44fbc7e5aa2e 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -362,9 +362,9 @@ TEST_F(iommufd_ioas, alloc_hwpt_nested) EXPECT_ERRNO(EBUSY, _test_ioctl_destroy(self->fd, parent_hwpt_id)); =20 - /* hwpt_invalidate only supports a user-managed hwpt (nested) */ + /* hwpt_invalidate does not support a parent hwpt */ num_inv =3D 1; - test_err_hwpt_invalidate(ENOENT, parent_hwpt_id, inv_reqs, + test_err_hwpt_invalidate(EINVAL, parent_hwpt_id, inv_reqs, IOMMU_HWPT_INVALIDATE_DATA_SELFTEST, sizeof(*inv_reqs), &num_inv); assert(!num_inv); --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2044.outbound.protection.outlook.com [40.107.223.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4912421C2E7; Fri, 25 Oct 2024 23:51:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.44 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900273; cv=fail; b=QWg5sEXm/2TCs5W/ruqwYmwEVXPD6wGB4xLJlLonhbW8tAZ78uYkOoSLRc5excDNZlkK7iB8aBDAwd85DnU8A69AhqwjCAZq0scnlB7bmbEoW0rr0/FhjJTQ32WGJhUdpHioxn5VrCjOJe1++LymxeYp6C17bJ+B0gBKOPhwm0E= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900273; c=relaxed/simple; bh=9ULRXjb1t90r69U4kVFtxEzZ0bUWoxzjiqhBoNawn4s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gifn/hj/Z+K1Nxvgh3ucKl+gyVQFpEI5kAd9Z4EnGQGsuUfdP6YokL4ptP1bi93Rq9gCkYf8vmcbtH0bF4CLvHHk8mDYJiaIAh47MV1a6/OZuIDsvDyYD8OLn/fkYgQzWVsQeKzeqa50SFWZ3R7JgAbI30rwbPjhyDJp8iywHTk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=WC3ZNhRj; arc=fail smtp.client-ip=40.107.223.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="WC3ZNhRj" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=oNqk48yiD0fGrVRtbqXFjDeK4ToGc6fwLG4f+ZEF4ruBiA9F0j4JUf9ukXtxWE0M0nxM+t4lrWG941nCuxfKbomh2nRqeZ4gyPy/J9bOp+1FhzMeMI/ptkFobnydC6c8MJjkdn+mVReBi3yFvGrkUDPRAzFnSFVGa5po/KkgMptEpKQ0ShktqRXEiG8VPkR1UQGstvsfkVv4NvjHOef5+V3h/SOjQU3hRGClEUbvoJw8GpXxWy0OtQM2FieqVkeiyrwLBdsKrcW22F4QQjVGZSDxQMTD/klNhbj00dkv3FwU6qnoNkB+ToVMvx+1EQNN9J8PFZkgMtKNQV5Dy9FIkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=qmItsekwfeO802HIZU+t5OAf0G2DRhEQ1I8e0cO9Lcg=; b=HV02MMKvCIigrfNZrDHocRE+1RRzPDvS7TroPyikf9ztaB+5pNUSYxjBqPORb7cKuWsZFt3uLla/BB0T+iCinMrQqo23XPWReiQcPEWAsKv6rbnPk4QxfgaCXCsxTc6sZmA79iEOji057aN1GnxENIOaK1S+vVv3VPw+JcB/wfc2DJNYGk7uHZSfO+Vakrt8U6ze6uY9rc45wahIBPFIqViqeHETFLpZWjrdYFEos7JC+zHalQ3IAhbiSltpW5RhMR7fCmBp8uZSuz5Btz/AtE3/FdzFCDbreo7mWR9ev7PL1WJSZTHgQ5/3uObnmuBF9i2fVfKwmZw44Yh+8+y65w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=qmItsekwfeO802HIZU+t5OAf0G2DRhEQ1I8e0cO9Lcg=; b=WC3ZNhRjnHp5YSAsJ6hB1Y1S6x7xM1xOqa5/oKXyan6c0INyVFEQXpd595JFACgO6Cu4GuMyFUQQqnDnvVK8Rz4KKztUFgGnIKDDYVLZOajgU3FRd7hBqFAdk30xnJu7Tv4U/Au1sn/BzdpWtU/ZhJEF85ZXH9/ySZyl1KienACopLcUIwDKTOHDoiTNV/1NoVNiNT76L15FPiuwllVAHq7kjipz8hz+6XScCpTvUZGnxSXpsMobJoAx9heo5/UXGUihAcLLvyO479Mb3aDCQr2qpqtaCL+5cPa25eT7FmE1KJhVizzZKoUX/TCrVy+xzzqO69AWsFG2WNzVrMajWg== Received: from BYAPR05CA0105.namprd05.prod.outlook.com (2603:10b6:a03:e0::46) by DM3PR12MB9286.namprd12.prod.outlook.com (2603:10b6:8:1ae::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.21; Fri, 25 Oct 2024 23:51:05 +0000 Received: from SJ1PEPF000023CF.namprd02.prod.outlook.com (2603:10b6:a03:e0:cafe::2f) by BYAPR05CA0105.outlook.office365.com (2603:10b6:a03:e0::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.8 via Frontend Transport; Fri, 25 Oct 2024 23:51:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:04 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:56 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:56 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:55 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 06/13] iommu: Add iommu_copy_struct_from_full_user_array helper Date: Fri, 25 Oct 2024 16:50:35 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|DM3PR12MB9286:EE_ X-MS-Office365-Filtering-Correlation-Id: c41ae62f-8913-4f9c-6040-08dcf54fe3a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ChXZONn76KBOjkwoLR5vTSqntVxZQW2paeEF1wk+QUyAvO/l1034OpnrN+Qt?= =?us-ascii?Q?JOcg8OD5fjh14H0dHYdVY7Mz/N1NpZLSX6MhKVwaWWB1Kvl7jP2HxzIWrs8j?= =?us-ascii?Q?Xnzxgr9D7837fdPs1LXSttYHTPQNDmLyAjxedpKoNvIQcffaPpfWZYuf/m0b?= =?us-ascii?Q?8az/McJiUwzUdAglNbxYQU3EMt77QxVaVhrdtJ22f4USRiZx9KrP4IIvwHJ4?= =?us-ascii?Q?XlK7IAXBQ8qOh5tURq6lrzw217eU3vBgsClufAgGjRQOVYi83XOYqKWRUesg?= =?us-ascii?Q?XtxKKFb4d17L4JAp47eKNH9ELHwzQ0wfR9XhxxR3xL4JSYw5lW8LRxSKYb5v?= =?us-ascii?Q?/ARPGulEu8oJQAr2Qxv25r7OREflmwqoZ+NKJnsDKQOxfpghpiPvNIvOHck4?= =?us-ascii?Q?mSdnyVJlczQoC+BSDYPltR/xYm4d5N0/VeHJU8wKGnkY44CPyHaFPxq0WZqB?= =?us-ascii?Q?5/vAEIdvkSCH1ev7oLhdOzXbShF7F3YRylWkhL++ih5eS6vppMxNRIgq72KU?= =?us-ascii?Q?yeJq4H/0hXDDZTtcuIU2OhzZzAMswBO5hCnIuhaL0OT3hBTeA1EGFuPhWuVU?= =?us-ascii?Q?1mg++eQTwMDl9fuDg/JYO4Y9wJDCH+T7wrcyJkz+DOqdgwn0bi4d3xWxpRFl?= =?us-ascii?Q?CbcjLpJwHjURm7x0OfQnvLcbukFPriDNq5gAa5dtkYOcnw5TBWj97wPNaFPe?= =?us-ascii?Q?gi/oHqCWZoNjdy9jHdtHoLFVdzcqGaOfVi//CpvrfG3i9ZhCLKZqnB4dFyKI?= =?us-ascii?Q?Xoa2WFrZH6tQh46iCXGbvPBIdTMx3AhouVC4BIarjxkncwDFsVPww/D/U6FR?= =?us-ascii?Q?hacB7Zcf94UCkM4eYyZGUbgHaaDh1+tCyYPkMmLSFIyE7Mki1ju3KSyXuAdl?= =?us-ascii?Q?ZH7yjjkcqk0o5jlXwupeoS8X/xz0eib2VkxwBNJogRBIdkGLCWzjSlT3aedN?= =?us-ascii?Q?kutoqZysls9cmz7RLCs0TnVL5wacnj0VDreywmN0FjHFednELyHGDJXu1Ozb?= =?us-ascii?Q?nZapkJI2aFnojiTGVLFjSmq8ILnQN5DVg6C7lb94GtSzcWmxYHLswUrooFin?= =?us-ascii?Q?kPWP9lRkmlOhcGNQ4jyPcj78tFWMmFW7ha0Isxh1XlT8Gw1stbeodJvgaPXj?= =?us-ascii?Q?b5VQmMK+tCmxJLTg5f2OUMWYTDlP30KmKFYn4Dc6U1s6sYuvTPGd0i8yWiWJ?= =?us-ascii?Q?3jKUFe7lZpLRGsr2Sir9w6hgMPb4MMFu/PTdTVtCL8BDaoqundsvgzLVviq1?= =?us-ascii?Q?R/tX2HM+avK5mQm8H6QdSxrSdG7lUTYIoU+ktM47LF/7L0SAOGRCG2O86EWE?= =?us-ascii?Q?bmdyiwlqfLyrwKLhFop+Qprf60aOjltn1aaJtK/UFDlHxHUg75GTX8MFpc8M?= =?us-ascii?Q?HaQgbhail44z6OWv25ptreWry5qBJB1rNIPDhGtO105yoxZU2A=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:04.9721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c41ae62f-8913-4f9c-6040-08dcf54fe3a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9286 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe The iommu_copy_struct_from_user_array helper can be used to copy a single entry from a user array which might not be efficient if the array is big. Add a new iommu_copy_struct_from_full_user_array to copy the entire user array at once. Update the existing iommu_copy_struct_from_user_array kdoc accordingly. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- include/linux/iommu.h | 48 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 14f24b5cd16f..3c3d5d0849d7 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -493,7 +493,9 @@ static inline int __iommu_copy_struct_from_user_array( * @index: Index to the location in the array to copy user data from * @min_last: The last member of the data structure @kdst points in the * initial version. - * Return 0 for success, otherwise -error. + * + * Copy a single entry from a user array. Return 0 for success, otherwise + * -error. */ #define iommu_copy_struct_from_user_array(kdst, user_array, data_type, ind= ex, \ min_last) \ @@ -501,6 +503,50 @@ static inline int __iommu_copy_struct_from_user_array( kdst, user_array, data_type, index, sizeof(*(kdst)), \ offsetofend(typeof(*(kdst)), min_last)) =20 +/** + * iommu_copy_struct_from_full_user_array - Copy iommu driver specific user + * space data from an iommu_user_data_array + * @kdst: Pointer to an iommu driver specific user data that is defined in + * include/uapi/linux/iommufd.h + * @kdst_entry_size: sizeof(*kdst) + * @user_array: Pointer to a struct iommu_user_data_array for a user space + * array + * @data_type: The data type of the @kdst. Must match with @user_array->ty= pe + * + * Copy the entire user array. kdst must have room for kdst_entry_size * + * user_array->entry_num bytes. Return 0 for success, otherwise -error. + */ +static inline int +iommu_copy_struct_from_full_user_array(void *kdst, size_t kdst_entry_size, + struct iommu_user_data_array *user_array, + unsigned int data_type) +{ + unsigned int i; + int ret; + + if (user_array->type !=3D data_type) + return -EINVAL; + if (!user_array->entry_num) + return -EINVAL; + if (likely(user_array->entry_len =3D=3D kdst_entry_size)) { + if (copy_from_user(kdst, user_array->uptr, + user_array->entry_num * + user_array->entry_len)) + return -EFAULT; + } + + /* Copy item by item */ + for (i =3D 0; i !=3D user_array->entry_num; i++) { + ret =3D copy_struct_from_user( + kdst + kdst_entry_size * i, kdst_entry_size, + user_array->uptr + user_array->entry_len * i, + user_array->entry_len); + if (ret) + return ret; + } + return 0; +} + /** * struct iommu_ops - iommu ops and capabilities * @capable: check capability --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2071.outbound.protection.outlook.com [40.107.223.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D25F6214409; Fri, 25 Oct 2024 23:51:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.71 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900271; cv=fail; b=duJrifPN7AykqbrblD7/kCuagl3kYzhUynJFE079lpLjwRvgKRsXy37c7betkoid+pxPtn+hxlCZYrmT3ObrmdizcwN218NA1kYxgrp5TEDPqinDGYzy1zinGW3iuaN4w4mLdBSctfn3QfiAxnq1XH/OTqYQJSxbQb+MhTo02PY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900271; c=relaxed/simple; bh=42LeZJ3xvFmYgLbihdsh81s1wMRtIgrr4/9tlzTCBIM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nZ4wV4fHu7J69k1oLxhEAaoUJR2oPzkLtMP0zstfIKhjfZrP9GdiaRTAuGGhWSwJoNfTpukiEINNyPPZo51rymPjrue8oYR6TWEUfEq8KsjQAVCIiE1JPp4IIMt/dxO3bM+Os0PvO8ubuYWTZNTrFrFinbS3Boc6ZdXgVXBKI+M= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=E4eUZsv5; arc=fail smtp.client-ip=40.107.223.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="E4eUZsv5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EP/MbRAMz5EG4tc5IRYiyITbZlDEaDLjwSAhsFChlvxWr28GLVOGwFMghztZLfMBJcqfohgJdvRVPFhog9hYwE6b/SlUzQEnXNoywZFiamiff7xH2PXI0Gl/5BEWSgzIeKy13Kw9I6wun2F8HUHthq83GEsfz2kcgebRduFnfjQpxsiMkMtKw3eu+4XZLCqEJRqMpffT6XgXuSpmFQU11tljeeQMQtfuhW/B4qEuaW7aRjSDkcK7441PKm+bCgnly9DNznyonjIfiajqd0Ok57wk/RP5kbnW2mDtbdybREPiUS43M8NsbU4WoxgyTXR8/kC2IZa6QOih2a6bJUPAcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lvlBSYEvWCG0hAnIUYc10bbXD8NGghhkWHcflXNXcto=; b=QH+nWpHH6b9GImCh9EUE68IJ/Q7lxGG4J1GlB5CpubKbntdAjG80RWOdD4ntAx1vaqzopU9NeJGCI8nrqyelj5fp1nMD6XlQuG1/yHgW70KPAs5RjCh2zN3MOKuWkcKUbUK4Wzq+1wCs4QcU0srtj9PtVPJGBTB/5Seiv2RqYyDNI9FJzuBMTNlRBVbHTVkVTAvBMIAV3b5ODZGIE2CEcuHRrQTVqi5EBAv5TFgL7bwbXVLylteijcuWWEnaf/ZkzmvDqs+0ml7Cdtn3kn0IBQ0METKazbe1nZiuymAY2c32mfvDn6ji+B1iy7WANyhp+G44iLOJdupCcfX/NGfipQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lvlBSYEvWCG0hAnIUYc10bbXD8NGghhkWHcflXNXcto=; b=E4eUZsv51JungpLM2GZZztmIb9hCivFZwCdp+iK/9SSPSNjA3gSUiraLNsi/532FieYehYOTGO+DeYdHJwcuyuveLEGHLlMwJhlbkGL6Jxu3LjDRmm7+nqKYUBgQVeqBLoqDAADEbz5sbW5vjT9NeLLLK3P5eV4R6467gMYwKZ4VRF14y3Mg19ZAaV7UkZMGnYQKjn1dI8FqKW1LtkxM0qygDP+/XNPAbvNvwlNPfN5xfEIQwfk3TB0g6AoYkntFSA/MYYkwrjyW5OvUwMSlF0BBMhIywoG3RwC/N0JWm8/ebpJZpxu+lUsZ1vVCf6YOOebGBeeftzDCHLMIRGUzdg== Received: from BYAPR05CA0100.namprd05.prod.outlook.com (2603:10b6:a03:e0::41) by CY8PR12MB7731.namprd12.prod.outlook.com (2603:10b6:930:86::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.19; Fri, 25 Oct 2024 23:51:05 +0000 Received: from SJ1PEPF000023CF.namprd02.prod.outlook.com (2603:10b6:a03:e0:cafe::38) by BYAPR05CA0100.outlook.office365.com (2603:10b6:a03:e0::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.8 via Frontend Transport; Fri, 25 Oct 2024 23:51:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:05 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:57 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:57 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:56 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 07/13] iommufd/viommu: Add iommufd_viommu_find_dev helper Date: Fri, 25 Oct 2024 16:50:36 -0700 Message-ID: <384f7b4333a1f75da09e390902b8f82be21a0dd3.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|CY8PR12MB7731:EE_ X-MS-Office365-Filtering-Correlation-Id: 006ed9b0-b188-461b-0c50-08dcf54fe412 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?PzRHX/1AQIgXyKxvdKk4NPzmvDwk5JqMazn8tAaXnNEgTY9tikJf80s4bo4X?= =?us-ascii?Q?VC1m6BeNJQkFmV+AZRu0RTZZGoX9l9WWAc3/5pE9iCBH1Xpkv+3rJePaVybo?= =?us-ascii?Q?3nRNayvkn1FwIZxgEqpqlkK5iJDKpTqfA4501bm47pxQnQqSYoleaDSaVa16?= =?us-ascii?Q?WzNaN+m0geQmpppJHVOqvXHTnau0mMoJjs74scbRqsczYl7P6uvzf6GFAYN/?= =?us-ascii?Q?dWNqfxO5DDod2yqxFXhREYmZcu+PADeKw3eA+Nn2DdzXurobcyeGbjs+0QKx?= =?us-ascii?Q?mDNlB5cjo2d5ZjD+3f/byUfHlkKxNVO+ymaoQSZIoxN7n1JeVp3CKEnaVGCd?= =?us-ascii?Q?b451Adkfc56X50EoeSvio7019fi7iZeujB8XnH3l0tUQSNzD3qY/cwtuo9Ps?= =?us-ascii?Q?PLt0FsrDHuR6/PnyWv1EQQQcKvfTuU4S63unQyH8UpqQyAnFTS8cNfbyrIbf?= =?us-ascii?Q?6ep0sGX2pWc7bSIB5nUNMsX5td3Nw3XkGhCFXxkrJxLyJSMXurG5wTLePJ75?= =?us-ascii?Q?emskMWBrb6XwrnwW1+vMMZBhC0F4B9Enn1pwa3vf93pT36WK9yyGvh9H6ciR?= =?us-ascii?Q?f6/iaIOUE8RBteQTlUQfRWC3UDS7RatPM5uS9Rr5M0qrqMlPgBp/fstU+x38?= =?us-ascii?Q?XGyDnd1qNysHe8JVfL7xOnEI9dFb00poTnRenoxkAWFD/BZJ7gCEqF5d42DJ?= =?us-ascii?Q?QvH8ju2jIgdGNp28m6BE3WZggYWD+vm1R7qW+DrqBsEJjUv6tTzvvjS3XrDk?= =?us-ascii?Q?nPubuUdTxaWtTbTiHteU5EvG21cY43jYDm9XSWiFlGCbD4kSyKUh+14P2p8A?= =?us-ascii?Q?AOWTb2bD+W9zxC4Q8hBLCuvckj120vzJqaUX1jJ+Vk5hodt2++KbYMmASjwY?= =?us-ascii?Q?WbWkkU9WA1P8sp2uHp3Hyo5d5BJAdZfC+s/k9NNC9khTLIl5LxDYVdoXvQdC?= =?us-ascii?Q?w2Qsbt2micKNa6C3ET5FScRwSaHxvV04/Uc+M3HmqtgVUJqnEnGb5Ak3AaTG?= =?us-ascii?Q?8Tah73dLgOF/aG121a9Xr4K1bM+2Lxf/kZ8mAPcKOKh/+hfvRuEwYm8PO53m?= =?us-ascii?Q?AdJSc0nGzhh/WRh8cm2BKXIhroaPMJL9TPrxPfTQLLI81hFbmF3+Qnn41wQ4?= =?us-ascii?Q?wEx9Krss9XOcmOUba08PXXTUOIlr7c2PLqxiqyOkBAN/cqRGxRmLaq55NCBO?= =?us-ascii?Q?ojOWFsOjsqHkLyHVs9HmsJ8tzShkxkUaR7V+SzYKTmbSzQ+1JWNmFw33G6ND?= =?us-ascii?Q?+YKleJUBrFdgKyKeB0ZNpkEHYhu6t5NaHBzgfI8qEvvWZvfVHTCmMZPVDdeJ?= =?us-ascii?Q?IWhRfpgKiraQ8u0vM9QjUfTbDx9oh4dYOTNevALzqS/CVCBoNLvtwTIejr4k?= =?us-ascii?Q?r+KDYQJdHRFQsWEPOi2KdxCg1nluRjcgMsPyI7P7vF8EL5hUdw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:05.7064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 006ed9b0-b188-461b-0c50-08dcf54fe412 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7731 Content-Type: text/plain; charset="utf-8" This avoids a bigger trouble of exposing struct iommufd_device and struct iommufd_vdevice in the public header. Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- include/linux/iommufd.h | 8 ++++++++ drivers/iommu/iommufd/driver.c | 13 +++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 0287a6d00192..dc174d02132b 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -184,6 +184,8 @@ static inline int iommufd_vfio_compat_set_no_iommu(stru= ct iommufd_ctx *ictx) struct iommufd_object *_iommufd_object_alloc(struct iommufd_ctx *ictx, size_t size, enum iommufd_object_type type); +struct device *iommufd_viommu_find_dev(struct iommufd_viommu *viommu, + unsigned long vdev_id); #else /* !CONFIG_IOMMUFD_DRIVER */ static inline struct iommufd_object * _iommufd_object_alloc(struct iommufd_ctx *ictx, size_t size, @@ -191,6 +193,12 @@ _iommufd_object_alloc(struct iommufd_ctx *ictx, size_t= size, { return ERR_PTR(-EOPNOTSUPP); } + +static inline struct device * +iommufd_viommu_find_dev(struct iommufd_viommu *viommu, unsigned long vdev_= id) +{ + return NULL; +} #endif /* CONFIG_IOMMUFD_DRIVER */ =20 /* diff --git a/drivers/iommu/iommufd/driver.c b/drivers/iommu/iommufd/driver.c index c0876d3f91c7..3604443f82a1 100644 --- a/drivers/iommu/iommufd/driver.c +++ b/drivers/iommu/iommufd/driver.c @@ -36,3 +36,16 @@ struct iommufd_object *_iommufd_object_alloc(struct iomm= ufd_ctx *ictx, return ERR_PTR(rc); } EXPORT_SYMBOL_NS_GPL(_iommufd_object_alloc, IOMMUFD); + +/* Caller should xa_lock(&viommu->vdevs) to protect the return value */ +struct device *iommufd_viommu_find_dev(struct iommufd_viommu *viommu, + unsigned long vdev_id) +{ + struct iommufd_vdevice *vdev; + + lockdep_is_held(&viommu->vdevs.xa_lock); + + vdev =3D xa_load(&viommu->vdevs, vdev_id); + return vdev ? vdev->idev->dev : NULL; +} +EXPORT_SYMBOL_NS_GPL(iommufd_viommu_find_dev, IOMMUFD); --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2043.outbound.protection.outlook.com [40.107.243.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EDEC215C70; Fri, 25 Oct 2024 23:51:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.43 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900272; cv=fail; b=YiQInhXnHW45TYMcK34RPdvRF8JJnDaipaUPmxjzz/aERbP1uIkUJQJPZEaBAIk/89HHGP649QlcsQ5AOSNKAJ5S2ZTsubjiERsaRujEAgLujGtXeJmv7OGoQdzESo/y+jVD9Qcc544yaoUGEwSt0wo0ZxzeX26u84EP4j9RJ1o= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900272; c=relaxed/simple; bh=IGTx5FrmS1qBGXsG+jeNnQdJA7XqIrpOoSKctvM8QIU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f8GCoWITsDo3IQ5u/4PaKZRwbJgPND+EEOjmsOkAh7p5RIcEhU0rQH5QcHiO5wisGFQA40RmHO4pOldCLkFRJEMtK0SHTHh9aoMxwgO6VEb7ZU0P1zuVdo9zXeIPjY5iWL3cHcFawYEYLbrKH6zn+iJOn6FRdZyScGQXbBSl3LU= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=FhMqh2rC; arc=fail smtp.client-ip=40.107.243.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="FhMqh2rC" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Yx5OtB+fB4XB51KswsFc/1hiKnAgPP9mWMKMyX4f2fX4D4lJq+UpO2ONiqVGiY5wqX+3gQ0/SnEVvIiosNO0hlCjOU1d+X+SxazEmgHr9KYqoZLmWDUSAkrHh+zLXUcgmB4aFROPl2N51wyUdwYt+ymgatH8TyN0abRKayU7+haDVyu/kU674Tm9mthMAmQc7kd1hGOsCF0TJkJ7X0Vopclq1pNIPbAPo677Ld0tuad4uoOnRK5fYR8sKxwGjLpJjaVfxTEAn4zKJ5LNFGfthk7XQMEjY+0HBJKq/C4PuYokWrp2xn/ZddAYKd50pX48stcGOQoVC8IZxBTz9gOi1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0nSBZ4LqKfElNvT7voQBCikyGQCQjd2n14NLCSZ5K/M=; b=mzJXl712WopqAvdOazTeOGqTBPEiLITPH5ImFVo/0tuNvosaPAHccJVPe6JGsAEEeo4DS3roJ36EJCAFa6tReCJjXqpmju9plb4TsTXOrIT1/+J7dAWJg/ur/soc1DbI4EbJsSTZzoSo6b896LZdy6HR/G5rzrPxxoBPhPXKc4AW5zJl8V/TjImir5qRxnAoXCQIxdp69La16eHtGejpoPiaYOKKi7HadMgQkjWVj1jpxdjj/KgP00QIKzln/TNEWKRdQlizV+Cg3iLk1HL1rlMYsdlw+RUHXMFLgyB6YBduMT41tCV3R/z4dqzfdGt7xPnCAK/W4TdcCG9XYuToVg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0nSBZ4LqKfElNvT7voQBCikyGQCQjd2n14NLCSZ5K/M=; b=FhMqh2rCRH3WxGx7Sv8HX96gLmFQRI7KaBi/KEgcplPr8a8JlQNJnvEHjRZ1vUaFY2p+BzPyY/s6C+Ph2eINFulSeUqG6gEiUIWapw7WyOfoE3Vn2Y4v/qF1qN1U4UYRxvetOZ5MWTlneJXqCCiVtvGlISauGkfvj0nmc79Epa5sXAGs3RJV3jm/ixJDCpLSJ0TZQfzXAHYZHa3PY/ipa5CJ6+qoQu3l9dSXnaSfPOBChkRoHmhoAjReO4kwLED5tEdu6zqLVC7c0CuqHwnLYwXsxiHPAWX4IQow7oAmmjerqxXyBh//uPnliwZ4FxM02QiiFGo7O5TDap4IG24gdw== Received: from BY3PR10CA0011.namprd10.prod.outlook.com (2603:10b6:a03:255::16) by DS7PR12MB8084.namprd12.prod.outlook.com (2603:10b6:8:ef::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.21; Fri, 25 Oct 2024 23:51:06 +0000 Received: from SJ1PEPF000023D2.namprd02.prod.outlook.com (2603:10b6:a03:255:cafe::eb) by BY3PR10CA0011.outlook.office365.com (2603:10b6:a03:255::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.19 via Frontend Transport; Fri, 25 Oct 2024 23:51:06 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023D2.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:06 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:59 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:50:58 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:57 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 08/13] iommufd/selftest: Add mock_viommu_cache_invalidate Date: Fri, 25 Oct 2024 16:50:37 -0700 Message-ID: <6ecee6aff136af1a1b8c13adb0210a74c1974ee7.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|DS7PR12MB8084:EE_ X-MS-Office365-Filtering-Correlation-Id: d4f9598c-bf60-4542-abf6-08dcf54fe4b2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?m+MxbWh7CPFmMJhytnU1EkrO/o3S2e/+MYkgn/0YQZmroIBfxDk1ZhDSxksV?= =?us-ascii?Q?5ZVOxyxkaV1yLk0i21oGE39HfWClCcyDo+pYJJCs7+wzsrKn4/qRyVa7A597?= =?us-ascii?Q?+v39qc5a/CBDyGyh5cuNfen3csg/5kO+6dpvLE1SRmCLvwZvTBkgELdi3nhk?= =?us-ascii?Q?gPTruumerS+rFIna5Hw1agvD35pI1LNn0NhlJ01scSjBSOqBFoDq1u5WC82i?= =?us-ascii?Q?xHbWphN6E94HNPBHdLzsD14ReHB8nV50CQ+oBL+9lin5Evcq93nUZU2rv6Cp?= =?us-ascii?Q?nLqPCKnSTfGoz32PrtS/Sz98WHt6F4JtQmsz/Pwcc1qwaQZdY9vDOR0QONc+?= =?us-ascii?Q?S0U611dJLSnnzEgcAzbNU816wPFQK0ou8wFqDBgpAV7m2w7BvP9WKS4mQTH4?= =?us-ascii?Q?QcrRJ+Kb6zbeNPVpywxW9tTIaOdnARhAjjexDcVs7clpDU6U9KuxP7LgiUDu?= =?us-ascii?Q?HINdhphFnVUlVqWL1etY1XchTeDwW8/TJPL1ujMepJ0U9Q0fx2DEM1Ggs/Uh?= =?us-ascii?Q?jJetWHqHujlCiko2G18ClDMljsIyy1WEV0MrQ1P4i42oeeO+eSkCYagyT5F5?= =?us-ascii?Q?35h7xi3iJ6RPhG5MXLkC0hSWl1IzGmT4+1ZaZA701TJVv7VG+pcSbZT4Prg6?= =?us-ascii?Q?lD77XLdNE0H3YJVa0N31YTRJc3sER3bFur/xBSjMAjQHAzNozhRia6kR1W8/?= =?us-ascii?Q?svgp7JmS08WCrQhR/DJqJwffQ2G9OngufmjbCVVTwyrpTi2zxF3RzsUZpM7O?= =?us-ascii?Q?kL0/iEL8Gp4M2jla5WjsrmV+bi1IjhMpW9kU/sdw5e2H2uPKxRKhrepjnrL0?= =?us-ascii?Q?nlWn7N66AZbEFEHr3gBiKHEGf8l7Kaf3bWmRq2x17UKbeQjs+k6FLhbWcoft?= =?us-ascii?Q?Eo5uWR8NuOYzSmizUTVmW3xf0afEAdZCtMpAOfsLkmkxFc8Y7mA3UtmMiQRA?= =?us-ascii?Q?pjYr6dvHTMKzVh0t6J1ZrQ+043h5+eib621W2T5ZfbhYslc4ay+Adz9QrSYm?= =?us-ascii?Q?lOio8ykyhod40DuI1XNWJdwwywzcU/jHHlBuHywy5t1d970W+YuZEK8gEqGU?= =?us-ascii?Q?2g/sox1VQJlwAUH15hunCChyS/Blog6Q58qiP8ETqRgsQTw+LhN3KXsXQ1Tq?= =?us-ascii?Q?XSSNV/LV198evGVScOvv7Y6vvmf6BgVmP6/OpAR4uitHZ8xM+Ysy7P2L+ceQ?= =?us-ascii?Q?iK8FxvK+HekkXQxnyH/Er83kKFUuBogShSMzXZtFM4EhZEG5s9DQ7cyfk4Vt?= =?us-ascii?Q?aE6S+Rrl4CB+I7fKHMnEljmP5mGp9Cc+Jb/17bRf2XRydQe4cQR+F+S3U3Fn?= =?us-ascii?Q?cyfXO+RrX/iiMIFdv1idnhECE2N/8lUrhMnc/n+1a/8AGcekUYQzqwcBJJp1?= =?us-ascii?Q?SZp8wO9wm2SDSwY1S4Ncucrw37YIX7ntMdA0UjAIoYPbet+E9g=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:06.7747 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4f9598c-bf60-4542-abf6-08dcf54fe4b2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8084 Content-Type: text/plain; charset="utf-8" Similar to the coverage of cache_invalidate_user for iotlb invalidation, add a device cache and a viommu_cache_invalidate function to test it out. Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/iommu/iommufd/iommufd_test.h | 25 +++++++++ drivers/iommu/iommufd/selftest.c | 76 +++++++++++++++++++++++++++- 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/i= ommufd_test.h index edced4ac7cd3..46558f83e734 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -54,6 +54,11 @@ enum { MOCK_NESTED_DOMAIN_IOTLB_NUM =3D 4, }; =20 +enum { + MOCK_DEV_CACHE_ID_MAX =3D 3, + MOCK_DEV_CACHE_NUM =3D 4, +}; + struct iommu_test_cmd { __u32 size; __u32 op; @@ -152,6 +157,7 @@ struct iommu_test_hw_info { /* Should not be equal to any defined value in enum iommu_hwpt_data_type */ #define IOMMU_HWPT_DATA_SELFTEST 0xdead #define IOMMU_TEST_IOTLB_DEFAULT 0xbadbeef +#define IOMMU_TEST_DEV_CACHE_DEFAULT 0xbaddad =20 /** * struct iommu_hwpt_selftest @@ -182,4 +188,23 @@ struct iommu_hwpt_invalidate_selftest { =20 #define IOMMU_VIOMMU_TYPE_SELFTEST 0xdeadbeef =20 +/* Should not be equal to any defined value in enum iommu_viommu_invalidat= e_data_type */ +#define IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST 0xdeadbeef +#define IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST_INVALID 0xdadbeef + +/** + * struct iommu_viommu_invalidate_selftest - Invalidation data for Mock VI= OMMU + * (IOMMU_VIOMMU_INVALIDATE_DATA_SE= LFTEST) + * @flags: Invalidate flags + * @cache_id: Invalidate cache entry index + * + * If IOMMU_TEST_INVALIDATE_ALL is set in @flags, @cache_id will be ignored + */ +struct iommu_viommu_invalidate_selftest { +#define IOMMU_TEST_INVALIDATE_FLAG_ALL (1 << 0) + __u32 flags; + __u32 vdev_id; + __u32 cache_id; +}; + #endif diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selft= est.c index 33a0fcc0eff7..01556854f2f2 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -163,6 +163,7 @@ struct mock_dev { struct device dev; unsigned long flags; int id; + u32 cache[MOCK_DEV_CACHE_NUM]; }; =20 static inline struct mock_dev *to_mock_dev(struct device *dev) @@ -606,9 +607,80 @@ mock_viommu_alloc_domain_nested(struct iommufd_viommu = *viommu, return &mock_nested->domain; } =20 +static int mock_viommu_cache_invalidate(struct iommufd_viommu *viommu, + struct iommu_user_data_array *array) +{ + struct iommu_viommu_invalidate_selftest *cmds; + struct iommu_viommu_invalidate_selftest *cur; + struct iommu_viommu_invalidate_selftest *end; + int rc; + + /* A zero-length array is allowed to validate the array type */ + if (array->entry_num =3D=3D 0 && + array->type =3D=3D IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST) { + array->entry_num =3D 0; + return 0; + } + + cmds =3D kcalloc(array->entry_num, sizeof(*cmds), GFP_KERNEL); + if (!cmds) + return -ENOMEM; + cur =3D cmds; + end =3D cmds + array->entry_num; + + static_assert(sizeof(*cmds) =3D=3D 3 * sizeof(u32)); + rc =3D iommu_copy_struct_from_full_user_array( + cmds, sizeof(*cmds), array, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST); + if (rc) + goto out; + + while (cur !=3D end) { + struct mock_dev *mdev; + struct device *dev; + int i; + + if (cur->flags & ~IOMMU_TEST_INVALIDATE_FLAG_ALL) { + rc =3D -EOPNOTSUPP; + goto out; + } + + if (cur->cache_id > MOCK_DEV_CACHE_ID_MAX) { + rc =3D -EINVAL; + goto out; + } + + xa_lock(&viommu->vdevs); + dev =3D iommufd_viommu_find_dev(viommu, + (unsigned long)cur->vdev_id); + if (!dev) { + xa_unlock(&viommu->vdevs); + rc =3D -EINVAL; + goto out; + } + mdev =3D container_of(dev, struct mock_dev, dev); + + if (cur->flags & IOMMU_TEST_INVALIDATE_FLAG_ALL) { + /* Invalidate all cache entries and ignore cache_id */ + for (i =3D 0; i < MOCK_DEV_CACHE_NUM; i++) + mdev->cache[i] =3D 0; + } else { + mdev->cache[cur->cache_id] =3D 0; + } + xa_unlock(&viommu->vdevs); + + cur++; + } +out: + array->entry_num =3D cur - cmds; + kfree(cmds); + return rc; +} + static struct iommufd_viommu_ops mock_viommu_ops =3D { .free =3D mock_viommu_free, .alloc_domain_nested =3D mock_viommu_alloc_domain_nested, + .cache_invalidate =3D mock_viommu_cache_invalidate, }; =20 static struct iommufd_viommu *mock_viommu_alloc(struct device *dev, @@ -779,7 +851,7 @@ static void mock_dev_release(struct device *dev) static struct mock_dev *mock_dev_create(unsigned long dev_flags) { struct mock_dev *mdev; - int rc; + int rc, i; =20 if (dev_flags & ~(MOCK_FLAGS_DEVICE_NO_DIRTY | MOCK_FLAGS_DEVICE_HUGE_IOVA)) @@ -793,6 +865,8 @@ static struct mock_dev *mock_dev_create(unsigned long d= ev_flags) mdev->flags =3D dev_flags; mdev->dev.release =3D mock_dev_release; mdev->dev.bus =3D &iommufd_mock_bus_type.bus; + for (i =3D 0; i < MOCK_DEV_CACHE_NUM; i++) + mdev->cache[i] =3D IOMMU_TEST_DEV_CACHE_DEFAULT; =20 rc =3D ida_alloc(&mock_dev_ida, GFP_KERNEL); if (rc < 0) --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2051.outbound.protection.outlook.com [40.107.237.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3EA621C2CC; Fri, 25 Oct 2024 23:51:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.51 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900274; cv=fail; b=u6sOx3l/yPukoveqbotDan9umEMKfk5VII2KWeA/KLAYQ5oPJFmwGoTXarpzqFA/qmvffHNxQCKOYJVYtlygD3y0ioQp/80G4hAbwDkoqCcAjMqKOaKY/uRWYWNFWTgATYrmxnCASlu2STjxY9hGWkSCWjSnjkh1YCf5Xs5AU7Y= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900274; c=relaxed/simple; bh=T+C0rUgAM9mbD6ZhnLQA5x4Dn9VRPK5ibas/YkbfQxk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IsAQZPXq5S20/zwPww08E6miBEXbx5oPjAxE4hRbv7tRoyYf+YQKcIPOOR/O0+uPx0S1iSzWHYmwzuVzUgRObOiB7rtWnxV3AS9zR3RslOCcFXKErjI3aVmOxYMA1hr/eLwN+VOh1pwFyKPA2sUuOgvjfukq3bnCD6R5GIAv7CM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=NWAfM/hQ; arc=fail smtp.client-ip=40.107.237.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="NWAfM/hQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=S93ehYv1fzP+oGzq+vZoFErv15Z3liSuHaDWS6lfekVTJwia4TMvKd0ReG6goIuxT7H76ywK/GxVkMoU2NXTHzMWz+VqMYQnq8kvs1lU8XWLs078U8cEOPJFNnlrTMOh1QJ1PGRIcZrANXQFk02Q4tFQgtwBmkgcE2a+0zSgni/hORSqPBXN6kjmrxq7dPgq5AGu6gRpyzI3NySvwSoxLmArnXnr2b57/+6AVubhB3+6PGopEwL9OD2NLmSjJOMlCtxfXX+GI1B4C8WHjYrv/t64prIhNrthMiLYD5kllJTaRyVpy+z7FmqG5nvjUQnF2+CBOt/5sXFrrvy4ejFQyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cOFjVVxa+45dNXcuwjARBQP7UbO9XNA94R1VE5QaRAY=; b=FCbf2hOyv9GY+nzcTEoFW0xYXfhsDmPKvz54v/ScqIomBlOb/bCZXKpO8ISdSSjGUMF7tiwXjAIMdFvGjAjFtJZzVuYR3y6afVpscoaXFPbg9KeNKBvU1YnFP5ptuLhorXCfVIw9DGL/6Ze3QCeSEU/vAz+uIFnUCojwI6PcpwicVMgxY81MEmb54SWwp2+IoufduCd+A6quyt2kwoDw8oLBZo7IFh0ni9OCD42bAnpxCVI59LHBXtsZ6PHIKarmOnjsBU1VjGs0JR0XUS+cIZRW1NgydgjzcaQ/hsJ4gECE0vmV9EdHsj371jUsEOT0UdS1MoH55fyu4XPudJrQFw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cOFjVVxa+45dNXcuwjARBQP7UbO9XNA94R1VE5QaRAY=; b=NWAfM/hQHExvleTnfxEMtqrD4gGyUWHmmP2jcjK+lhsZkxuKuHVhDA4VBApZYh1wj6w7KmICi/6NcqXJhE2pwMbDAb9j18D0TwU86sLhfevG3654bUNNa8yieg6PDuSB5Ku5WoV7kVCLS+Y3OqrWPd01aucyId2wq2YWNrc12/cQe0UexpGRDIItbNvdzdfbJd72FBT5tEL/J7Il0NGPWoZ7pwlOKFeHHPf8b0EWYUM2P9uZemdxaaELcP3Q/6bpjZWKmh6ynMU8bvFDfGrgD5PbwIWpZSkX7ij0qDk1qUg8P2DGgtyoYXX1wN9V9McDu0NiwB/ZlKlFdFDaL54tYA== Received: from BY5PR03CA0003.namprd03.prod.outlook.com (2603:10b6:a03:1e0::13) by LV8PR12MB9183.namprd12.prod.outlook.com (2603:10b6:408:193::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.18; Fri, 25 Oct 2024 23:51:08 +0000 Received: from CO1PEPF000075ED.namprd03.prod.outlook.com (2603:10b6:a03:1e0:cafe::34) by BY5PR03CA0003.outlook.office365.com (2603:10b6:a03:1e0::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20 via Frontend Transport; Fri, 25 Oct 2024 23:51:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF000075ED.mail.protection.outlook.com (10.167.249.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:07 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:00 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:00 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:50:59 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 09/13] iommufd/selftest: Add IOMMU_TEST_OP_DEV_CHECK_CACHE test command Date: Fri, 25 Oct 2024 16:50:38 -0700 Message-ID: <6e578f2cb32141a676a6cb82c04506662d1a1254.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075ED:EE_|LV8PR12MB9183:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c1ee68f-5666-41ce-6502-08dcf54fe56f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|7416014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/74Pei6FsX/XgheJpK919geN4OS6NKbsiSzQGwDVRXLpLD10JB8Ths0KIfCK?= =?us-ascii?Q?37/vXsuUeYyY2W4H80cTiOwnBw3ly9O7m5hbr/cu/Uu/RgzUTcaAUQF99vSM?= =?us-ascii?Q?JQyWDncQ72QibQQvbgU+XYcxoRVLR8h5SPDl47f4zPaEfYwcy/CVHhp9kSa6?= =?us-ascii?Q?rgMwCuO7xyQHuJ2ZB8sMYsWZ1msWhELcaMrklsFYboUCs6Y+ctSPM6bk3t67?= =?us-ascii?Q?/tRzvMZk8jDlXdluLdp7skaNzbrTVRBKiO/c4W6L+9vJ2BvYMdEntlwh/QM8?= =?us-ascii?Q?BIlo9qIyYh9sCy6tqoOAmYq5vV1ul5HiRw2jxWP9sU0lw1S4zn1i6I5T5yw7?= =?us-ascii?Q?c3BaELWmsq3VVct1IPLuzaqOOQVKWIg8m0fSRHB92B5TCnmZv9f9J8f/p15i?= =?us-ascii?Q?WxQASUV2LaNvODSnyhSeCfhi4h8S2AfW3hkBPAdyiYAK86ETdu4Kapg5Jslf?= =?us-ascii?Q?M+oD9DoZuGLqna2fOhh0v2ZALAnhYE0uxAmZroo230Zgx1yqDcMEFC2JLFlx?= =?us-ascii?Q?bRzMy09Ov+I9fthloT/e6YZ9QV3dourIVfN4XzythCNMnpX4Cfx9JL5dNYpA?= =?us-ascii?Q?LUVSknrETZF29FNxWC1dRTcQNLzoFjX4rEWZVDNtnvVgj8z7vmZrQ0pG92eO?= =?us-ascii?Q?YpOUTaLq/oRmVj22SvRCbj4qInYz20O5wPDUXHE1k5q+Wg1e/s9DqJeYCRK7?= =?us-ascii?Q?c4FPrWrSVs7GoTELuiRZtqehzRtYCLEpmNXijrwq2MFWPEFHZ00ahpE8asQg?= =?us-ascii?Q?4BTBujbB7yUEWnuynNCWDi/8pTZ0d6GghZHOtQdy9wpcAouB5Bn0RmDyM56W?= =?us-ascii?Q?2cFWXo7MpZ8MrqlmZSQ85av7MCiGLAb96qPeHaBXrdQeDgBC3+P1Hu8R4qA/?= =?us-ascii?Q?sNNeSxq79uo2SN51ocuW9gst1VvdxlrThGIxSzyqO3J6rBSp/huZVGlr5YHA?= =?us-ascii?Q?ybk1sNXPc+yur7NRHNK7AKWrIL34uUlZOUTvC5OF8KVc6l1Rn+dm6OTYJvda?= =?us-ascii?Q?9hKkrULvl5PhdDYK7tGVEoWAiFjZGz4rrRVPYoczs2lSoNIANyfh9w1WNVDU?= =?us-ascii?Q?njXp+I3ItOBy+YLCrcLXvm3JGcuGJSkK2gIIiu2JRB+kQh54anxOCzNtu4sR?= =?us-ascii?Q?cu6A9ian1zkkJeuC4HbcBLLUxiPR6SnMhWN+gcED3o58J337oA2YuRKD2d6c?= =?us-ascii?Q?tK0uQvjSkXaoBK1pKo7do91fAhQocqFb9dXH/IpwxmOjjfjWwvB3H+OuR1cz?= =?us-ascii?Q?B6wPCvXL3+4Jjtge1oItbAuEkwa53J703JWROR81xvde7ucUvzQ7hAK1eD+e?= =?us-ascii?Q?MOBICyuYgpbwUdc5wUSlQ/wWL8ocsWwQphQISKskLubG9GQgU0mbXFEoGtRX?= =?us-ascii?Q?p5poU5eIDN2PREB6WBhtVk7nZMJSVxsVBqG0j8aM9xbfmSEGxQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(7416014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:07.9178 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c1ee68f-5666-41ce-6502-08dcf54fe56f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9183 Content-Type: text/plain; charset="utf-8" Similar to IOMMU_TEST_OP_MD_CHECK_IOTLB verifying a mock_domain's iotlb, IOMMU_TEST_OP_DEV_CHECK_CACHE will be used to verify a mock_dev's cache. Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/iommu/iommufd/iommufd_test.h | 5 ++++ tools/testing/selftests/iommu/iommufd_utils.h | 24 +++++++++++++++++++ drivers/iommu/iommufd/selftest.c | 22 +++++++++++++++++ tools/testing/selftests/iommu/iommufd.c | 7 +++++- 4 files changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/iommufd_test.h b/drivers/iommu/iommufd/i= ommufd_test.h index 46558f83e734..a6b7a163f636 100644 --- a/drivers/iommu/iommufd/iommufd_test.h +++ b/drivers/iommu/iommufd/iommufd_test.h @@ -23,6 +23,7 @@ enum { IOMMU_TEST_OP_DIRTY, IOMMU_TEST_OP_MD_CHECK_IOTLB, IOMMU_TEST_OP_TRIGGER_IOPF, + IOMMU_TEST_OP_DEV_CHECK_CACHE, }; =20 enum { @@ -140,6 +141,10 @@ struct iommu_test_cmd { __u32 perm; __u64 addr; } trigger_iopf; + struct { + __u32 id; + __u32 cache; + } check_dev_cache; }; __u32 last; }; diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/= selftests/iommu/iommufd_utils.h index 5b17d7b2ac5c..3ae6cb5eed7d 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -234,6 +234,30 @@ static int _test_cmd_hwpt_alloc(int fd, __u32 device_i= d, __u32 pt_id, __u32 ft_i test_cmd_hwpt_check_iotlb(hwpt_id, i, expected); \ }) =20 +#define test_cmd_dev_check_cache(device_id, cache_id, expected) = \ + ({ \ + struct iommu_test_cmd test_cmd =3D { \ + .size =3D sizeof(test_cmd), \ + .op =3D IOMMU_TEST_OP_DEV_CHECK_CACHE, \ + .id =3D device_id, \ + .check_dev_cache =3D { \ + .id =3D cache_id, \ + .cache =3D expected, \ + }, \ + }; \ + ASSERT_EQ(0, ioctl(self->fd, \ + _IOMMU_TEST_CMD( \ + IOMMU_TEST_OP_DEV_CHECK_CACHE), \ + &test_cmd)); \ + }) + +#define test_cmd_dev_check_cache_all(device_id, expected) = \ + ({ \ + int c; \ + for (c =3D 0; c < MOCK_DEV_CACHE_NUM; c++) \ + test_cmd_dev_check_cache(device_id, c, expected); \ + }) + static int _test_cmd_hwpt_invalidate(int fd, __u32 hwpt_id, void *reqs, uint32_t data_type, uint32_t lreq, uint32_t *nreqs) diff --git a/drivers/iommu/iommufd/selftest.c b/drivers/iommu/iommufd/selft= est.c index 01556854f2f2..7bb47b4a6d63 100644 --- a/drivers/iommu/iommufd/selftest.c +++ b/drivers/iommu/iommufd/selftest.c @@ -1122,6 +1122,24 @@ static int iommufd_test_md_check_iotlb(struct iommuf= d_ucmd *ucmd, return rc; } =20 +static int iommufd_test_dev_check_cache(struct iommufd_ucmd *ucmd, u32 ide= v_id, + unsigned int cache_id, u32 cache) +{ + struct iommufd_device *idev; + struct mock_dev *mdev; + int rc =3D 0; + + idev =3D iommufd_get_device(ucmd, idev_id); + if (IS_ERR(idev)) + return PTR_ERR(idev); + mdev =3D container_of(idev->dev, struct mock_dev, dev); + + if (cache_id > MOCK_DEV_CACHE_ID_MAX || mdev->cache[cache_id] !=3D cache) + rc =3D -EINVAL; + iommufd_put_object(ucmd->ictx, &idev->obj); + return rc; +} + struct selftest_access { struct iommufd_access *access; struct file *file; @@ -1631,6 +1649,10 @@ int iommufd_test(struct iommufd_ucmd *ucmd) return iommufd_test_md_check_iotlb(ucmd, cmd->id, cmd->check_iotlb.id, cmd->check_iotlb.iotlb); + case IOMMU_TEST_OP_DEV_CHECK_CACHE: + return iommufd_test_dev_check_cache(ucmd, cmd->id, + cmd->check_dev_cache.id, + cmd->check_dev_cache.cache); case IOMMU_TEST_OP_CREATE_ACCESS: return iommufd_test_create_access(ucmd, cmd->id, cmd->create_access.flags); diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selfte= sts/iommu/iommufd.c index 44fbc7e5aa2e..ff0181e5db48 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -222,6 +222,8 @@ FIXTURE_SETUP(iommufd_ioas) for (i =3D 0; i !=3D variant->mock_domains; i++) { test_cmd_mock_domain(self->ioas_id, &self->stdev_id, &self->hwpt_id, &self->device_id); + test_cmd_dev_check_cache_all(self->device_id, + IOMMU_TEST_DEV_CACHE_DEFAULT); self->base_iova =3D MOCK_APERTURE_START; } } @@ -1386,9 +1388,12 @@ FIXTURE_SETUP(iommufd_mock_domain) =20 ASSERT_GE(ARRAY_SIZE(self->hwpt_ids), variant->mock_domains); =20 - for (i =3D 0; i !=3D variant->mock_domains; i++) + for (i =3D 0; i !=3D variant->mock_domains; i++) { test_cmd_mock_domain(self->ioas_id, &self->stdev_ids[i], &self->hwpt_ids[i], &self->idev_ids[i]); + test_cmd_dev_check_cache_all(self->idev_ids[0], + IOMMU_TEST_DEV_CACHE_DEFAULT); + } self->hwpt_id =3D self->hwpt_ids[0]; =20 self->mmap_flags =3D MAP_SHARED | MAP_ANONYMOUS; --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2075.outbound.protection.outlook.com [40.107.92.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE6321E60C; Fri, 25 Oct 2024 23:51:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900277; cv=fail; b=H7N56qCe7TK4iTrFDib6APHQn29UufDwcRaEtZjsPiLvr4p4RqTggYbtz6LqmIpfR7bq/KGH/ucU6Qrwon3hu++5mZRuGn35iHgOw7jNuq8N8zlyaXfWS4hIrKJmwD8T0+LW3rveOhFgu2RsxSXE/fUgOxddNlnoC1izR8NUNW0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900277; c=relaxed/simple; bh=u6GzZ00+wb1AF3kZwqJmIZq0wpmLr6dnV8r+jXcEgrs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U+suWbSreYomENDDPYS9MjUGzeNvi6kWc8B7HNvi/zCDmnIl+E6YQPEUZpcZn5KVREaccKLp4WRaMd5I74UL2fRn7FDDrfT576l1jwuQV06qAGa+V7yE3XA3kKRsIe/dL7DeA+Wb0KUYgf1skOzoOMphWnyovCfx1/lDmLPrpno= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=Z+PmJxHi; arc=fail smtp.client-ip=40.107.92.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="Z+PmJxHi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=SFxNBWEw30hOicWe5LKHmqFjy9IfPrLxcSwLIlETZE201j1zuNdTnVnDFPAbuhrMxwK7WniOVxAjtORDQv4HEsLsnqF/sRAj6Mjcuk5M19FCIJO41HhFbnft5aTVTsSapaivi2N+jM/4kbfY4ReQ5ukNPYhffBhuH/SMU/YHeO/Up6KAfyRmID3oAMjcSuNhPTnUUsNiE+qVlX949oU234XAKKneCIX2zw1sOdRPF6AXfvz2CtDvqd+mDb7qf+TiLOIWjiTpHxQzht8vyhhJj7NUlNAUnaEkS3yzMG7aDmx+IfBPyHKzJ+AUTkopPU/4FEzBgF35MYej/jqFNDNUVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=X6dG17MunVwVcYiNUHxHYS/ZiQYCsjJGFDI3pRFAE9s=; b=TTApuXO/s5a4vq4Sr8BAZGxeiYYUGpQRmR9zPr8ODGRzdjMddvj1t06cKGspREJ7D/ozE0qDXIWEjkz77lMEkC+ujJs3LYYZ8MRVPHGwbCVulrSIb/wL+5mVmWfxYPWTTMYnRObr9c1dRdh0boyZzKgDfY89OIw7AnoHkiavu9CZKm3T+cbcB6c1xYXvI3PNYV9EoVJ6u4wv3pLeq8OWzjNPTimsqyPceGqRdjftWytixm2EZchyiKn/Yx+6X2OjisOh5fi6okOseq1UJ+3Thn9Vxfi7//VDK6QIG5u6gs5EtWgkRp1oD0pBPbH43gnV5WhwixN3ygFyjWzSLZBWuQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=X6dG17MunVwVcYiNUHxHYS/ZiQYCsjJGFDI3pRFAE9s=; b=Z+PmJxHi9/J+ponkQWwW/VB45hmpxDEWwnKDd4pyD6mbVR6LbSUDk1bMmUHYulDLJLxh30uljiVqs31bNT9SQre7XGMVQRy52chG4o+y4MRF7+jwIzEkFaAI3qYSt/Ge6mXURfrOutjxrdLbCIUCcv+B35sZg6waz3Po40vtFVNsjkwSl0KkOxaKY2s5bTaJ8JGPjhtk5BjpintL3NXKc9QdBvkSSVE0GIIheh2fsCNzC1z7xFSV2FPtl0QS0qc9bEPieJe2ZIVNGwiyxuqa2mYS5ZZwFoMeNt376BsMD8ZaPYYyLIDB70TFAN801Pc1dN9Vp67N6trooHhGEzapkA== Received: from BYAPR05CA0105.namprd05.prod.outlook.com (2603:10b6:a03:e0::46) by BY5PR12MB4276.namprd12.prod.outlook.com (2603:10b6:a03:20f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.23; Fri, 25 Oct 2024 23:51:09 +0000 Received: from SJ1PEPF000023CF.namprd02.prod.outlook.com (2603:10b6:a03:e0:cafe::a5) by BYAPR05CA0105.outlook.office365.com (2603:10b6:a03:e0::46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.8 via Frontend Transport; Fri, 25 Oct 2024 23:51:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:08 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:02 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:01 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:51:00 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 10/13] iommufd/selftest: Add vIOMMU coverage for IOMMU_HWPT_INVALIDATE ioctl Date: Fri, 25 Oct 2024 16:50:39 -0700 Message-ID: <35452ef0c1bcc9e0ed5217c89c9a72c1f7a17360.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|BY5PR12MB4276:EE_ X-MS-Office365-Filtering-Correlation-Id: 7becad32-3c21-454a-ce6b-08dcf54fe5fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QuNa/mGfQChsSk9MusmIdVCOR4Wpr+hFlb9tNw6eO+5uuQj6oxwwjq+jo4kk?= =?us-ascii?Q?KysXCRuuS4Z9ulg+lI+rU2jD9kQC9xs6KMWHzWqKQYCuzJBrVpVe7/JWQHWp?= =?us-ascii?Q?j9olIgibFzJJlrgqGyTRK3cNlUHN1prk+RHgTkQZ5wJKP+81eSMq0ezAYH8w?= =?us-ascii?Q?fmI3rRJ5lodKtOZXZb7/yE2IqVUIzbKiJceR1noO9LO/p2fvpX1otsLgofOn?= =?us-ascii?Q?Chry3WVKSTGO9rFTxZbMY3iqpUFL6VQ8972oKkFVC+ffixWOQk4bH/Hm/U5I?= =?us-ascii?Q?I3oxeqRomk69Y4/ipU08krLfdSD/1atKBbjLXV5ZaTcgcDmaobaCinUpRZwN?= =?us-ascii?Q?srN8AWOoha07NJZoSkXaTs5X5m1yXYdXiMuYRjW5un04RbV90PYGEVJW/9fH?= =?us-ascii?Q?dRTDwV6WSvjHmGzLKliJTmZziIKjYXBULHqEv73LGwm9nV3TPyWxvuIwvKjf?= =?us-ascii?Q?lBpMpMf4PRJuIs91U+6oecGld6PSP72AJudzYmfDNxAJQbjLd3goOz7i1G4V?= =?us-ascii?Q?Fen1DoLxA8zdZxEgQog5mj9ioycLuwmnJMz4gl20IE1XkTG9x3W/azjMy9M1?= =?us-ascii?Q?QBvj65Yw/76YrabCTOkynbFXbjeNh1lQlvtYtmUmETaSnc3PVU/H0rq00+zq?= =?us-ascii?Q?tLgOXlmINjmmObqROsLtM47u42gxJztvKLlYNOs21OqdiX/hiY2975mb7LrX?= =?us-ascii?Q?wNR33N/JXDT0maCzQ0p9BFs2WlZuwg5ceFrx7jspb2b7bpwp0WfHQAaZ51Ri?= =?us-ascii?Q?yyJSsSLMQCrvzWsLeyJIA3YHTL0ZtIEqJSTs0SvyGRpP219AngYHyOB9J/uY?= =?us-ascii?Q?qhMkjvMKhtkGfMYl/NeOeOcumWT2cLa2guSThvHJWSYTDCFFOHpqi9tI8wH9?= =?us-ascii?Q?NBM9rdYbNv9RzAf5QkKXpGZloxFB0OQoow4N61SadgRaFowz6jotSL+9IeDE?= =?us-ascii?Q?Bo0SgyzWEbEuiW1wH06Cer7XGic+v1rZAiwdRsmaUYDDtMc24gyUqNgguMaz?= =?us-ascii?Q?Z6MwU3xzQzxrdVmVBwYpXfh+1inlxcAC64VscvcJsimKRMQKj7fyKDnvg7lG?= =?us-ascii?Q?N0wUD7c6Wj7TJ+P6xluLj48lUu9RO08w1Qn0h4JJ8070u8JsG4st8b4TOnW2?= =?us-ascii?Q?RtFlqrwD1KTJGVImFyKLDYQJgeyNvIiss5RaWWDb3MAzbB7I6R9PyC/z1g0O?= =?us-ascii?Q?ArKsC0kA3GeoLmOzeDTHI/P93XDojCAxuNdcWWHABoQbsbJHZ4+utXYOAo+z?= =?us-ascii?Q?H6dYareLbY7CsldiaCS9CfKDKUjrIKEBFzaim63i0i8WXmSXTGszdCnTF6CK?= =?us-ascii?Q?YuObHj1U5D74mp3hl/2LECLQ79gt7QQcKDd56fnfZwp7X5cyJN8SD7lRpSg1?= =?us-ascii?Q?w09PojrZlOjWDsqbLb076D891l9rGqyK5s82+3CqExohxJeS9Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:08.9252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7becad32-3c21-454a-ce6b-08dcf54fe5fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4276 Content-Type: text/plain; charset="utf-8" Add a viommu_cache test function to cover vIOMMU invalidations using the updated IOMMU_HWPT_INVALIDATE ioctl, which now allows passing in a vIOMMU via its hwpt_id field. Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- tools/testing/selftests/iommu/iommufd_utils.h | 32 ++++ tools/testing/selftests/iommu/iommufd.c | 173 ++++++++++++++++++ 2 files changed, 205 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/= selftests/iommu/iommufd_utils.h index 3ae6cb5eed7d..aa458c80ad30 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -289,6 +289,38 @@ static int _test_cmd_hwpt_invalidate(int fd, __u32 hwp= t_id, void *reqs, data_type, lreq, nreqs)); \ }) =20 +static int _test_cmd_viommu_invalidate(int fd, __u32 viommu_id, void *reqs, + uint32_t data_type, uint32_t lreq, + uint32_t *nreqs) +{ + struct iommu_hwpt_invalidate cmd =3D { + .size =3D sizeof(cmd), + .hwpt_id =3D viommu_id, + .data_type =3D data_type, + .data_uptr =3D (uint64_t)reqs, + .entry_len =3D lreq, + .entry_num =3D *nreqs, + }; + int rc =3D ioctl(fd, IOMMU_HWPT_INVALIDATE, &cmd); + *nreqs =3D cmd.entry_num; + return rc; +} + +#define test_cmd_viommu_invalidate(viommu, reqs, lreq, nreqs) = \ + ({ \ + ASSERT_EQ(0, \ + _test_cmd_viommu_invalidate(self->fd, viommu, reqs, \ + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, \ + lreq, nreqs)); \ + }) +#define test_err_viommu_invalidate(_errno, viommu_id, reqs, data_type, lre= q, \ + nreqs) \ + ({ \ + EXPECT_ERRNO(_errno, _test_cmd_viommu_invalidate( \ + self->fd, viommu_id, reqs, \ + data_type, lreq, nreqs)); \ + }) + static int _test_cmd_access_replace_ioas(int fd, __u32 access_id, unsigned int ioas_id) { diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selfte= sts/iommu/iommufd.c index ff0181e5db48..9a7d4b9c44f6 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -2498,4 +2498,177 @@ TEST_F(iommufd_viommu, vdevice_alloc) } } =20 +TEST_F(iommufd_viommu, vdevice_cache) +{ + struct iommu_viommu_invalidate_selftest inv_reqs[2] =3D {}; + uint32_t viommu_id =3D self->viommu_id; + uint32_t dev_id =3D self->device_id; + uint32_t vdev_id =3D 0; + uint32_t num_inv; + + if (dev_id) { + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x99, &vdev_id); + + test_cmd_dev_check_cache_all(dev_id, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Check data_type by passing zero-length array */ + num_inv =3D 0; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: Invalid data_type */ + num_inv =3D 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST_INVALID, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: structure size sanity */ + num_inv =3D 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs) + 1, &num_inv); + assert(!num_inv); + + num_inv =3D 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + 1, &num_inv); + assert(!num_inv); + + /* Negative test: invalid flag is passed */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0xffffffff; + inv_reqs[0].vdev_id =3D 0x99; + test_err_viommu_invalidate(EOPNOTSUPP, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid data_uptr when array is not empty */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + test_err_viommu_invalidate(EINVAL, viommu_id, NULL, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid entry_len when array is not empty */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + 0, &num_inv); + assert(!num_inv); + + /* Negative test: invalid cache_id */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D MOCK_DEV_CACHE_ID_MAX + 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid vdev_id */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x9; + inv_reqs[0].cache_id =3D 0; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* + * Invalidate the 1st cache entry but fail the 2nd request + * due to invalid flags configuration in the 2nd request. + */ + num_inv =3D 2; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 0; + inv_reqs[1].flags =3D 0xffffffff; + inv_reqs[1].vdev_id =3D 0x99; + inv_reqs[1].cache_id =3D 1; + test_err_viommu_invalidate(EOPNOTSUPP, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* + * Invalidate the 1st cache entry but fail the 2nd request + * due to invalid cache_id configuration in the 2nd request. + */ + num_inv =3D 2; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 0; + inv_reqs[1].flags =3D 0; + inv_reqs[1].vdev_id =3D 0x99; + inv_reqs[1].cache_id =3D MOCK_DEV_CACHE_ID_MAX + 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Invalidate the 2nd cache entry and verify */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 1; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, 0); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Invalidate the 3rd and 4th cache entries and verify */ + num_inv =3D 2; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 2; + inv_reqs[1].flags =3D 0; + inv_reqs[1].vdev_id =3D 0x99; + inv_reqs[1].cache_id =3D 3; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 2); + test_cmd_dev_check_cache_all(dev_id, 0); + + /* Invalidate all cache entries for nested_dev_id[1] and verify */ + num_inv =3D 1; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].flags =3D IOMMU_TEST_INVALIDATE_FLAG_ALL; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache_all(dev_id, 0); + test_ioctl_destroy(vdev_id); + } +} + TEST_HARNESS_MAIN --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2044.outbound.protection.outlook.com [40.107.243.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E6721E63F; Fri, 25 Oct 2024 23:51:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.243.44 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900279; cv=fail; b=rEXDhZTzkyfuzxGdlmgX2IF/2seeCgLtxAbKLfwuQu0Grtug/n0seH56g8LXF8SwoBHRHt9HrCCB+oCvnyK5kP6GjXAlUTv/lBmOsJKG99z6b5H9vBp8bwPRNCcJvzXRHqBdboym2AKJH10XL0p1bSKSCW2wStH/9yC6gsizFyA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900279; c=relaxed/simple; bh=cC0jz4bcpNdkQAMS+QyStdtWW6QC3eJ5+coK2iC9kcI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Vwb3W4pyLNaY747nYK6jCHFT6NLwGaML2DslKMNgz+LZkC1J/+4eVLn9nMfOLfTrnCSM9UdaCBP3AlnYTn58VpltPxwBLXHbjWg/fG4XNRJ7DOS/aNJbjVVdQYmBdJLX3eMc34fqkvy8fUCj0zUb+CtWP9pjVshQRKMkPWKzoxE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=t6mWOfFS; arc=fail smtp.client-ip=40.107.243.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="t6mWOfFS" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=KBAEzV2DVBhnv07V7YJ1qR8aYDH0KbH63/g4tGjvgQXiYbhVZLGQj8AzhQr92wO/z0ZrRqL/xOwNy3vIbRTubR7aoMYqkKl/dTCP5LjhkOwQj6eMiBk1GT0fqm+gjXYgVncds6UiWyIakHm1Lts5871xPLEQzvfkcf9cRSwQ8QivXE8cej91xbKG0EuUqGp1XEGBtGuaK79zd+WCcVSC+CRjVRxrn3vzVgrOFu7ngF5tl6eDb+SnIp/Snld5/xTTM4iJKJj5ltGyutR3G2a5MqO4P6brrdM300IrjeXGiXsSbNrKZUzJC2Zms0xuVcvd81J0ZKyilEycAzczHmN9vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZiC5SOn5wx3+AyofS3XSFjYoRsquGrqqghEx28hfyWA=; b=s5udR2+alF03cZ0t0VZMclhCcbToQ3QVPW3pi9EA/Y3S/jUdeGcaJZPsZ0VEnIykAwBSUCy+gMitreM7KOiAF5WY6gyiqZDvpiDLrU2pyUyHz59VR0HrzK21e4Dauo4NKmCaPmYWIqqHqqBHrlqt0shQ6ePxdsyCjfDHtmFn0BT+qosq+bbMzgGHy8P8BZlyW4O4kPdZkjBLgTZd8YRBbn3WEwNUpfT5oXwBdKRqdF7Kf6FDz5agqr6N1On0RDbCf/xrKeU0Jb/vmO83oqena6Ne9lyJ07+fDDrWkF2RGurmAF+sVw4AYyULuOk9WLAFNfuzwJTmGyF7d89OLnqCkg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZiC5SOn5wx3+AyofS3XSFjYoRsquGrqqghEx28hfyWA=; b=t6mWOfFSGhvKlOrVNHx+lDqYbsr6BLt3p1kFFTHO9FqdtNhh6qObuspiZdYWp8hgXO/aL/02F96xTYty8cuvDNNn/kd6Z881sBzrL+dW7Pe0FIbUARaENCGsOPtruFLTUDA2NhICwelGtqUIhqrpVafvgU+juTopM8CsY//UclO/r4v+USUSFFLvTnfR16QL5SEN+mFXb4xevEep3B6Gj/EcMkqJATQfgG5weCbKkJH6zaECZI6MEvojUUCZ5JWcwnB+35wSg57I/i5Dwxis9+hFz+yuf3lXkxrCwaBH2VTETv78FSYklNZC6mAPwuTSOzEwGGY8ckChd7pN+Zo/cg== Received: from BY3PR10CA0028.namprd10.prod.outlook.com (2603:10b6:a03:255::33) by IA0PR12MB7604.namprd12.prod.outlook.com (2603:10b6:208:438::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.18; Fri, 25 Oct 2024 23:51:11 +0000 Received: from SJ1PEPF000023D2.namprd02.prod.outlook.com (2603:10b6:a03:255:cafe::54) by BY3PR10CA0028.outlook.office365.com (2603:10b6:a03:255::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20 via Frontend Transport; Fri, 25 Oct 2024 23:51:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023D2.mail.protection.outlook.com (10.167.244.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:11 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:03 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:03 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:51:02 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 11/13] Documentation: userspace-api: iommufd: Update vDEVICE Date: Fri, 25 Oct 2024 16:50:40 -0700 Message-ID: <3e7166c065f767ff55c3207b12144a8aa4dc8ae3.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D2:EE_|IA0PR12MB7604:EE_ X-MS-Office365-Filtering-Correlation-Id: d9fe2ed3-74de-4192-7b26-08dcf54fe749 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Q+vgNPwMxTHLVBk5kHJ84rM/aLRx9iOOq9CW+jOJZwPsRmSrjedvaR4az60v?= =?us-ascii?Q?m4U0Et+1xHOth42nFSjmYJvh91gvy3DcLjaoFa6SenceKd1MpH1N2bH96KXO?= =?us-ascii?Q?3JVtnHB/Zp1PuEoo03OngZKYIO4ZttuYETlZZumKNuU/d2OC8fj1nT1xLOo+?= =?us-ascii?Q?nKDQTwzrIUqjdlWfS9ZDU0mmukSLtLYJsw74a6vSUZ4xgYF9kCqSUp7Yn4LD?= =?us-ascii?Q?G419YyS3xEsLphyTWTqMurO+OYwKfbLrN6qH7sNAW6CzGoNLH/ofc+b08K8+?= =?us-ascii?Q?+TlFFRdIrZZpuBWDdYymsuc1k5qT6tY4HJE+eZV7iW0zjV+f3/T+U1w95PwF?= =?us-ascii?Q?sim4rm2f1QetztxS4TWD1xPIcan66csRXmXpUYPv+ZQF6SuAnze/9Ois9uMW?= =?us-ascii?Q?9INR+E/LUDv1fQ1jDXOJ403LrLtp+vOMn1p4Lcov7n5j5kCVY4ZDtU4rLilJ?= =?us-ascii?Q?F1ZbVzfD/0jxqOzbsoc6urzFlI+q/QO+5ieQoaGE52NbCNSn7vCpKFaowcc8?= =?us-ascii?Q?FYB5j/FPBz3s9lbad5Sdv3wMyObpMqSLXZCqvb4YebtGvmhe7vru1886yCuO?= =?us-ascii?Q?fc+7mFlXfA0PE5i2OfxF6kindT/qUUHL4SDgTzsNCbm2KgpbBPAWS65kiIQX?= =?us-ascii?Q?K6h/HpDibwHhYUmDwNSgtcM0xFr6QijcTagsPux2AcHlP3Gw4bfWH8e8E+Y3?= =?us-ascii?Q?+aV/Neoij7J7Uh8W6I/S4lsxBMq0DmDkCr2VTqvudQ6081/yCdlQ7E+cNquH?= =?us-ascii?Q?wDSxiq6GGTYOmS9mEIu6nyProUNI5UO7BclDldx+0cEzKrPICjltkq9RPk+a?= =?us-ascii?Q?QIjGc+XQpi5dGXVFk+v768LtCcelRiWXtzJgUCGOahukDg+euXxzdnLwVnw4?= =?us-ascii?Q?N410Zsz4YriaVtneZ7u0RBQgZ8ouYNMx9np4fBfTYJoeCtEdIWVHVpMhEARg?= =?us-ascii?Q?sl5A/DaAN4NhxncyuTD3sGu7qJoADYnVFnz3OZlj9EjAS0LEFSh2jcssmf0X?= =?us-ascii?Q?x6MF1TSDB9alPfGUh/XtXgUsEoSAOEj963K6wZGylpmiqoAxtHA0QoNP3vkA?= =?us-ascii?Q?whwvPxJh86eSAcP/+5g4r7PSKutTE7vBxettnrmt1QPE+0I4pda2x0t6aBCT?= =?us-ascii?Q?Z0/QCahW/zhXtsM3TLelqLCFiAY+ASGp6omXJG13VB5EVn65YU70JXcVM7Y+?= =?us-ascii?Q?HgIx4zCJV6i/dnz5iq4qVfCV7zfpwp6yyeXWNPVuyKv8Mb8AxvlrQwqdJ0l3?= =?us-ascii?Q?ivlvdi2h/sqWPYMZm1tYpQFVG7WfmU0h8gp9/xTltb3aKx/wczgkhoB7Z5A3?= =?us-ascii?Q?L1YUw4twxA3MhcY38oFt9RMEDx5zajo3fU9cycRmyjxCamifiohSFCcyNHkC?= =?us-ascii?Q?3YVf52INzz8y9k4DCJGKz//1T3oNk3XM8QXFOQDRozsAGu0z8Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:11.1185 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9fe2ed3-74de-4192-7b26-08dcf54fe749 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7604 Content-Type: text/plain; charset="utf-8" With the introduction of the new object and its infrastructure, update the doc and the vIOMMU graph to reflect that. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- Documentation/userspace-api/iommufd.rst | 41 +++++++++++++++++++------ 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/Documentation/userspace-api/iommufd.rst b/Documentation/usersp= ace-api/iommufd.rst index 92d16efad5b0..3c27cc92c2cb 100644 --- a/Documentation/userspace-api/iommufd.rst +++ b/Documentation/userspace-api/iommufd.rst @@ -94,6 +94,19 @@ Following IOMMUFD objects are exposed to userspace: backed by corresponding vIOMMU objects, in which case a guest OS wou= ld do the "dispatch" naturally instead of VMM trappings. =20 + - IOMMUFD_OBJ_VDEVICE, representing a virtual device for an IOMMUFD_OBJ_D= EVICE + against an IOMMUFD_OBJ_VIOMMU. This virtual device holds the device's v= irtual + information or attributes (related to the vIOMMU) in a VM. An immediate= vDATA + example can be the virtual ID of the device on a vIOMMU, which is a uni= que ID + that VMM assigns to the device for a translation channel/port of the vI= OMMU, + e.g. vSID of ARM SMMUv3, vDeviceID of AMD IOMMU, and vID of Intel VT-d = to a + Context Table. Potential use cases of some advanced security informatio= n can + be forwarded via this object too, such as security level or realm infor= mation + in a Confidential Compute Architecture. A VMM should create a vDEVICE o= bject + to forward all the device information in a VM, when it connects a devic= e to a + vIOMMU, which is a separate ioctl call from attaching the same device t= o an + HWPT_PAGING that the vIOMMU holds. + All user-visible objects are destroyed via the IOMMU_DESTROY uAPI. =20 The diagrams below show relationships between user-visible objects and ker= nel @@ -133,16 +146,16 @@ creating the objects and links:: |____________| |____________| |______| =20 _______________________________________________________________________ - | iommufd (with vIOMMU) | + | iommufd (with vIOMMU/vDEVICE) | | | - | [5] | - | _____________ | - | | | | - | |----------------| vIOMMU | | - | | | | | - | | | | | - | | [1] | | [4] [2] | - | | ______ | | _____________ ________ | + | [5] [6] | + | _____________ _____________ | + | | | | | | + | |----------------| vIOMMU |<---| vDEVICE |<----| | + | | | | |_____________| | | + | | | | | | + | | [1] | | [4] | [2] | + | | ______ | | _____________ _|______ | | | | | | [3] | | | | | | | | | IOAS |<---|(HWPT_PAGING)|<---| HWPT_NESTED |<--| DEVICE | | | | |______| |_____________| |_____________| |________| | @@ -215,6 +228,15 @@ creating the objects and links:: the vIOMMU object and the HWPT_PAGING, then this vIOMMU object can be u= sed as a nesting parent object to allocate an HWPT_NESTED object described = above. =20 +6. IOMMUFD_OBJ_VDEVICE can be only manually created via the IOMMU_VDEVICE_= ALLOC + uAPI, provided a viommu_id for an iommufd_viommu object and a dev_id fo= r an + iommufd_device object. The vDEVICE object will be the binding between t= hese + two parent objects. Another @virt_id will be also set via the uAPI prov= iding + the iommufd core an index to store the vDEVICE object to a vDEVICE arra= y per + vIOMMU. If necessary, the IOMMU driver may choose to implement a vdevce= _alloc + op to init its HW for virtualization feature related to a vDEVICE. Succ= essful + completion of this operation sets up the linkages between vIOMMU and de= vice. + A device can only bind to an iommufd due to DMA ownership claim and attach= to at most one IOAS object (no support of PASID yet). =20 @@ -228,6 +250,7 @@ User visible objects are backed by following datastruct= ures: - iommufd_hwpt_paging for IOMMUFD_OBJ_HWPT_PAGING. - iommufd_hwpt_nested for IOMMUFD_OBJ_HWPT_NESTED. - iommufd_viommu for IOMMUFD_OBJ_VIOMMU. +- iommufd_vdevice for IOMMUFD_OBJ_VDEVICE =20 Several terminologies when looking at these datastructures: =20 --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2086.outbound.protection.outlook.com [40.107.223.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABF0B216E03; Fri, 25 Oct 2024 23:51:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.223.86 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900284; cv=fail; b=H9ZTRph8xaOFPNLdUSki/4G2Pb+uAUnVvf/9MpAS7geyAjmeyuY/rH0XlRMaE+pg8o8SO+cSajJnvmpgsudyPsAS5R2tDp7na2q4tT0mFFZ7E61wkWBR6PRETsdHQTwEx3+CmsBSNDei1t8UQIUG2IqZGdLHkD3UQVxp8G67yEM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900284; c=relaxed/simple; bh=Eu6XWs3rpVlKBng75kJOpigKxUqnkduMIJWjkbUFCxM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ff1Xf+mwtZzNxtRaOkxyMBgg8aIC78nrdjZr1tTjbeBrzp8+W5R47JDmRnV0Vr2ufmcd4CFL68sBz9DVYVzZqBdMIAnOg8wEPoivQDTKT+mB8eBefF2YKC3JjlB+XGrNENDY2RqMzKneIvFZ9PC7lhwHxbHomlMVI3tcXutFbmQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=TKgU2cLb; arc=fail smtp.client-ip=40.107.223.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="TKgU2cLb" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EGsRQDCXcqAcsHeYQiEVn4lMGF4V7zOn/yo8hWIkwKF+YmFI4mXF/eq7nJQ1/pK4Zy5s5lr7K8c0hBXUHqgKLUQmEDxBq8n3A8VvSqT8y+j5dclTv4IHMq5GRHQKWnBFg+t8Dxy5vQM+IE5H/s9sj6zhbAlahXf2olHkWMTxaSJWY6gUtTX13ch3+bReY7rBNmpkYIdS1T0M3Ns5Dmhj5XPAGEaP1gHpjFEzUwGG7hofmiQrNBHoNCnAp/aN3tDojxm6VMk98vqoPP5oXjqFm8f8L7j9ZK5c4/YVM5PL3uiAwpBhARMe1nIVM5xxk4ZyHI+1qSafW2LMXjI512zIEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=klNgxq4doYeESjjSjmv1yXG01PlVRtxfKFAm5gKvwXk=; b=SfZfASiaaEzcflWO5lQtio4CdT0Tv1SJwP1ZOhhfBSoh+OJ3tptFGVUwL5bxK6ZEdyCgikFksCCwa1psde4VPF544b8cCAzePPM7Wl8l7lBv0lx7hr6YlRLi/HklHLtMN6MNswisxtpyXU4Ciu7saOAFTsdlhOW2WhE+u6quNc6Urfw5Wrr3VQqCZL20sY8eFE1KJC4IOpJE0qIfXroDqh2mKuOSqdBeT0asILlBv2HNTRoqv+qyYisyf1HFRa2OxW51mAfvAoz1qOQetZL9aQNcl/1AYYi1VYWD682OmAi3vumhgaMUYReIajt1zmgQzdfdnPjUc8tEkXsWKwmD5w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=klNgxq4doYeESjjSjmv1yXG01PlVRtxfKFAm5gKvwXk=; b=TKgU2cLbN+Bhq3lwvJDtVmUoh9KhZc1kvMN43644bBYoV2wmIgpc9wzz9PxbKqOXBSmH0GMKCTMshl0n0JrxCvA9KJZrFXU0sbiCxlFGt3F2UC/wWy7wbv54cVSu9C8cQBYY1jaV7H1V61cr4E7foWRemLhI4AraVx3CggUN0O0uxatKkZsjC081OZVQh191td2o0RNN+zORp+HYUSWA17+uhoHoaPfuNSzx3IzIRtKQ6debPmLgh01hnMk7AiX609mMmUz2lJC02YK8McEwKSxnhrPpSpcp2pjbQoLGYx68Gn5WzNlBePj68b61KElsEHi02s/lIXoWLkeB3q+Ogg== Received: from BYAPR02CA0025.namprd02.prod.outlook.com (2603:10b6:a02:ee::38) by SA1PR12MB8095.namprd12.prod.outlook.com (2603:10b6:806:33f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.23; Fri, 25 Oct 2024 23:51:18 +0000 Received: from CO1PEPF000075EF.namprd03.prod.outlook.com (2603:10b6:a02:ee:cafe::77) by BYAPR02CA0025.outlook.office365.com (2603:10b6:a02:ee::38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20 via Frontend Transport; Fri, 25 Oct 2024 23:51:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF000075EF.mail.protection.outlook.com (10.167.249.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:17 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:05 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:04 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:51:03 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 12/13] iommu/arm-smmu-v3: Add arm_vsmmu_cache_invalidate Date: Fri, 25 Oct 2024 16:50:41 -0700 Message-ID: <16cb47d80cfd37028f6d32231a785a3c486239f5.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075EF:EE_|SA1PR12MB8095:EE_ X-MS-Office365-Filtering-Correlation-Id: 5de8bf90-2e41-458d-f040-08dcf54feb57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?olA5H4JYP0ZDO2FZwfdhD90RqJPnfSzBOH0rPYDSgDEsAyeS12T0qO7bbxZs?= =?us-ascii?Q?icWQULFJkuDRi8KGyxeDDlL6FWid0G1GKFglEKusbKE/vJtu4yIgOb9wu+T8?= =?us-ascii?Q?reH/5EiifOKH0fqAVRkuyymz1n5o+p8bYZMVBOOIvMvY2dqf2Ap6zO+Lyz1Z?= =?us-ascii?Q?U1EyPhRW7rTAgEA7e3HZupQH/vcP399wzB0oyBywBolnn6jg26+k5//q0JTG?= =?us-ascii?Q?dwmLSH5alC4LU6svLoVvHFv3eHztZEcAfLYpHm8Hcrxv3NAdBV0Lw+XwbWGO?= =?us-ascii?Q?GP0x9rFdtJNoK1SiJ8mSXx5notKvZCBaHS3RGFKETMvogeRGdGWwnPfZqOJR?= =?us-ascii?Q?agmGmZ4HE9e9QDjRtd1dtom70bO/s89IQueKUp0ggf1QR/B50zQuftFtUkFA?= =?us-ascii?Q?2HB5d+8Tjp19fukpMXQhkYYXUSuEHqHcYheKmiGBs82mq06n13ll8vexQ1rD?= =?us-ascii?Q?dvW7j21ww9Vi/PGKbNqav3TbMU+YIsRTMbUgOO/TMho4TYn4sVkY//2d5BlB?= =?us-ascii?Q?AWVeZkGnrzowl+2ih98kvm2vYyWuHRDUtjczXW7ah3v1/KltOw5DK9vNg7Pc?= =?us-ascii?Q?wk4bZtF8dbBzv1xQ/R6E1OBmUIyNciwQgmM8hGrMQk3spDV4yK3XaShQj4ci?= =?us-ascii?Q?XfyFc34itfIY218ie/+b5CIzCFi6jZds84kCCsnBA2eMWY2ufsKEqWkNktpn?= =?us-ascii?Q?XHkUqjA3GzJRl3VoPGW83OMPhC2CTWU5Unz71bMe12DWGLyeXyH0rBveLolK?= =?us-ascii?Q?p02eJa79rBdMVXN9QqUT0mKD6KMMQJztNWQ2XQasF8iqr3n6QeMZ5yBTM6Rz?= =?us-ascii?Q?t54gSuPZGzG4+JFRz4h2GjsJTxclVIpr/Jms9NknRtARav33RHZVPxLVqhPO?= =?us-ascii?Q?uMcg7lV1bOa9FAzOk+sj12E3BpM7emlKJvfmtR/b8JcwXCpQvzExatsarWQJ?= =?us-ascii?Q?P4lxSFhBXbdqQeaF6CPXMPjzEGd+bswKhlz+dMNDFe7CfrHSEjTtP+8yfDgw?= =?us-ascii?Q?3ugAbd3kUfADrmZ0MVDjEZoxMoljLz/IPab75NzXMthiTDcGRVVN4+1nF2PU?= =?us-ascii?Q?e4gH5xBTR7ELTAJEd9cBGMws17MYrNsCZ6aMyt8jYjf56L/PRmj8L8vAqpqG?= =?us-ascii?Q?VBu7Xon6eDyMLSYz0JxcD6sVwyeP4r+KmYGmlYtZreTgPZThxLJJpa179faf?= =?us-ascii?Q?s5iEO6cg7KAa/+dML3eUhtuWBBGGnMM5oiAVGcOvFi5rAjR6iCn35pQLrzSE?= =?us-ascii?Q?fkiQKWIj6UNV/j+GzSLcZzaD3BNkllfM1lg0x96U67z3xe6hhrZ9gXsV3abZ?= =?us-ascii?Q?xCkthLkKsFAGK5apPsN/8lGkw/5sApb5949LnhatVfo9WkqiQmlJrLd+BngB?= =?us-ascii?Q?s5RKLGAZtSAz+ahrct4R12YOSQ3SFQPwzBGq4/c2QZ3jvPTFiQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:17.8460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5de8bf90-2e41-458d-f040-08dcf54feb57 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075EF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8095 Content-Type: text/plain; charset="utf-8" Implement the vIOMMU's cache_invalidate op for user space to invalidate the IOTLB entries, Device ATS and CD entries that are still cached by hardware. Add struct iommu_viommu_arm_smmuv3_invalidate defining invalidation entries that are simply in the native format of a 128-bit TLBI command. Scan those commands against the permitted command list and fix their VMID/SID fields. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 + include/uapi/linux/iommufd.h | 24 ++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 130 ++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +- 4 files changed, 162 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 5a025d310dbe..8bd740f537ee 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -529,6 +529,7 @@ struct arm_smmu_cmdq_ent { #define CMDQ_OP_TLBI_NH_ALL 0x10 #define CMDQ_OP_TLBI_NH_ASID 0x11 #define CMDQ_OP_TLBI_NH_VA 0x12 + #define CMDQ_OP_TLBI_NH_VAA 0x13 #define CMDQ_OP_TLBI_EL2_ALL 0x20 #define CMDQ_OP_TLBI_EL2_ASID 0x21 #define CMDQ_OP_TLBI_EL2_VA 0x22 @@ -949,6 +950,10 @@ void arm_smmu_attach_commit(struct arm_smmu_attach_sta= te *state); void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, const struct arm_smmu_ste *target); =20 +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, + bool sync); + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); bool arm_smmu_master_sva_supported(struct arm_smmu_master *master); diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index c2c5f49fdf17..8e66e2fde1dd 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -686,9 +686,11 @@ struct iommu_hwpt_get_dirty_bitmap { * enum iommu_hwpt_invalidate_data_type - IOMMU HWPT Cache Invalidation * Data Type * @IOMMU_HWPT_INVALIDATE_DATA_VTD_S1: Invalidation data for VTD_S1 + * @IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3: Invalidation data for ARM SMM= Uv3 */ enum iommu_hwpt_invalidate_data_type { IOMMU_HWPT_INVALIDATE_DATA_VTD_S1 =3D 0, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3 =3D 1, }; =20 /** @@ -727,6 +729,28 @@ struct iommu_hwpt_vtd_s1_invalidate { __u32 __reserved; }; =20 +/** + * struct iommu_viommu_arm_smmuv3_invalidate - ARM SMMUv3 cahce invalidati= on + * (IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3) + * @cmd: 128-bit cache invalidation command that runs in SMMU CMDQ. + * Must be little-endian. + * + * Supported command list only when passing in a vIOMMU via @hwpt_id: + * CMDQ_OP_TLBI_NSNH_ALL + * CMDQ_OP_TLBI_NH_VA + * CMDQ_OP_TLBI_NH_VAA + * CMDQ_OP_TLBI_NH_ALL + * CMDQ_OP_TLBI_NH_ASID + * CMDQ_OP_ATC_INV + * CMDQ_OP_CFGI_CD + * CMDQ_OP_CFGI_CD_ALL + * + * -EIO will be returned if the command is not supported. + */ +struct iommu_viommu_arm_smmuv3_invalidate { + __aligned_le64 cmd[2]; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index abb6d2868376..2479074db820 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -184,9 +184,131 @@ arm_vsmmu_alloc_domain_nested(struct iommufd_viommu *= viommu, return &nested_domain->domain; } =20 +static int arm_vsmmu_vsid_to_sid(struct arm_vsmmu *vsmmu, u32 vsid, u32 *s= id) +{ + struct arm_smmu_master *master; + struct device *dev; + int ret =3D 0; + + xa_lock(&vsmmu->core.vdevs); + dev =3D iommufd_viommu_find_dev(&vsmmu->core, (unsigned long)vsid); + if (!dev) { + ret =3D -EIO; + goto unlock; + } + master =3D dev_iommu_priv_get(dev); + + /* At this moment, iommufd only supports PCI device that has one SID */ + if (sid) + *sid =3D master->streams[0].id; +unlock: + xa_unlock(&vsmmu->core.vdevs); + return ret; +} + +/* This is basically iommu_viommu_arm_smmuv3_invalidate in u64 for convers= ion */ +struct arm_vsmmu_invalidation_cmd { + u64 cmd[2]; +}; + +/* + * Convert, in place, the raw invalidation command into an internal format= that + * can be passed to arm_smmu_cmdq_issue_cmdlist(). Internally commands are + * stored in CPU endian. + * + * Enforce the VMID or SID on the command. + */ +static int arm_vsmmu_convert_user_cmd(struct arm_vsmmu *vsmmu, + struct arm_vsmmu_invalidation_cmd *cmd) +{ + /* Commands are le64 stored in u64 */ + cmd->cmd[0] =3D le64_to_cpu((__force __le64)cmd->cmd[0]); + cmd->cmd[1] =3D le64_to_cpu((__force __le64)cmd->cmd[1]); + + switch (cmd->cmd[0] & CMDQ_0_OP) { + case CMDQ_OP_TLBI_NSNH_ALL: + /* Convert to NH_ALL */ + cmd->cmd[0] =3D CMDQ_OP_TLBI_NH_ALL | + FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid); + cmd->cmd[1] =3D 0; + break; + case CMDQ_OP_TLBI_NH_VA: + case CMDQ_OP_TLBI_NH_VAA: + case CMDQ_OP_TLBI_NH_ALL: + case CMDQ_OP_TLBI_NH_ASID: + cmd->cmd[0] &=3D ~CMDQ_TLBI_0_VMID; + cmd->cmd[0] |=3D FIELD_PREP(CMDQ_TLBI_0_VMID, vsmmu->vmid); + break; + case CMDQ_OP_ATC_INV: + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: { + u32 sid, vsid =3D FIELD_GET(CMDQ_CFGI_0_SID, cmd->cmd[0]); + + if (arm_vsmmu_vsid_to_sid(vsmmu, vsid, &sid)) + return -EIO; + cmd->cmd[0] &=3D ~CMDQ_CFGI_0_SID; + cmd->cmd[0] |=3D FIELD_PREP(CMDQ_CFGI_0_SID, sid); + break; + } + default: + return -EIO; + } + return 0; +} + +static int arm_vsmmu_cache_invalidate(struct iommufd_viommu *viommu, + struct iommu_user_data_array *array) +{ + struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); + struct arm_smmu_device *smmu =3D vsmmu->smmu; + struct arm_vsmmu_invalidation_cmd *last; + struct arm_vsmmu_invalidation_cmd *cmds; + struct arm_vsmmu_invalidation_cmd *cur; + struct arm_vsmmu_invalidation_cmd *end; + int ret; + + cmds =3D kcalloc(array->entry_num, sizeof(*cmds), GFP_KERNEL); + if (!cmds) + return -ENOMEM; + cur =3D cmds; + end =3D cmds + array->entry_num; + + static_assert(sizeof(*cmds) =3D=3D 2 * sizeof(u64)); + ret =3D iommu_copy_struct_from_full_user_array( + cmds, sizeof(*cmds), array, + IOMMU_VIOMMU_INVALIDATE_DATA_ARM_SMMUV3); + if (ret) + goto out; + + last =3D cmds; + while (cur !=3D end) { + ret =3D arm_vsmmu_convert_user_cmd(vsmmu, cur); + if (ret) + goto out; + + /* FIXME work in blocks of CMDQ_BATCH_ENTRIES and copy each block? */ + cur++; + if (cur !=3D end && (cur - last) !=3D CMDQ_BATCH_ENTRIES - 1) + continue; + + /* FIXME always uses the main cmdq rather than trying to group by type */ + ret =3D arm_smmu_cmdq_issue_cmdlist(smmu, &smmu->cmdq, last->cmd, + cur - last, true); + if (ret) { + cur--; + goto out; + } + last =3D cur; + } +out: + array->entry_num =3D cur - cmds; + kfree(cmds); + return ret; +} =20 static const struct iommufd_viommu_ops arm_vsmmu_ops =3D { .alloc_domain_nested =3D arm_vsmmu_alloc_domain_nested, + .cache_invalidate =3D arm_vsmmu_cache_invalidate, }; =20 struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, @@ -206,6 +328,14 @@ struct iommufd_viommu *arm_vsmmu_alloc(struct device *= dev, if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) return ERR_PTR(-EOPNOTSUPP); =20 + /* + * FORCE_SYNC is not set with FEAT_NESTING. Some study of the exact HW + * defect is needed to determine if arm_vsmmu_cache_invalidate() needs + * any change to remove this. + */ + if (WARN_ON(smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) + return ERR_PTR(-EOPNOTSUPP); + /* * Must support some way to prevent the VM from bypassing the cache * because VFIO currently does not do any cache maintenance. diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 8215c49d3bac..d1abfb42d828 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -766,9 +766,9 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu= _cmdq *cmdq, u64 *cmds, * insert their own list of commands then all of the commands from one * CPU will appear before any of the commands from the other CPU. */ -static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq, - u64 *cmds, int n, bool sync) +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, u64 *cmds, int n, + bool sync) { u64 cmd_sync[CMDQ_ENT_DWORDS]; u32 prod; --=20 2.43.0 From nobody Mon Nov 25 13:34:55 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2078.outbound.protection.outlook.com [40.107.92.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07EF921E741; Fri, 25 Oct 2024 23:51:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.78 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900280; cv=fail; b=nc9Sl9X6f3Vcp+JCol0pRwsZuWhw0OMP/NJg7HTuqOQd1hToOwOhtusPb3AZ1DgI95LG5xRq02oFdfAudi13jO54TUUzm8N3DDribdMbLW76Mep6BnjxA5XG4Fnpu4TuIKOnd8gbAzWke6RfwHsrgJN90uNH9Ra/wNUo2Q9HnYU= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729900280; c=relaxed/simple; bh=z+CIohTvZsyvKVADtR5qfpa3ofDVquHGeTqJn6uFHOw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RTqLKb7EaUTTAcUUEWaAvc71tWI9mYczbGQjQbzWpQhQdQSSPhiSl7n2AWSWucyjPoKZG5XPAjH/61/JGUBbeOwNZUSSCi+LEEZPFoNm9klBPgzsdeQSo1ioGrXZdYCmyXXwdomz7NO4Vp71INAQOShtn1pz1h5hrpXAjz5fQKI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=MnOMBhpI; arc=fail smtp.client-ip=40.107.92.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="MnOMBhpI" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=IBQpg4GQIK0YTD5m18eiSGTibeooZ/qTQ0YdSsZaM04ZTopPIVUvaq9kQ/7kQVv39rgLgL6PxCChNt48VnsnI+SZN6g7V+ou5EMMYemkeACQWlrqfFFzf4JFybYLB7/oFCaILm58StwLUX4drjIuEnPHVgyZJYB5o95yD9MUDDKzA2K+Fo/QrJyna2aLWWTxZ0SDY+gJZjY8zCDv70cP7M3L7FLVFlYPJA1WVaT7tuvOjr1FWhQEqJP6J03Bz8Od9nU9c3+27Ejal6FSlhWHvBGhfdU/wA8aIo3wSlakRpx5YnNMtOs/2YEATvG7PpXA3KeOB+q5C1b9sX0CCgrqAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6F5obBqATICOdBkQz/EV+SUSAYbGIVH1Y1YVLS+PyJw=; b=nNfwxvLnjYn2e09hmRgZp1hDvpK1Veyx7jOgj8qZOKum+9CMa50IJTMIxvPCoWLQO7lZTDpoNrT76sFM7ZnI16XWK1iHPCKa6O/dfjf22jymxwEFWHRXh5MZWZK4P4v1c4U/pnjqHeCiw5G7KkXVVxQp6pWzAQEfWAueJf4/wakt+OnqPsfAC3KFz/uFOdQkRPyRPDavy5odLXRtB0H1rlgSDUyPjAgdj8UkSg1L9yS9wjVfsia9tQRN/0bhlzflHzsiNHTSX272KtZZccwm1bQf4bAarKSYiBEFgISZ+9oF1kQQzBzzAzq1fQLU+ZhhdGG6FUhQ/dwF0C0WUucImg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6F5obBqATICOdBkQz/EV+SUSAYbGIVH1Y1YVLS+PyJw=; b=MnOMBhpIAGrPTBXzTDtjn+VH1WusOeGfydecLlewxkL6PcYOPu/jWui31RWywVnHAEplxanpGo5t6eB+qciikMQWoYjyhHzXnzkPSwh1tnTIh896LtdFYIDWOSaHOc7Ft2+tRA6mq/XXQ3z6ZNjahO4KLsWnkX0mQC8Ja5I91E3m6ggu90ANKgQyfk1AaM4htrqWqqZwzQBcT01avRlVfn9IKzf24RfeFKjpPIS/ZdZc2b69C4Rr3ctLcMPE4cJoUHPCT5h11m5UrL/lhCQLQHIP5+3nRXQ1+n+6uo1QR2bY/oXZoSoGXSriHuiGYdZ0EWKQxx5Li3ot8lb7TgPQ8w== Received: from BYAPR05CA0083.namprd05.prod.outlook.com (2603:10b6:a03:e0::24) by SJ2PR12MB9114.namprd12.prod.outlook.com (2603:10b6:a03:567::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.20; Fri, 25 Oct 2024 23:51:13 +0000 Received: from SJ1PEPF000023CF.namprd02.prod.outlook.com (2603:10b6:a03:e0:cafe::71) by BYAPR05CA0083.outlook.office365.com (2603:10b6:a03:e0::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8114.8 via Frontend Transport; Fri, 25 Oct 2024 23:51:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by SJ1PEPF000023CF.mail.protection.outlook.com (10.167.244.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 23:51:13 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:06 -0700 Received: from drhqmail203.nvidia.com (10.126.190.182) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 25 Oct 2024 16:51:05 -0700 Received: from Asurada-Nvidia.nvidia.com (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 25 Oct 2024 16:51:04 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 13/13] iommu/arm-smmu-v3: Allow ATS for IOMMU_DOMAIN_NESTED Date: Fri, 25 Oct 2024 16:50:42 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|SJ2PR12MB9114:EE_ X-MS-Office365-Filtering-Correlation-Id: a3ed0ed8-0ff2-4cdc-851d-08dcf54fe8db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?As/6TN2aEMi2wxWHJ1a/Pbx7Z/i65/e1BXV9DN1ebpy/glTOth65hm9pdM+r?= =?us-ascii?Q?/n9x4xcfD2Ge8LNuJKi7/WpxNH3du6qQuh1eNwovNiM+nPQqVtEnm/bK6+HB?= =?us-ascii?Q?XKF1UnarIfcAdDWUms2XCNRep1LyYEBoPiNNl2oAhV2uzE3vtiRuz4JiHeot?= =?us-ascii?Q?eFgswfFZI9VJQ9FPIl1IZPXkzFJ/MSiEhBzCIM4Kn2aJqYtpdYtfZMA7lIlE?= =?us-ascii?Q?1FzGnGC802P2GuLenljazvhv8mIb1ZhpXjv8YqxOh0z2TgrDkuRpSwmsTpku?= =?us-ascii?Q?9edg8nLas3AYfW7gVzVylpJ7Xs7JG9fzY466BcG9w0qsoBNGZOHIxgP0/CDZ?= =?us-ascii?Q?R/ZIxUjH0aHerMVG3enGpcD8wZaW+VhuIL0TV7es40xlt7g34PisOJpz1Hbd?= =?us-ascii?Q?J79JfArUoySJpnIgp6BPPY04qRhB9G/LwdlVqkApuFB+op+5fDEd94sy37ZT?= =?us-ascii?Q?2AkBd5RD/uNxqkE7IQRZlk1Tk8KmHwVWv1uFbD1yF7x89T0PSdIRL2yEaVki?= =?us-ascii?Q?rsq7hGZpdTIZHjrzGhRiFae5kaTi5hn1HEG/ZCpyDl5iHnZsfFymgHRPf6/p?= =?us-ascii?Q?QT1GqVEaFHCbGtnV65rMytek6EKEn1yFJvabOZs/Il5cUshGRL16tibeM/Nr?= =?us-ascii?Q?0c+0r2r/kgPYEq5wneOu5Z/4uDdoHtWbFr8T31zFTX43Sp4CxLnLwAkgQKI4?= =?us-ascii?Q?Eb+wat1uOGplGNUZdIYZrwPgei5LRwLPus28JfzMWVuUSY0DW+nmdLTYn2R8?= =?us-ascii?Q?9Avh7lJS8gs35WgxE4PR6a3Xo26oURlRPzGrDKCAqzeocq1E8FaOIxf31D5P?= =?us-ascii?Q?LA/MIpJe8UVHWlcDZXNvwxNKH4iyoRxq2ISGeiVhSgNaTdQgdZU7FKZIColf?= =?us-ascii?Q?bwbNId2QPWrJ6Rsfke15tQLlabTCYHrwmn22M+WDQlR2gCs6jeSHgJF3vxpt?= =?us-ascii?Q?V0TY3xLtTqR+K+uSQySlftqCdiskRipPXfKeioihU9h3mptDU7hKnT41u7e3?= =?us-ascii?Q?neaxd8/MbuMoj5ZvkseYhBdDiJMUXED8ls1xbdwsmAVQjnZhmZJCiC55t9vi?= =?us-ascii?Q?VhwRpnMKHN92p/lTAyz4KpkP8WPuNro6oQIj7IOR5YMCWPh9CK0K6oYejSPv?= =?us-ascii?Q?dabDwfjmA77Pp4W5p98NwGMhGBX0EY4GcbH6YnBWWk7Zz7upMkr+7gkiapgG?= =?us-ascii?Q?cc2dl2ywsN9u/T87gfyeofn1NbhdDNhKLsW+vWMoqrONWR8qh4f5kIVoPVeu?= =?us-ascii?Q?vuXMrNy5w40ACjHvir4W4/6BXBd0P5xQh9DOTpbNkznXmprJH8Y5VRd3+kUb?= =?us-ascii?Q?9+Fo287wpT4hvHaOSwSzStHLwsJC2k8dB34VFUh/IT5z8NEyA4d665rDCCjT?= =?us-ascii?Q?UdxpBjJhQEzBVOARuDEBZnr8k/SPKGDhtNKX05JOIockThjg1Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:13.7533 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3ed0ed8-0ff2-4cdc-851d-08dcf54fe8db X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9114 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Now, ATC invalidation can be done with the vIOMMU invalidation op. A guest owned IOMMU_DOMAIN_NESTED can do an ATS too. Allow it to pass in the EATS field via the vSTE words. Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++- include/uapi/linux/iommufd.h | 2 +- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 31 ++++++++++++++++--- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 26 +++++++++++++--- 4 files changed, 53 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 8bd740f537ee..af25f092303f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -305,7 +305,7 @@ static inline u32 arm_smmu_strtab_l2_idx(u32 sid) #define STRTAB_STE_1_NESTING_ALLOWED \ cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | \ STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | \ - STRTAB_STE_1_S1STALLD) + STRTAB_STE_1_S1STALLD | STRTAB_STE_1_EATS) =20 /* * Context descriptors. @@ -838,6 +838,7 @@ struct arm_smmu_domain { struct arm_smmu_nested_domain { struct iommu_domain domain; struct arm_vsmmu *vsmmu; + bool enable_ats : 1; =20 __le64 ste[2]; }; @@ -879,6 +880,7 @@ struct arm_smmu_master_domain { struct list_head devices_elm; struct arm_smmu_master *master; ioasid_t ssid; + bool nested_ats_flush : 1; }; =20 static inline struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *= dom) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 8e66e2fde1dd..056ba05a8022 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -404,7 +404,7 @@ struct iommu_hwpt_vtd_s1 { * a user stage-1 Context Descriptor Table. Must be little-endian. * Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW S= pec) * - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax - * - word-1: S1DSS, S1CIR, S1COR, S1CSH, S1STALLD + * - word-1: EATS, S1DSS, S1CIR, S1COR, S1CSH, S1STALLD * * -EIO will be returned if @ste is not legal or contains any non-allowed = field. * Cfg can be used to select a S1, Bypass or Abort configuration. A Bypass diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 2479074db820..c0c5cd807d34 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -96,8 +96,6 @@ static int arm_smmu_attach_dev_nested(struct iommu_domain= *domain, .master =3D master, .old_domain =3D iommu_get_domain_for_dev(dev), .ssid =3D IOMMU_NO_PASID, - /* Currently invalidation of ATC is not supported */ - .disable_ats =3D true, }; struct arm_smmu_ste ste; int ret; @@ -108,6 +106,15 @@ static int arm_smmu_attach_dev_nested(struct iommu_dom= ain *domain, return -EBUSY; =20 mutex_lock(&arm_smmu_asid_lock); + /* + * The VM has to control the actual ATS state at the PCI device because + * we forward the invalidations directly from the VM. If the VM doesn't + * think ATS is on it will not generate ATC flushes and the ATC will + * become incoherent. Since we can't access the actual virtual PCI ATS + * config bit here base this off the EATS value in the STE. If the EATS + * is set then the VM must generate ATC flushes. + */ + state.disable_ats =3D !nested_domain->enable_ats; ret =3D arm_smmu_attach_prepare(&state, domain); if (ret) { mutex_unlock(&arm_smmu_asid_lock); @@ -132,8 +139,10 @@ static const struct iommu_domain_ops arm_smmu_nested_o= ps =3D { .free =3D arm_smmu_domain_nested_free, }; =20 -static int arm_smmu_validate_vste(struct iommu_hwpt_arm_smmuv3 *arg) +static int arm_smmu_validate_vste(struct iommu_hwpt_arm_smmuv3 *arg, + bool *enable_ats) { + unsigned int eats; unsigned int cfg; =20 if (!(arg->ste[0] & cpu_to_le64(STRTAB_STE_0_V))) { @@ -150,6 +159,18 @@ static int arm_smmu_validate_vste(struct iommu_hwpt_ar= m_smmuv3 *arg) if (cfg !=3D STRTAB_STE_0_CFG_ABORT && cfg !=3D STRTAB_STE_0_CFG_BYPASS && cfg !=3D STRTAB_STE_0_CFG_S1_TRANS) return -EIO; + + /* + * Only Full ATS or ATS UR is supported + * The EATS field will be set by arm_smmu_make_nested_domain_ste() + */ + eats =3D FIELD_GET(STRTAB_STE_1_EATS, le64_to_cpu(arg->ste[1])); + arg->ste[1] &=3D ~cpu_to_le64(STRTAB_STE_1_EATS); + if (eats !=3D STRTAB_STE_1_EATS_ABT && eats !=3D STRTAB_STE_1_EATS_TRANS) + return -EIO; + + if (cfg =3D=3D STRTAB_STE_0_CFG_S1_TRANS) + *enable_ats =3D (eats =3D=3D STRTAB_STE_1_EATS_TRANS); return 0; } =20 @@ -160,6 +181,7 @@ arm_vsmmu_alloc_domain_nested(struct iommufd_viommu *vi= ommu, struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); struct arm_smmu_nested_domain *nested_domain; struct iommu_hwpt_arm_smmuv3 arg; + bool enable_ats =3D false; int ret; =20 ret =3D iommu_copy_struct_from_user(&arg, user_data, @@ -167,7 +189,7 @@ arm_vsmmu_alloc_domain_nested(struct iommufd_viommu *vi= ommu, if (ret) return ERR_PTR(ret); =20 - ret =3D arm_smmu_validate_vste(&arg); + ret =3D arm_smmu_validate_vste(&arg, &enable_ats); if (ret) return ERR_PTR(ret); =20 @@ -177,6 +199,7 @@ arm_vsmmu_alloc_domain_nested(struct iommufd_viommu *vi= ommu, =20 nested_domain->domain.type =3D IOMMU_DOMAIN_NESTED; nested_domain->domain.ops =3D &arm_smmu_nested_ops; + nested_domain->enable_ats =3D enable_ats; nested_domain->vsmmu =3D vsmmu; nested_domain->ste[0] =3D arg.ste[0]; nested_domain->ste[1] =3D arg.ste[1] & ~cpu_to_le64(STRTAB_STE_1_EATS); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index d1abfb42d828..10b4dbc8d027 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2107,7 +2107,16 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *= smmu_domain, if (!master->ats_enabled) continue; =20 - arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, &cmd); + if (master_domain->nested_ats_flush) { + /* + * If a S2 used as a nesting parent is changed we have + * no option but to completely flush the ATC. + */ + arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); + } else { + arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, + &cmd); + } =20 for (i =3D 0; i < master->num_streams; i++) { cmd.atc.sid =3D master->streams[i].id; @@ -2631,7 +2640,7 @@ static void arm_smmu_disable_pasid(struct arm_smmu_ma= ster *master) static struct arm_smmu_master_domain * arm_smmu_find_master_domain(struct arm_smmu_domain *smmu_domain, struct arm_smmu_master *master, - ioasid_t ssid) + ioasid_t ssid, bool nested_ats_flush) { struct arm_smmu_master_domain *master_domain; =20 @@ -2640,7 +2649,8 @@ arm_smmu_find_master_domain(struct arm_smmu_domain *s= mmu_domain, list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) { if (master_domain->master =3D=3D master && - master_domain->ssid =3D=3D ssid) + master_domain->ssid =3D=3D ssid && + master_domain->nested_ats_flush =3D=3D nested_ats_flush) return master_domain; } return NULL; @@ -2671,13 +2681,18 @@ static void arm_smmu_remove_master_domain(struct ar= m_smmu_master *master, { struct arm_smmu_domain *smmu_domain =3D to_smmu_domain_devices(domain); struct arm_smmu_master_domain *master_domain; + bool nested_ats_flush =3D false; unsigned long flags; =20 if (!smmu_domain) return; =20 + if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) + nested_ats_flush =3D to_smmu_nested_domain(domain)->enable_ats; + spin_lock_irqsave(&smmu_domain->devices_lock, flags); - master_domain =3D arm_smmu_find_master_domain(smmu_domain, master, ssid); + master_domain =3D arm_smmu_find_master_domain(smmu_domain, master, ssid, + nested_ats_flush); if (master_domain) { list_del(&master_domain->devices_elm); kfree(master_domain); @@ -2744,6 +2759,9 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, return -ENOMEM; master_domain->master =3D master; master_domain->ssid =3D state->ssid; + if (new_domain->type =3D=3D IOMMU_DOMAIN_NESTED) + master_domain->nested_ats_flush =3D + to_smmu_nested_domain(new_domain)->enable_ats; =20 /* * During prepare we want the current smmu_domain and new --=20 2.43.0