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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:42:21.7586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c47e8ca9-ce95-456f-e0e7-08dcf3926e31 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE35.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5720 Content-Type: text/plain; charset="utf-8" The RMPREAD instruction returns an architecture defined format of an RMP entry. This is the preferred method for examining RMP entries. In preparation for using the RMPREAD instruction, convert the existing code that directly accesses the RMP to map the raw RMP information into the architecture defined format. RMPREAD output returns a status bit for the 2MB region status. If the input page address is 2MB aligned and any other pages within the 2MB region are assigned, then 2MB region status will be set to 1. Otherwise, the 2MB region status will be set to 0. For systems that do not support RMPREAD, calculating this value would require looping over all of the RMP table entries within that range until one is found with the assigned bit set. Since this bit is not defined in the current format, and so not used today, do not incur the overhead associated with calculating it. Signed-off-by: Tom Lendacky Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/virt/svm/sev.c | 121 +++++++++++++++++++++++++++++----------- 1 file changed, 87 insertions(+), 34 deletions(-) diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index 0ce17766c0e5..4d095affdb4d 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -30,6 +30,22 @@ #include #include =20 +/* + * The RMP entry format as returned by the RMPREAD instruction. + */ +struct rmpread { + u64 gpa; + u8 assigned :1, + rsvd1 :7; + u8 pagesize :1, + hpage_region_status :1, + rsvd2 :6; + u8 immutable :1, + rsvd3 :7; + u8 rsvd4; + u32 asid; +} __packed; + /* * The RMP entry format is not architectural. The format is defined in PPR * Family 19h Model 01h, Rev B1 processor. @@ -270,48 +286,77 @@ static int __init snp_rmptable_init(void) */ device_initcall(snp_rmptable_init); =20 -static struct rmpentry *get_rmpentry(u64 pfn) +static struct rmpentry *__get_rmpentry(u64 pfn) { - if (WARN_ON_ONCE(pfn > rmptable_max_pfn)) - return ERR_PTR(-EFAULT); - - return &rmptable[pfn]; -} - -static struct rmpentry *__snp_lookup_rmpentry(u64 pfn, int *level) -{ - struct rmpentry *large_entry, *entry; - - if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) + if (!rmptable) return ERR_PTR(-ENODEV); =20 - entry =3D get_rmpentry(pfn); - if (IS_ERR(entry)) - return entry; + if (unlikely(pfn > rmptable_max_pfn)) + return ERR_PTR(-EFAULT); + + return rmptable + pfn; +} + +static int get_rmpentry(u64 pfn, struct rmpread *entry) +{ + struct rmpentry *e; + + e =3D __get_rmpentry(pfn); + if (IS_ERR(e)) + return PTR_ERR(e); + + /* + * Map the RMP table entry onto the RMPREAD output format. + * The 2MB region status indicator (hpage_region_status field) is not + * calculated, since the overhead could be significant and the field + * is not used. + */ + memset(entry, 0, sizeof(*entry)); + entry->gpa =3D e->gpa << PAGE_SHIFT; + entry->asid =3D e->asid; + entry->assigned =3D e->assigned; + entry->pagesize =3D e->pagesize; + entry->immutable =3D e->immutable; + + return 0; +} + +static int __snp_lookup_rmpentry(u64 pfn, struct rmpread *entry, int *leve= l) +{ + struct rmpread large_entry; + int ret; + + if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) + return -ENODEV; + + ret =3D get_rmpentry(pfn, entry); + if (ret) + return ret; =20 /* * Find the authoritative RMP entry for a PFN. This can be either a 4K * RMP entry or a special large RMP entry that is authoritative for a * whole 2M area. */ - large_entry =3D get_rmpentry(pfn & PFN_PMD_MASK); - if (IS_ERR(large_entry)) - return large_entry; + ret =3D get_rmpentry(pfn & PFN_PMD_MASK, &large_entry); + if (ret) + return ret; =20 - *level =3D RMP_TO_PG_LEVEL(large_entry->pagesize); + *level =3D RMP_TO_PG_LEVEL(large_entry.pagesize); =20 - return entry; + return 0; } =20 int snp_lookup_rmpentry(u64 pfn, bool *assigned, int *level) { - struct rmpentry *e; + struct rmpread rmpread; + int ret; =20 - e =3D __snp_lookup_rmpentry(pfn, level); - if (IS_ERR(e)) - return PTR_ERR(e); + ret =3D __snp_lookup_rmpentry(pfn, &rmpread, level); + if (ret) + return ret; =20 - *assigned =3D !!e->assigned; + *assigned =3D !!rmpread.assigned; return 0; } EXPORT_SYMBOL_GPL(snp_lookup_rmpentry); @@ -324,18 +369,26 @@ EXPORT_SYMBOL_GPL(snp_lookup_rmpentry); */ static void dump_rmpentry(u64 pfn) { - u64 pfn_i, pfn_end; + struct rmpread rmpread; struct rmpentry *e; - int level; + u64 pfn_i, pfn_end; + int level, ret; =20 - e =3D __snp_lookup_rmpentry(pfn, &level); - if (IS_ERR(e)) { - pr_err("Failed to read RMP entry for PFN 0x%llx, error %ld\n", - pfn, PTR_ERR(e)); + ret =3D __snp_lookup_rmpentry(pfn, &rmpread, &level); + if (ret) { + pr_err("Failed to read RMP entry for PFN 0x%llx, error %d\n", + pfn, ret); return; } =20 - if (e->assigned) { + if (rmpread.assigned) { + e =3D __get_rmpentry(pfn); + if (IS_ERR(e)) { + pr_err("Failed to read RMP contents for PFN 0x%llx, error %ld\n", + pfn, PTR_ERR(e)); + return; + } + pr_info("PFN 0x%llx, RMP entry: [0x%016llx - 0x%016llx]\n", pfn, e->lo, e->hi); return; @@ -356,9 +409,9 @@ static void dump_rmpentry(u64 pfn) pfn, pfn_i, pfn_end); =20 while (pfn_i < pfn_end) { - e =3D __snp_lookup_rmpentry(pfn_i, &level); + e =3D __get_rmpentry(pfn_i); if (IS_ERR(e)) { - pr_err("Error %ld reading RMP entry for PFN 0x%llx\n", + pr_err("Error %ld reading RMP contents for PFN 0x%llx\n", PTR_ERR(e), pfn_i); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:42:31.4777 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11cf8ba9-0eb2-49ff-470b-08dcf39273ff X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8136 Content-Type: text/plain; charset="utf-8" The RMPREAD instruction returns an architecture defined format of an RMP table entry. This is the preferred method for examining RMP entries. The instruction is advertised in CPUID 0x8000001f_EAX[21]. Use this instruction when available. Signed-off-by: Tom Lendacky Reviewed-by: Ashish Kalra Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/virt/svm/sev.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 913fd3a7bac6..89c1308cdf54 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -448,6 +448,7 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache= coherency */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full= debug state swap support */ +#define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ =20 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word = 20 */ diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index 4d095affdb4d..e197610b4eed 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -301,6 +301,17 @@ static int get_rmpentry(u64 pfn, struct rmpread *entry) { struct rmpentry *e; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:42:36.7164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c6e5c06-c679-4c1e-a4d4-08dcf392771e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5838 Content-Type: text/plain; charset="utf-8" Limit usage of the non-architectural RMP format to Zen3/Zen4 processors. The RMPREAD instruction, with architectural defined output, is available and should be used for RMP access beyond Zen4. Signed-off-by: Tom Lendacky Reviewed-by: Ashish Kalra Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/kernel/cpu/amd.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index fab5caec0b72..547bcdf50f1b 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -355,10 +355,15 @@ static void bsp_determine_snp(struct cpuinfo_x86 *c) /* * RMP table entry format is not architectural and is defined by the * per-processor PPR. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:42:43.4234 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d39b6a94-ada5-4abc-0e5e-08dcf3927b1e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE33.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4468 Content-Type: text/plain; charset="utf-8" To make patch review easier for the segmented RMP support, move the SNP probe function out from in between the initialization-related routines. No functional change. Signed-off-by: Tom Lendacky Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/virt/svm/sev.c | 60 ++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index e197610b4eed..d0fca9bb2e12 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -132,36 +132,6 @@ static __init void snp_enable(void *arg) __snp_enable(smp_processor_id()); } =20 -#define RMP_ADDR_MASK GENMASK_ULL(51, 13) - -bool snp_probe_rmptable_info(void) -{ - u64 rmp_sz, rmp_base, rmp_end; - - rdmsrl(MSR_AMD64_RMP_BASE, rmp_base); - rdmsrl(MSR_AMD64_RMP_END, rmp_end); - - if (!(rmp_base & RMP_ADDR_MASK) || !(rmp_end & RMP_ADDR_MASK)) { - pr_err("Memory for the RMP table has not been reserved by BIOS\n"); - return false; - } - - if (rmp_base > rmp_end) { - pr_err("RMP configuration not valid: base=3D%#llx, end=3D%#llx\n", rmp_b= ase, rmp_end); - return false; - } - - rmp_sz =3D rmp_end - rmp_base + 1; - - probed_rmp_base =3D rmp_base; - probed_rmp_size =3D rmp_sz; - - pr_info("RMP table physical range [0x%016llx - 0x%016llx]\n", - rmp_base, rmp_end); - - return true; -} - static void __init __snp_fixup_e820_tables(u64 pa) { if (IS_ALIGNED(pa, PMD_SIZE)) @@ -286,6 +256,36 @@ static int __init snp_rmptable_init(void) */ device_initcall(snp_rmptable_init); =20 +#define RMP_ADDR_MASK GENMASK_ULL(51, 13) + +bool snp_probe_rmptable_info(void) +{ + u64 rmp_sz, rmp_base, rmp_end; + + rdmsrl(MSR_AMD64_RMP_BASE, rmp_base); + rdmsrl(MSR_AMD64_RMP_END, rmp_end); + + if (!(rmp_base & RMP_ADDR_MASK) || !(rmp_end & RMP_ADDR_MASK)) { + pr_err("Memory for the RMP table has not been reserved by BIOS\n"); + return false; + } + + if (rmp_base > rmp_end) { + pr_err("RMP configuration not valid: base=3D%#llx, end=3D%#llx\n", rmp_b= ase, rmp_end); + return false; + } + + rmp_sz =3D rmp_end - rmp_base + 1; + + probed_rmp_base =3D rmp_base; + probed_rmp_size =3D rmp_sz; + + pr_info("RMP table physical range [0x%016llx - 0x%016llx]\n", + rmp_base, rmp_end); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:42:50.5914 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 146b3646-1a17-4ed4-cb64-08dcf3927f63 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE30.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8461 Content-Type: text/plain; charset="utf-8" In preparation for support of a segmented RMP table, map only the RMP table entries. The RMP bookkeeping area is only ever accessed when first enabling SNP and does not need to remain mapped. To accomplish this, split the initialization of the RMP bookkeeping area and the initialization of the RMP entry area. The RMP bookkeeping area will be mapped only while it is being initialized. Signed-off-by: Tom Lendacky Reviewed-by: Ashish Kalra Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/virt/svm/sev.c | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index d0fca9bb2e12..dd256e76e443 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -168,6 +168,23 @@ void __init snp_fixup_e820_tables(void) __snp_fixup_e820_tables(probed_rmp_base + probed_rmp_size); } =20 +static bool __init init_rmptable_bookkeeping(void) +{ + void *bk; + + bk =3D memremap(probed_rmp_base, RMPTABLE_CPU_BOOKKEEPING_SZ, MEMREMAP_WB= ); + if (!bk) { + pr_err("Failed to map RMP bookkeeping area\n"); + return false; + } + + memset(bk, 0, RMPTABLE_CPU_BOOKKEEPING_SZ); + + memunmap(bk); + + return true; +} + /* * Do the necessary preparations which are verified by the firmware as * described in the SNP_INIT_EX firmware command description in the SNP @@ -205,12 +222,17 @@ static int __init snp_rmptable_init(void) goto nosnp; } =20 - rmptable_start =3D memremap(probed_rmp_base, probed_rmp_size, MEMREMAP_WB= ); + /* Map only the RMP entries */ + rmptable_start =3D memremap(probed_rmp_base + RMPTABLE_CPU_BOOKKEEPING_SZ, + probed_rmp_size - RMPTABLE_CPU_BOOKKEEPING_SZ, + MEMREMAP_WB); if (!rmptable_start) { pr_err("Failed to map RMP table\n"); goto nosnp; } =20 + rmptable_size =3D probed_rmp_size - RMPTABLE_CPU_BOOKKEEPING_SZ; + /* * Check if SEV-SNP is already enabled, this can happen in case of * kexec boot. @@ -219,7 +241,14 @@ static int __init snp_rmptable_init(void) if (val & MSR_AMD64_SYSCFG_SNP_EN) goto skip_enable; =20 - memset(rmptable_start, 0, probed_rmp_size); + /* Zero out the RMP bookkeeping area */ + if (!init_rmptable_bookkeeping()) { + memunmap(rmptable_start); + goto nosnp; + } + + /* Zero out the RMP entries */ + memset(rmptable_start, 0, rmptable_size); =20 /* Flush the caches to ensure that data is written before SNP is enabled.= */ wbinvd_on_all_cpus(); @@ -230,9 +259,6 @@ static int __init snp_rmptable_init(void) on_each_cpu(snp_enable, NULL, 1); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:42:57.6807 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62fd3202-e7ef-4ec6-c7c5-08dcf3928398 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE31.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4040 Content-Type: text/plain; charset="utf-8" In preparation for support of a segmented RMP table, treat the contiguous RMP table as a segmented RMP table with a single segment covering all of memory. By treating a contiguous RMP table as a single segment, much of the code that initializes and accesses the RMP can be re-used. Segmented RMP tables can have up to 512 segment entries. Each segment will have metadata associated with it to identify the segment location, the segment size, etc. The segment data and the physical address are used to determine the index of the segment within the table and then the RMP entry within the segment. For an actual segmented RMP table environment, much of the segment information will come from a configuration MSR. For the contiguous RMP, though, much of the information will be statically defined. Signed-off-by: Tom Lendacky Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/virt/svm/sev.c | 193 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 174 insertions(+), 19 deletions(-) diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index dd256e76e443..043b2582e10e 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #include #include @@ -74,12 +75,42 @@ struct rmpentry { */ #define RMPTABLE_CPU_BOOKKEEPING_SZ 0x4000 =20 +/* + * For a non-segmented RMP table, use the maximum physical addressing as t= he + * segment size in order to always arrive at index 0 in the table. + */ +#define RMPTABLE_NON_SEGMENTED_SHIFT 52 + +struct rmp_segment_desc { + struct rmpentry *rmp_entry; + u64 max_index; + u64 size; +}; + +/* + * Segmented RMP Table support. + * - The segment size is used for two purposes: + * - Identify the amount of memory covered by an RMP segment + * - Quickly locate an RMP segment table entry for a physical address + * + * - The RMP segment table contains pointers to an RMP table that covers + * a specific portion of memory. There can be up to 512 8-byte entries, + * one pages worth. + */ +static struct rmp_segment_desc **rmp_segment_table __ro_after_init; +static unsigned int rst_max_index __ro_after_init =3D 512; + +static u64 rmp_segment_size_max; +static unsigned int rmp_segment_coverage_shift; +static u64 rmp_segment_coverage_size; +static u64 rmp_segment_coverage_mask; +#define RST_ENTRY_INDEX(x) ((x) >> rmp_segment_coverage_shift) +#define RMP_ENTRY_INDEX(x) ((u64)(PHYS_PFN((x) & rmp_segment_coverage_mask= ))) + /* Mask to apply to a PFN to get the first PFN of a 2MB page */ #define PFN_PMD_MASK GENMASK_ULL(63, PMD_SHIFT - PAGE_SHIFT) =20 static u64 probed_rmp_base, probed_rmp_size; -static struct rmpentry *rmptable __ro_after_init; -static u64 rmptable_max_pfn __ro_after_init; =20 static LIST_HEAD(snp_leaked_pages_list); static DEFINE_SPINLOCK(snp_leaked_pages_list_lock); @@ -185,6 +216,92 @@ static bool __init init_rmptable_bookkeeping(void) return true; } =20 +static bool __init alloc_rmp_segment_desc(u64 segment_pa, u64 segment_size= , u64 pa) +{ + struct rmp_segment_desc *desc; + void *rmp_segment; + u64 rst_index; + + /* Validate the RMP segment size */ + if (segment_size > rmp_segment_size_max) { + pr_err("Invalid RMP size (%#llx) for configured segment size (%#llx)\n", + segment_size, rmp_segment_size_max); + return false; + } + + /* Validate the RMP segment table index */ + rst_index =3D RST_ENTRY_INDEX(pa); + if (rst_index >=3D rst_max_index) { + pr_err("Invalid RMP segment base address (%#llx) for configured segment = size (%#llx)\n", + pa, rmp_segment_coverage_size); + return false; + } + rst_index =3D array_index_nospec(rst_index, rst_max_index); + + if (rmp_segment_table[rst_index]) { + pr_err("RMP segment descriptor already exists at index %llu\n", rst_inde= x); + return false; + } + + /* Map the RMP entries */ + rmp_segment =3D memremap(segment_pa, segment_size, MEMREMAP_WB); + if (!rmp_segment) { + pr_err("Failed to map RMP segment addr 0x%llx size 0x%llx\n", + segment_pa, segment_size); + return false; + } + + desc =3D kzalloc(sizeof(*desc), GFP_KERNEL); + if (!desc) { + memunmap(rmp_segment); + return false; + } + + desc->rmp_entry =3D rmp_segment; + desc->max_index =3D segment_size / sizeof(*desc->rmp_entry); + desc->size =3D segment_size; + + /* Add the segment descriptor to the table */ + rmp_segment_table[rst_index] =3D desc; + + return true; +} + +static void __init free_rmp_segment_table(void) +{ + unsigned int i; + + for (i =3D 0; i < rst_max_index; i++) { + struct rmp_segment_desc *desc; + + desc =3D rmp_segment_table[i]; + if (!desc) + continue; + + memunmap(desc->rmp_entry); + + kfree(desc); + } + + free_page((unsigned long)rmp_segment_table); + + rmp_segment_table =3D NULL; +} + +static bool __init alloc_rmp_segment_table(void) +{ + struct page *page; + + /* Allocate the table used to index into the RMP segments */ + page =3D alloc_page(__GFP_ZERO); + if (!page) + return false; + + rmp_segment_table =3D page_address(page); + + return true; +} + /* * Do the necessary preparations which are verified by the firmware as * described in the SNP_INIT_EX firmware command description in the SNP @@ -192,8 +309,8 @@ static bool __init init_rmptable_bookkeeping(void) */ static int __init snp_rmptable_init(void) { - u64 max_rmp_pfn, calc_rmp_sz, rmptable_size, rmp_end, val; - void *rmptable_start; + u64 max_rmp_pfn, calc_rmp_sz, rmptable_segment, rmptable_size, rmp_end, v= al; + unsigned int i; =20 if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) return 0; @@ -222,17 +339,18 @@ static int __init snp_rmptable_init(void) goto nosnp; } =20 + if (!alloc_rmp_segment_table()) + goto nosnp; + /* Map only the RMP entries */ - rmptable_start =3D memremap(probed_rmp_base + RMPTABLE_CPU_BOOKKEEPING_SZ, - probed_rmp_size - RMPTABLE_CPU_BOOKKEEPING_SZ, - MEMREMAP_WB); - if (!rmptable_start) { - pr_err("Failed to map RMP table\n"); + rmptable_segment =3D probed_rmp_base + RMPTABLE_CPU_BOOKKEEPING_SZ; + rmptable_size =3D probed_rmp_size - RMPTABLE_CPU_BOOKKEEPING_SZ; + + if (!alloc_rmp_segment_desc(rmptable_segment, rmptable_size, 0)) { + free_rmp_segment_table(); goto nosnp; } =20 - rmptable_size =3D probed_rmp_size - RMPTABLE_CPU_BOOKKEEPING_SZ; - /* * Check if SEV-SNP is already enabled, this can happen in case of * kexec boot. @@ -243,12 +361,20 @@ static int __init snp_rmptable_init(void) =20 /* Zero out the RMP bookkeeping area */ if (!init_rmptable_bookkeeping()) { - memunmap(rmptable_start); + free_rmp_segment_table(); goto nosnp; } =20 /* Zero out the RMP entries */ - memset(rmptable_start, 0, rmptable_size); + for (i =3D 0; i < rst_max_index; i++) { + struct rmp_segment_desc *desc; + + desc =3D rmp_segment_table[i]; + if (!desc) + continue; + + memset(desc->rmp_entry, 0, desc->size); + } =20 /* Flush the caches to ensure that data is written before SNP is enabled.= */ wbinvd_on_all_cpus(); @@ -259,9 +385,6 @@ static int __init snp_rmptable_init(void) on_each_cpu(snp_enable, NULL, 1); =20 skip_enable: - rmptable =3D (struct rmpentry *)rmptable_start; - rmptable_max_pfn =3D rmptable_size / sizeof(struct rmpentry) - 1; - cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/rmptable_init:online", __snp_= enable, NULL); =20 /* @@ -282,6 +405,17 @@ static int __init snp_rmptable_init(void) */ device_initcall(snp_rmptable_init); =20 +static void set_rmp_segment_info(unsigned int segment_shift) +{ + rmp_segment_coverage_shift =3D segment_shift; + rmp_segment_coverage_size =3D 1ULL << rmp_segment_coverage_shift; + rmp_segment_coverage_mask =3D rmp_segment_coverage_size - 1; + + /* Calculate the maximum size an RMP can be (16 bytes/page mapped) */ + rmp_segment_size_max =3D PHYS_PFN(rmp_segment_coverage_size); + rmp_segment_size_max <<=3D 4; +} + #define RMP_ADDR_MASK GENMASK_ULL(51, 13) =20 bool snp_probe_rmptable_info(void) @@ -303,6 +437,11 @@ bool snp_probe_rmptable_info(void) =20 rmp_sz =3D rmp_end - rmp_base + 1; =20 + /* Treat the contiguous RMP table as a single segment */ + rst_max_index =3D 1; + + set_rmp_segment_info(RMPTABLE_NON_SEGMENTED_SHIFT); + probed_rmp_base =3D rmp_base; probed_rmp_size =3D rmp_sz; =20 @@ -314,13 +453,29 @@ bool snp_probe_rmptable_info(void) =20 static struct rmpentry *__get_rmpentry(u64 pfn) { - if (!rmptable) + struct rmp_segment_desc *desc; + u64 paddr, rst_index, segment_index; + + if (!rmp_segment_table) return ERR_PTR(-ENODEV); =20 - if (unlikely(pfn > rmptable_max_pfn)) + paddr =3D pfn << PAGE_SHIFT; + + rst_index =3D RST_ENTRY_INDEX(paddr); + if (unlikely(rst_index >=3D rst_max_index)) + return ERR_PTR(-EFAULT); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:43:04.8470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e272dca2-3916-4804-a73d-08dcf39287e0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6943 Content-Type: text/plain; charset="utf-8" A segmented RMP table allows for improved locality of reference between the memory protected by the RMP and the RMP entries themselves. Add support to detect and initialize a segmented RMP table with multiple segments as configured by the system BIOS. While the RMPREAD instruction will be used to read an RMP entry in a segmented RMP, initialization and debugging capabilities will require the mapping of the segments. The RMP_CFG MSR indicates if segmented RMP support is enabled and, if enabled, the amount of memory that an RMP segment covers. When segmented RMP support is enabled, the RMP_BASE MSR points to the start of the RMP bookkeeping area, which is 16K in size. The RMP Segment Table (RST) is located immediately after the bookkeeping area and is 4K in size. The RST contains up to 512 8-byte entries that identify the location of the RMP segment and amount of memory mapped by the segment (which must be less than or equal to the configured segment size). The physical address that is covered by a segment is based on the segment size and the index of the segment in the RST. The RMP entry for a physical address is based on the offset within the segment. For example, if the segment size is 64GB (0x1000000000 or 1 << 36), then physical address 0x9000800000 is RST entry 9 (0x9000800000 >> 36) and RST entry 9 covers physical memory 0x9000000000 to 0x9FFFFFFFFF. The RMP entry index within the RMP segment is the physical address AND-ed with the segment mask, 64GB - 1 (0xFFFFFFFFF), and then right-shifted 12 bits or PHYS_PFN(0x9000800000 & 0xFFFFFFFFF), which is 0x800. CPUID 0x80000025_EBX[9:0] describes the number of RMP segments that can be cached by the hardware. Additionally, if CPUID 0x80000025_EBX[10] is set, then the number of actual RMP segments defined cannot exceed the number of RMP segments that can be cached and can be used as a maximum RST index. Signed-off-by: Tom Lendacky Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 8 +- arch/x86/virt/svm/sev.c | 251 ++++++++++++++++++++++++++--- 3 files changed, 236 insertions(+), 24 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 89c1308cdf54..bf2485bbe184 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -449,6 +449,7 @@ #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache= coherency */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full= debug state swap support */ #define X86_FEATURE_RMPREAD (19*32+21) /* RMPREAD instruction */ +#define X86_FEATURE_SEGMENTED_RMP (19*32+23) /* Segmented RMP support */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ =20 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word = 20 */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 3ae84c3b8e6d..3f3e2bc99162 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -644,6 +644,7 @@ #define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ #define MSR_AMD64_SVM_AVIC_DOORBELL 0xc001011b #define MSR_AMD64_VM_PAGE_FLUSH 0xc001011e +#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f #define MSR_AMD64_SEV_ES_GHCB 0xc0010130 #define MSR_AMD64_SEV 0xc0010131 #define MSR_AMD64_SEV_ENABLED_BIT 0 @@ -682,11 +683,12 @@ #define MSR_AMD64_SNP_SMT_PROT BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT) #define MSR_AMD64_SNP_RESV_BIT 18 #define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT) - -#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f - #define MSR_AMD64_RMP_BASE 0xc0010132 #define MSR_AMD64_RMP_END 0xc0010133 +#define MSR_AMD64_RMP_CFG 0xc0010136 +#define MSR_AMD64_SEG_RMP_ENABLED_BIT 0 +#define MSR_AMD64_SEG_RMP_ENABLED BIT_ULL(MSR_AMD64_SEG_RMP_ENABLED_BIT) +#define MSR_AMD64_RMP_SEGMENT_SHIFT(x) (((x) & GENMASK_ULL(13, 8)) >> 8) =20 #define MSR_SVSM_CAA 0xc001f000 =20 diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c index 043b2582e10e..f4f801f1c328 100644 --- a/arch/x86/virt/svm/sev.c +++ b/arch/x86/virt/svm/sev.c @@ -97,6 +97,10 @@ struct rmp_segment_desc { * a specific portion of memory. There can be up to 512 8-byte entries, * one pages worth. */ +#define RST_ENTRY_MAPPED_SIZE(x) ((x) & GENMASK_ULL(19, 0)) +#define RST_ENTRY_SEGMENT_BASE(x) ((x) & GENMASK_ULL(51, 20)) + +#define RMP_SEGMENT_TABLE_SIZE SZ_4K static struct rmp_segment_desc **rmp_segment_table __ro_after_init; static unsigned int rst_max_index __ro_after_init =3D 512; =20 @@ -107,6 +111,9 @@ static u64 rmp_segment_coverage_mask; #define RST_ENTRY_INDEX(x) ((x) >> rmp_segment_coverage_shift) #define RMP_ENTRY_INDEX(x) ((u64)(PHYS_PFN((x) & rmp_segment_coverage_mask= ))) =20 +static u64 rmp_cfg; +#define RMP_IS_SEGMENTED(x) ((x) & MSR_AMD64_SEG_RMP_ENABLED) + /* Mask to apply to a PFN to get the first PFN of a 2MB page */ #define PFN_PMD_MASK GENMASK_ULL(63, PMD_SHIFT - PAGE_SHIFT) =20 @@ -196,7 +203,49 @@ static void __init __snp_fixup_e820_tables(u64 pa) void __init snp_fixup_e820_tables(void) { __snp_fixup_e820_tables(probed_rmp_base); - __snp_fixup_e820_tables(probed_rmp_base + probed_rmp_size); + + if (RMP_IS_SEGMENTED(rmp_cfg)) { + u64 pa, *rst, size, mapped_size; + unsigned int i; + + pa =3D probed_rmp_base; + pa +=3D RMPTABLE_CPU_BOOKKEEPING_SZ; + pa +=3D RMP_SEGMENT_TABLE_SIZE; + __snp_fixup_e820_tables(pa); + + pa -=3D RMP_SEGMENT_TABLE_SIZE; + rst =3D early_memremap(pa, RMP_SEGMENT_TABLE_SIZE); + if (!rst) + return; + + for (i =3D 0; i < rst_max_index; i++) { + pa =3D RST_ENTRY_SEGMENT_BASE(rst[i]); + mapped_size =3D RST_ENTRY_MAPPED_SIZE(rst[i]); + if (!mapped_size) + continue; + + __snp_fixup_e820_tables(pa); + + /* + * Mapped size in GB. Mapped size is allowed to exceed + * the segment coverage size, but gets reduced to the + * segment coverage size. + */ + mapped_size <<=3D 30; + if (mapped_size > rmp_segment_coverage_size) + mapped_size =3D rmp_segment_coverage_size; + + /* Calculate the RMP segment size (16 bytes/page mapped) */ + size =3D PHYS_PFN(mapped_size); + size <<=3D 4; + + __snp_fixup_e820_tables(pa + size); + } + + early_memunmap(rst, RMP_SEGMENT_TABLE_SIZE); + } else { + __snp_fixup_e820_tables(probed_rmp_base + probed_rmp_size); + } } =20 static bool __init init_rmptable_bookkeeping(void) @@ -302,29 +351,17 @@ static bool __init alloc_rmp_segment_table(void) return true; } =20 -/* - * Do the necessary preparations which are verified by the firmware as - * described in the SNP_INIT_EX firmware command description in the SNP - * firmware ABI spec. - */ -static int __init snp_rmptable_init(void) +static bool __init contiguous_rmptable_setup(void) { - u64 max_rmp_pfn, calc_rmp_sz, rmptable_segment, rmptable_size, rmp_end, v= al; - unsigned int i; - - if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) - return 0; - - if (!amd_iommu_snp_en) - goto nosnp; + u64 max_rmp_pfn, calc_rmp_sz, rmptable_segment, rmptable_size, rmp_end; =20 if (!probed_rmp_size) - goto nosnp; + return false; =20 rmp_end =3D probed_rmp_base + probed_rmp_size - 1; =20 /* - * Calculate the amount the memory that must be reserved by the BIOS to + * Calculate the amount of memory that must be reserved by the BIOS to * address the whole RAM, including the bookkeeping area. The RMP itself * must also be covered. */ @@ -336,11 +373,11 @@ static int __init snp_rmptable_init(void) if (calc_rmp_sz > probed_rmp_size) { pr_err("Memory reserved for the RMP table does not cover full system RAM= (expected 0x%llx got 0x%llx)\n", calc_rmp_sz, probed_rmp_size); - goto nosnp; + return false; } =20 if (!alloc_rmp_segment_table()) - goto nosnp; + return false; =20 /* Map only the RMP entries */ rmptable_segment =3D probed_rmp_base + RMPTABLE_CPU_BOOKKEEPING_SZ; @@ -348,9 +385,127 @@ static int __init snp_rmptable_init(void) =20 if (!alloc_rmp_segment_desc(rmptable_segment, rmptable_size, 0)) { free_rmp_segment_table(); - goto nosnp; + return false; } =20 + return true; +} + +static bool __init segmented_rmptable_setup(void) +{ + u64 rst_pa, *rst, pa, ram_pa_end, ram_pa_max; + unsigned int i, max_index; + + if (!probed_rmp_base) + return false; + + if (!alloc_rmp_segment_table()) + return false; + + /* Map the RMP Segment Table */ + rst_pa =3D probed_rmp_base + RMPTABLE_CPU_BOOKKEEPING_SZ; + rst =3D memremap(rst_pa, RMP_SEGMENT_TABLE_SIZE, MEMREMAP_WB); + if (!rst) { + pr_err("Failed to map RMP segment table addr %#llx\n", rst_pa); + goto e_free; + } + + /* Get the address for the end of system RAM */ + ram_pa_max =3D max_pfn << PAGE_SHIFT; + + /* Process each RMP segment */ + max_index =3D 0; + ram_pa_end =3D 0; + for (i =3D 0; i < rst_max_index; i++) { + u64 rmp_segment, rmp_size, mapped_size; + + mapped_size =3D RST_ENTRY_MAPPED_SIZE(rst[i]); + if (!mapped_size) + continue; + + max_index =3D i; + + /* + * Mapped size in GB. Mapped size is allowed to exceed the + * segment coverage size, but gets reduced to the segment + * coverage size. + */ + mapped_size <<=3D 30; + if (mapped_size > rmp_segment_coverage_size) { + pr_info("RMP segment %u mapped size (0x%llx) reduced to 0x%llx\n", + i, mapped_size, rmp_segment_coverage_size); + mapped_size =3D rmp_segment_coverage_size; + } + + rmp_segment =3D RST_ENTRY_SEGMENT_BASE(rst[i]); + + /* Calculate the RMP segment size (16 bytes/page mapped) */ + rmp_size =3D PHYS_PFN(mapped_size); + rmp_size <<=3D 4; + + pa =3D (u64)i << rmp_segment_coverage_shift; + + /* + * Some segments may be for MMIO mapped above system RAM. These + * segments are used for Trusted I/O. + */ + if (pa < ram_pa_max) + ram_pa_end =3D pa + mapped_size; + + if (!alloc_rmp_segment_desc(rmp_segment, rmp_size, pa)) + goto e_unmap; + + pr_info("RMP segment %u physical address [%#llx - %#llx] covering [%#llx= - %#llx]\n", + i, rmp_segment, rmp_segment + rmp_size - 1, pa, pa + mapped_size - 1); + } + + if (ram_pa_max > ram_pa_end) { + pr_err("Segmented RMP does not cover full system RAM (expected 0x%llx go= t 0x%llx)\n", + ram_pa_max, ram_pa_end); + goto e_unmap; + } + + /* Adjust the maximum index based on the found segments */ + rst_max_index =3D max_index + 1; + + memunmap(rst); + + return true; + +e_unmap: + memunmap(rst); + +e_free: + free_rmp_segment_table(); + + return false; +} + +static bool __init rmptable_setup(void) +{ + return RMP_IS_SEGMENTED(rmp_cfg) ? segmented_rmptable_setup() + : contiguous_rmptable_setup(); +} + +/* + * Do the necessary preparations which are verified by the firmware as + * described in the SNP_INIT_EX firmware command description in the SNP + * firmware ABI spec. + */ +static int __init snp_rmptable_init(void) +{ + unsigned int i; + u64 val; + + if (!cc_platform_has(CC_ATTR_HOST_SEV_SNP)) + return 0; + + if (!amd_iommu_snp_en) + goto nosnp; + + if (!rmptable_setup()) + goto nosnp; + /* * Check if SEV-SNP is already enabled, this can happen in case of * kexec boot. @@ -418,7 +573,7 @@ static void set_rmp_segment_info(unsigned int segment_s= hift) =20 #define RMP_ADDR_MASK GENMASK_ULL(51, 13) =20 -bool snp_probe_rmptable_info(void) +static bool probe_contiguous_rmptable_info(void) { u64 rmp_sz, rmp_base, rmp_end; =20 @@ -451,6 +606,60 @@ bool snp_probe_rmptable_info(void) return true; } =20 +static bool probe_segmented_rmptable_info(void) +{ + unsigned int eax, ebx, segment_shift, segment_shift_min, segment_shift_ma= x; + u64 rmp_base, rmp_end; + + rdmsrl(MSR_AMD64_RMP_BASE, rmp_base); + rdmsrl(MSR_AMD64_RMP_END, rmp_end); + + if (!(rmp_base & RMP_ADDR_MASK)) { + pr_err("Memory for the RMP table has not been reserved by BIOS\n"); + return false; + } + + WARN_ONCE(rmp_end & RMP_ADDR_MASK, + "Segmented RMP enabled but RMP_END MSR is non-zero\n"); + + /* Obtain the min and max supported RMP segment size */ + eax =3D cpuid_eax(0x80000025); + segment_shift_min =3D eax & GENMASK(5, 0); + segment_shift_max =3D (eax & GENMASK(11, 6)) >> 6; + + /* Verify the segment size is within the supported limits */ + segment_shift =3D MSR_AMD64_RMP_SEGMENT_SHIFT(rmp_cfg); + if (segment_shift > segment_shift_max || segment_shift < segment_shift_mi= n) { + pr_err("RMP segment size (%u) is not within advertised bounds (min=3D%u,= max=3D%u)\n", + segment_shift, segment_shift_min, segment_shift_max); + return false; + } + + /* Override the max supported RST index if a hardware limit exists */ + ebx =3D cpuid_ebx(0x80000025); + if (ebx & BIT(10)) + rst_max_index =3D ebx & GENMASK(9, 0); + + set_rmp_segment_info(segment_shift); + + probed_rmp_base =3D rmp_base; + probed_rmp_size =3D 0; + + pr_info("Segmented RMP base table physical range [0x%016llx - 0x%016llx]\= n", + rmp_base, rmp_base + RMPTABLE_CPU_BOOKKEEPING_SZ + RMP_SEGMENT_TABLE_SIZ= E); + + return true; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2024 18:43:12.1369 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9977ebac-fb24-43af-61fa-08dcf3928c3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE36.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7603 Content-Type: text/plain; charset="utf-8" Update the AMD memory encryption documentation to include information on the Reverse Map Table (RMP) and the two table formats. Signed-off-by: Tom Lendacky Reviewed-by: Neeraj Upadhyay Reviewed-by: Nikunj A Dadhania --- .../arch/x86/amd-memory-encryption.rst | 118 ++++++++++++++++++ 1 file changed, 118 insertions(+) diff --git a/Documentation/arch/x86/amd-memory-encryption.rst b/Documentati= on/arch/x86/amd-memory-encryption.rst index 6df3264f23b9..bd840df708ea 100644 --- a/Documentation/arch/x86/amd-memory-encryption.rst +++ b/Documentation/arch/x86/amd-memory-encryption.rst @@ -130,8 +130,126 @@ SNP feature support. =20 More details in AMD64 APM[1] Vol 2: 15.34.10 SEV_STATUS MSR =20 +Reverse Map Table (RMP) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The RMP is a structure in system memory that is used to ensure a one-to-one +mapping between system physical addresses and guest physical addresses. Ea= ch +page of memory that is potentially assignable to guests has one entry with= in +the RMP. + +The RMP table can be either contiguous in memory or a collection of segmen= ts +in memory. + +Contiguous RMP +-------------- + +Support for this form of the RMP is present when support for SEV-SNP is +present, which can be determined using the CPUID instruction:: + + 0x8000001f[eax]: + Bit[4] indicates support for SEV-SNP + +The location of the RMP is identified to the hardware through two MSRs:: + + 0xc0010132 (RMP_BASE): + System physical address of the first byte of the RMP + + 0xc0010133 (RMP_END): + System physical address of the last byte of the RMP + +Hardware requires that RMP_BASE and (RPM_END + 1) be 8KB aligned, but SEV +firmware increases the alignment requirement to require a 1MB alignment. + +The RMP consists of a 16KB region used for processor bookkeeping followed +by the RMP entries, which are 16 bytes in size. The size of the RMP +determines the range of physical memory that the hypervisor can assign to +SEV-SNP guests. The RMP covers the system physical address from:: + + 0 to ((RMP_END + 1 - RMP_BASE - 16KB) / 16B) x 4KB. + +The current Linux support relies on BIOS to allocate/reserve the memory for +the RMP and to set RMP_BASE and RMP_END appropriately. Linux uses the MSR +values to locate the RMP and determine the size of the RMP. The RMP must +cover all of system memory in order for Linux to enable SEV-SNP. + +Segmented RMP +------------- + +Segmented RMP support is a new way of representing the layout of an RMP. +Initial RMP support required the RMP table to be contiguous in memory. +RMP accesses from a NUMA node on which the RMP doesn't reside +can take longer than accesses from a NUMA node on which the RMP resides. +Segmented RMP support allows the RMP entries to be located on the same +node as the memory the RMP is covering, potentially reducing latency +associated with accessing an RMP entry associated with the memory. Each +RMP segment covers a specific range of system physical addresses. + +Support for this form of the RMP can be determined using the CPUID +instruction:: + + 0x8000001f[eax]: + Bit[23] indicates support for segmented RMP + +If supported, segmented RMP attributes can be found using the CPUID +instruction:: + + 0x80000025[eax]: + Bits[5:0] minimum supported RMP segment size + Bits[11:6] maximum supported RMP segment size + + 0x80000025[ebx]: + Bits[9:0] number of cacheable RMP segment definitions + Bit[10] indicates if the number of cacheable RMP segmen= ts + is a hard limit + +To enable a segmented RMP, a new MSR is available:: + + 0xc0010136 (RMP_CFG): + Bit[0] indicates if segmented RMP is enabled + Bits[13:8] contains the size of memory covered by an RMP + segment (expressed as a power of 2) + +The RMP segment size defined in the RMP_CFG MSR applies to all segments +of the RMP. Therefore each RMP segment covers a specific range of system +physical addresses. For example, if the RMP_CFG MSR value is 0x2401, then +the RMP segment coverage value is 0x24 =3D> 36, meaning the size of memory +covered by an RMP segment is 64GB (1 << 36). So the first RMP segment +covers physical addresses from 0 to 0xF_FFFF_FFFF, the second RMP segment +covers physical addresses from 0x10_0000_0000 to 0x1F_FFFF_FFFF, etc. + +When a segmented RMP is enabled, RMP_BASE points to the RMP bookkeeping +area as it does today (16K in size). However, instead of RMP entries +beginning immediately after the bookkeeping area, there is a 4K RMP +segment table (RST). Each entry in the RST is 8-bytes in size and represen= ts +an RMP segment:: + + Bits[19:0] mapped size (in GB) + The mapped size can be less than the defined segment s= ize. + A value of zero, indicates that no RMP exists for the = range + of system physical addresses associated with this segm= ent. + Bits[51:20] segment physical address + This address is left shift 20-bits (or just masked when + read) to form the physical address of the segment (1MB + alignment). + +The RST can hold 512 segment entries but can be limited in size to the num= ber +of cacheable RMP segments (CPUID 0x80000025_EBX[9:0]) if the number of cac= heable +RMP segments is a hard limit (CPUID 0x80000025_EBX[10]). + +The current Linux support relies on BIOS to allocate/reserve the memory for +the segmented RMP (the bookkeeping area, RST, and all segments), build the= RST +and to set RMP_BASE, RMP_END, and RMP_CFG appropriately. Linux uses the MSR +values to locate the RMP and determine the size and location of the RMP +segments. The RMP must cover all of system memory in order for Linux to en= able +SEV-SNP. + +More details in the AMD64 APM Vol 2, section "15.36.3 Reverse Map Table", +docID: 24593. + Secure VM Service Module (SVSM) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D + SNP provides a feature called Virtual Machine Privilege Levels (VMPL) which defines four privilege levels at which guest software can run. The most privileged level is 0 and numerically higher numbers have lesser privilege= s. --=20 2.46.2