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charset="utf-8" From: Chen Wang Sophgo SG2042 contains a PWM controller, which has 4 channels and can generate PWM waveforms output. Signed-off-by: Chen Wang Reviewed-by: Krzysztof Kozlowski --- .../bindings/pwm/sophgo,sg2042-pwm.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm= .yaml diff --git a/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml b= /Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml new file mode 100644 index 000000000000..fe89719ed9dd --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/sophgo,sg2042-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PWM controller + +maintainers: + - Chen Wang + +description: + This controller contains 4 channels which can generate PWM waveforms. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,sg2042-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + pwm@7f006000 { + compatible =3D "sophgo,sg2042-pwm"; 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charset="utf-8" From: Chen Wang Add a PWM driver for PWM controller in Sophgo SG2042 SoC. Signed-off-by: Chen Wang --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sophgo-sg2042.c | 180 ++++++++++++++++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 drivers/pwm/pwm-sophgo-sg2042.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0915c1e7df16..ec85f3895936 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -584,6 +584,16 @@ config PWM_SL28CPLD To compile this driver as a module, choose M here: the module will be called pwm-sl28cpld. =20 +config PWM_SOPHGO_SG2042 + tristate "Sophgo SG2042 PWM support" + depends on ARCH_SOPHGO || COMPILE_TEST + help + PWM driver for the PWM controller on Sophgo SG2042 SoC. The PWM + controller supports outputing 4 channels of PWM waveforms. + + To compile this driver as a module, choose M here: the module + will be called pwm_sophgo_sg2042. + config PWM_SPEAR tristate "STMicroelectronics SPEAr PWM support" depends on PLAT_SPEAR || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9081e0c0e9e0..539e0def3f82 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_PWM_RZ_MTU3) +=3D pwm-rz-mtu3.o obj-$(CONFIG_PWM_SAMSUNG) +=3D pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) +=3D pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) +=3D pwm-sl28cpld.o +obj-$(CONFIG_PWM_SOPHGO_SG2042) +=3D pwm-sophgo-sg2042.o obj-$(CONFIG_PWM_SPEAR) +=3D pwm-spear.o obj-$(CONFIG_PWM_SPRD) +=3D pwm-sprd.o obj-$(CONFIG_PWM_STI) +=3D pwm-sti.o diff --git a/drivers/pwm/pwm-sophgo-sg2042.c b/drivers/pwm/pwm-sophgo-sg204= 2.c new file mode 100644 index 000000000000..198019b751ad --- /dev/null +++ b/drivers/pwm/pwm-sophgo-sg2042.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sophgo SG2042 PWM Controller Driver + * + * Copyright (C) 2024 Sophgo Technology Inc. + * Copyright (C) 2024 Chen Wang + * + * Limitations: + * - After reset, the output of the PWM channel is always high. + * The value of HLPERIOD/PERIOD is 0. + * - When HLPERIOD or PERIOD is reconfigured, PWM will start to + * output waveforms with the new configuration after completing + * the running period. + * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will + * be stopped and the output is pulled to high. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * Offset RegisterName + * 0x0000 HLPERIOD0 + * 0x0004 PERIOD0 + * 0x0008 HLPERIOD1 + * 0x000C PERIOD1 + * 0x0010 HLPERIOD2 + * 0x0014 PERIOD2 + * 0x0018 HLPERIOD3 + * 0x001C PERIOD3 + * Four groups and every group is composed of HLPERIOD & PERIOD + */ +#define SG2042_HLPERIOD(chan) ((chan) * 8 + 0) +#define SG2042_PERIOD(chan) ((chan) * 8 + 4) + +#define SG2042_PWM_CHANNELNUM 4 + +/** + * struct sg2042_pwm_ddata - private driver data + * @base: base address of mapped PWM registers + * @clk_rate_hz: rate of base clock in HZ + */ +struct sg2042_pwm_ddata { + void __iomem *base; + unsigned long clk_rate_hz; +}; + +static void pwm_sg2042_config(void __iomem *base, unsigned int chan, u32 p= eriod, u32 hlperiod) +{ + writel(period, base + SG2042_PERIOD(chan)); + writel(hlperiod, base + SG2042_HLPERIOD(chan)); +} + +static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata =3D pwmchip_get_drvdata(chip); + u32 hlperiod; + u32 period; + + if (state->polarity =3D=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + if (!state->enabled) { + pwm_sg2042_config(ddata->base, pwm->hwpwm, 0, 0); + return 0; + } + + /* + * Period of High level (duty_cycle) =3D HLPERIOD x Period_clk + * Period of One Cycle (period) =3D PERIOD x Period_clk + */ + period =3D min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSE= C_PER_SEC), U32_MAX); + hlperiod =3D min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->duty_cycl= e, NSEC_PER_SEC), U32_MAX); + + if (hlperiod > period) { + dev_err(pwmchip_parent(chip), "period < hlperiod, failed to apply curren= t setting\n"); + return -EINVAL; + } + + dev_dbg(pwmchip_parent(chip), "chan[%u]: period=3D%u, hlperiod=3D%u\n", + pwm->hwpwm, period, hlperiod); + + pwm_sg2042_config(ddata->base, pwm->hwpwm, period, hlperiod); + + return 0; +} + +static int pwm_sg2042_get_state(struct pwm_chip *chip, struct pwm_device *= pwm, + struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata =3D pwmchip_get_drvdata(chip); + unsigned int chan =3D pwm->hwpwm; + u32 hlperiod; + u32 period; + + period =3D readl(ddata->base + SG2042_PERIOD(chan)); + hlperiod =3D readl(ddata->base + SG2042_HLPERIOD(chan)); + + if (!period && !hlperiod) + state->enabled =3D false; + else + state->enabled =3D true; + + state->period =3D DIV_ROUND_UP_ULL((u64)period * NSEC_PER_SEC, ddata->clk= _rate_hz); + state->duty_cycle =3D DIV_ROUND_UP_ULL((u64)hlperiod * NSEC_PER_SEC, ddat= a->clk_rate_hz); + + state->polarity =3D PWM_POLARITY_NORMAL; + + return 0; +} + +static const struct pwm_ops pwm_sg2042_ops =3D { + .apply =3D pwm_sg2042_apply, + .get_state =3D pwm_sg2042_get_state, +}; + +static const struct of_device_id sg2042_pwm_ids[] =3D { + { .compatible =3D "sophgo,sg2042-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, sg2042_pwm_ids); + +static int pwm_sg2042_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sg2042_pwm_ddata *ddata; + struct pwm_chip *chip; + struct clk *clk; + int ret; + + chip =3D devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + ddata =3D pwmchip_get_drvdata(chip); + + ddata->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->base)) + return PTR_ERR(ddata->base); + + clk =3D devm_clk_get_enabled(dev, "apb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to get base clk\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, "failed to get exclusive rate\n"); + + ddata->clk_rate_hz =3D clk_get_rate(clk); + if (!ddata->clk_rate_hz || ddata->clk_rate_hz > NSEC_PER_SEC) + return dev_err_probe(dev, -EINVAL, + "Invalid clock rate: %lu\n", ddata->clk_rate_hz); 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Mon, 07 Oct 2024 20:04:41 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3e3cf854961sm1282089b6e.10.2024.10.07.20.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2024 20:04:40 -0700 (PDT) From: Chen Wang To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, chunzhi.lin@sophgo.com Subject: [PATCH v3 3/3] riscv: sophgo: dts: add pwm controller for SG2042 SoC Date: Tue, 8 Oct 2024 11:04:33 +0800 Message-Id: <960826e94a94c1c0a25261e4081de7fa82dff5f5.1728355974.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang SG2042 has one PWM controller, which has 4 pwm output channels. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index 4e5fa6591623..048792b30617 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -165,6 +165,14 @@ port2a: gpio-controller@0 { }; }; =20 + pwm: pwm@703000c000 { + compatible =3D "sophgo,sg2042-pwm"; + reg =3D <0x70 0x3000c000 0x0 0x20>; + #pwm-cells =3D <2>; + clocks =3D <&clkgen GATE_CLK_APB_PWM>; + clock-names =3D "apb"; + }; + pllclk: clock-controller@70300100c0 { compatible =3D "sophgo,sg2042-pll"; reg =3D <0x70 0x300100c0 0x0 0x40>; --=20 2.34.1