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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 06:04:15.2508 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 053a64e3-318c-4101-bba9-08dcd15e665e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9120 Content-Type: text/plain; charset="utf-8" Restricted injection is a feature which enforces additional interrupt and e= vent injection security protections for a SEV-SNP guest. It disables all hypervisor-based interrupt queuing and event injection of all vectors except a new exception vector, #HV (28), which is reserved for SNP guest use, but never generated by hardware. #HV is only allowed to be injected into VMSAs = that execute with Restricted Injection. The guests running with the SNP restricted injection feature active limit t= he host to ringing a doorbell with a #HV exception. Define two fields in the #HV doorbell page: a pending event field, and an EOI assist. Create the structure definition for the #HV doorbell page as per GHCB specification. Co-developed-by: Thomas Lendacky Signed-off-by: Thomas Lendacky Signed-off-by: Melody Wang --- arch/x86/include/asm/svm.h | 41 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index f0dea3750ca9..2b1f4c8daf19 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -516,6 +516,47 @@ struct ghcb { u32 ghcb_usage; } __packed; =20 +/* + * Hypervisor doorbell page: + * + * Used when restricted injection is enabled for a VM. One page in size th= at + * is shared between the guest and hypervisor to communicate exception and + * interrupt events. + */ +struct hvdb_events { + /* First 64 bytes of HV doorbell page defined in GHCB specification */ + union { + struct { + /* Interrupt vector being injected */ + u8 vector; + + /* Non-maskable event field (NMI, etc.) */ + u8 nm_events; + }; + + struct { + /* Non-maskable event indicators */ + u16 reserved1: 8, + nmi: 1, + mce: 1, + reserved2: 5, + no_further_signal: 1; + }; + + u16 pending_events; + }; + + u8 no_eoi_required; + + u8 reserved3[61]; +}; + +struct hvdb { + struct hvdb_events events; + + /* Remainder of the page is for software use */ + u8 reserved[PAGE_SIZE - sizeof(struct hvdb_events)]; +}; =20 #define EXPECTED_VMCB_SAVE_AREA_SIZE 744 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032 --=20 2.34.1 From nobody Sat Nov 30 10:51:03 2024 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2073.outbound.protection.outlook.com [40.107.96.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95DFF166F00; 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Tue, 10 Sep 2024 01:04:33 -0500 From: Melody Wang To: , , CC: Sean Christopherson , Paolo Bonzini , Tom Lendacky , Ashish Kalra , Michael Roth , Melody Wang Subject: [PATCH v2 2/6] KVM: SVM: Add support for the SEV-SNP #HV doorbell page NAE event Date: Tue, 10 Sep 2024 06:03:32 +0000 Message-ID: <7a04e3f07965a09d79bbcc067ed943ea0a4c7b7c.1725945912.git.huibo.wang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F3:EE_|SJ2PR12MB8134:EE_ X-MS-Office365-Filtering-Correlation-Id: 89b76146-8f53-4e75-bf2a-08dcd15e7217 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 06:04:34.9338 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89b76146-8f53-4e75-bf2a-08dcd15e7217 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8134 Content-Type: text/plain; charset="utf-8" To support the SEV-SNP Restricted Injection feature, the SEV-SNP guest must register a #HV doorbell page for use with the #HV. The #HV doorbell page NAE event allows the guest to register a #HV doorbell page. The NAE event consists of four actions: GET_PREFERRED, SET, QUERY, CL= EAR. Implement the NAE event as per GHCB specification. Co-developed-by: Thomas Lendacky Signed-off-by: Thomas Lendacky Signed-off-by: Melody Wang --- arch/x86/include/uapi/asm/svm.h | 5 +++ arch/x86/kvm/svm/sev.c | 73 +++++++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 2 + 3 files changed, 80 insertions(+) diff --git a/arch/x86/include/uapi/asm/svm.h b/arch/x86/include/uapi/asm/sv= m.h index 1814b413fd57..7905c9be44d1 100644 --- a/arch/x86/include/uapi/asm/svm.h +++ b/arch/x86/include/uapi/asm/svm.h @@ -115,6 +115,11 @@ #define SVM_VMGEXIT_AP_CREATE_ON_INIT 0 #define SVM_VMGEXIT_AP_CREATE 1 #define SVM_VMGEXIT_AP_DESTROY 2 +#define SVM_VMGEXIT_HVDB_PAGE 0x80000014 +#define SVM_VMGEXIT_HVDB_GET_PREFERRED 0 +#define SVM_VMGEXIT_HVDB_SET 1 +#define SVM_VMGEXIT_HVDB_QUERY 2 +#define SVM_VMGEXIT_HVDB_CLEAR 3 #define SVM_VMGEXIT_SNP_RUN_VMPL 0x80000018 #define SVM_VMGEXIT_HV_FEATURES 0x8000fffd #define SVM_VMGEXIT_TERM_REQUEST 0x8000fffe diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 714c517dd4b7..e65867ea768d 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3410,6 +3410,10 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *= svm) control->exit_info_1 =3D=3D control->exit_info_2) goto vmgexit_err; break; + case SVM_VMGEXIT_HVDB_PAGE: + if (!sev_snp_guest(vcpu->kvm)) + goto vmgexit_err; + break; default: reason =3D GHCB_ERR_INVALID_EVENT; goto vmgexit_err; @@ -4125,6 +4129,66 @@ static int snp_handle_ext_guest_req(struct vcpu_svm = *svm, gpa_t req_gpa, gpa_t r return 1; /* resume guest */ } =20 +static int sev_snp_hv_doorbell_page(struct vcpu_svm *svm) +{ + struct kvm_vcpu *vcpu =3D &svm->vcpu; + struct kvm_host_map hvdb_map; + gpa_t hvdb_gpa; + u64 request; + + if (!sev_snp_guest(vcpu->kvm)) + return -EINVAL; + + request =3D svm->vmcb->control.exit_info_1; + hvdb_gpa =3D svm->vmcb->control.exit_info_2; + + switch (request) { + case SVM_VMGEXIT_HVDB_GET_PREFERRED: + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, ~0ULL); + break; + case SVM_VMGEXIT_HVDB_SET: + svm->sev_es.hvdb_gpa =3D INVALID_PAGE; + + if (!PAGE_ALIGNED(hvdb_gpa)) { + vcpu_unimpl(vcpu, "vmgexit: unaligned #HV doorbell page address [%#llx]= from guest\n", + hvdb_gpa); + return -EINVAL; + } + + if (!page_address_valid(vcpu, hvdb_gpa)) { + vcpu_unimpl(vcpu, "vmgexit: invalid #HV doorbell page address [%#llx] f= rom guest\n", + hvdb_gpa); + return -EINVAL; + } + + /* Map and unmap the GPA just to be sure the GPA is valid */ + if (kvm_vcpu_map(vcpu, gpa_to_gfn(hvdb_gpa), &hvdb_map)) { + /* Unable to map #HV doorbell page from guest */ + vcpu_unimpl(vcpu, "vmgexit: error mapping #HV doorbell page [%#llx] fro= m guest\n", + hvdb_gpa); + return -EINVAL; + } + kvm_vcpu_unmap(vcpu, &hvdb_map, true); + + svm->sev_es.hvdb_gpa =3D hvdb_gpa; + fallthrough; + case SVM_VMGEXIT_HVDB_QUERY: + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, svm->sev_es.hvdb_gpa); + break; + case SVM_VMGEXIT_HVDB_CLEAR: + svm->sev_es.hvdb_gpa =3D INVALID_PAGE; + break; + default: + svm->sev_es.hvdb_gpa =3D INVALID_PAGE; + + vcpu_unimpl(vcpu, "vmgexit: invalid #HV doorbell page request [%#llx] fr= om guest\n", + request); + return -EINVAL; + } + + return 0; +} + static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) { struct vmcb_control_area *control =3D &svm->vmcb->control; @@ -4405,6 +4469,14 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) case SVM_VMGEXIT_EXT_GUEST_REQUEST: ret =3D snp_handle_ext_guest_req(svm, control->exit_info_1, control->exi= t_info_2); break; + case SVM_VMGEXIT_HVDB_PAGE: + if (sev_snp_hv_doorbell_page(svm)) { + ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 2); + ghcb_set_sw_exit_info_2(svm->sev_es.ghcb, GHCB_ERR_INVALID_INPUT); + } + + ret =3D 1; + break; case SVM_VMGEXIT_UNSUPPORTED_EVENT: vcpu_unimpl(vcpu, "vmgexit: unsupported event - exit_info_1=3D%#llx, exit_info_2=3D%#= llx\n", @@ -4572,6 +4644,7 @@ void sev_es_vcpu_reset(struct vcpu_svm *svm) sev_enc_bit)); =20 mutex_init(&svm->sev_es.snp_vmsa_mutex); + svm->sev_es.hvdb_gpa =3D INVALID_PAGE; } =20 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_sa= ve_area *hostsa) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 76107c7d0595..f0f14801e122 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -225,6 +225,8 @@ struct vcpu_sev_es_state { gpa_t snp_vmsa_gpa; bool snp_ap_waiting_for_reset; bool snp_has_guest_vmsa; + + gpa_t hvdb_gpa; }; =20 struct vcpu_svm { --=20 2.34.1 From nobody Sat Nov 30 10:51:03 2024 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF8AF16F27F; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 06:04:59.3758 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd37f508-6bfc-44d3-4cd3-08dcd15e80a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6080 Content-Type: text/plain; charset="utf-8" When restricted injection is active, only #HV exceptions can be injected in= to the SEV-SNP guest. Detect that restricted injection feature is active for the guest, and then follow the #HV doorbell communication from the GHCB specification to inject= the interrupt or exception. Co-developed-by: Thomas Lendacky Signed-off-by: Thomas Lendacky Signed-off-by: Melody Wang --- arch/x86/include/uapi/asm/kvm.h | 1 + arch/x86/kvm/svm/sev.c | 153 ++++++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 19 +++- arch/x86/kvm/svm/svm.h | 21 ++++- 4 files changed, 190 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/uapi/asm/kvm.h b/arch/x86/include/uapi/asm/kv= m.h index bf57a824f722..f5d85174e658 100644 --- a/arch/x86/include/uapi/asm/kvm.h +++ b/arch/x86/include/uapi/asm/kvm.h @@ -35,6 +35,7 @@ #define MC_VECTOR 18 #define XM_VECTOR 19 #define VE_VECTOR 20 +#define HV_VECTOR 28 =20 /* Select x86 specific features in */ #define __KVM_HAVE_PIT diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index e65867ea768d..f7623fa64307 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -5023,3 +5023,156 @@ int sev_private_max_mapping_level(struct kvm *kvm, = kvm_pfn_t pfn) =20 return level; } + +static void prepare_hv_injection(struct vcpu_svm *svm, struct hvdb *hvdb) +{ + if (hvdb->events.no_further_signal) + return; + + svm->vmcb->control.event_inj =3D HV_VECTOR | + SVM_EVTINJ_TYPE_EXEPT | + SVM_EVTINJ_VALID; + svm->vmcb->control.event_inj_err =3D 0; + + hvdb->events.no_further_signal =3D 1; +} + +static void unmap_hvdb(struct kvm_vcpu *vcpu, struct kvm_host_map *map) +{ + kvm_vcpu_unmap(vcpu, map, true); +} + +static struct hvdb *map_hvdb(struct kvm_vcpu *vcpu, struct kvm_host_map *m= ap) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + + if (!VALID_PAGE(svm->sev_es.hvdb_gpa)) + return NULL; + + if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->sev_es.hvdb_gpa), map)) { + /* Unable to map #HV doorbell page from guest */ + vcpu_unimpl(vcpu, "snp: error mapping #HV doorbell page [%#llx] from gue= st\n", + svm->sev_es.hvdb_gpa); + + return NULL; + } + + return map->hva; +} + +static bool __sev_snp_inject(enum inject_type type, struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + struct kvm_host_map hvdb_map; + struct hvdb *hvdb; + + hvdb =3D map_hvdb(vcpu, &hvdb_map); + if (!hvdb) + return false; + + hvdb->events.vector =3D vcpu->arch.interrupt.nr; + + prepare_hv_injection(svm, hvdb); + + unmap_hvdb(vcpu, &hvdb_map); + + return true; +} + +bool sev_snp_queue_exception(struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + + if (!sev_snp_is_rinj_active(vcpu)) + return false; + + /* + * Restricted injection is enabled, only #HV is supported. + * If the vector is not HV_VECTOR, do not inject the exception, + * then return true to skip the original injection path. + */ + if (WARN_ONCE(vcpu->arch.exception.vector !=3D HV_VECTOR, + "restricted injection enabled, exception %u injection not supporte= d\n", + vcpu->arch.exception.vector)) + return true; + + /* + * An intercept likely occurred during #HV delivery, so re-inject it + * using the current HVDB pending event values. + */ + svm->vmcb->control.event_inj =3D HV_VECTOR | + SVM_EVTINJ_TYPE_EXEPT | + SVM_EVTINJ_VALID; + svm->vmcb->control.event_inj_err =3D 0; + + return true; +} + +bool sev_snp_inject(enum inject_type type, struct kvm_vcpu *vcpu) +{ + if (!sev_snp_is_rinj_active(vcpu)) + return false; + + return __sev_snp_inject(type, vcpu); +} + +void sev_snp_cancel_injection(struct kvm_vcpu *vcpu) +{ + struct vcpu_svm *svm =3D to_svm(vcpu); + struct kvm_host_map hvdb_map; + struct hvdb *hvdb; + + if (!sev_snp_is_rinj_active(vcpu)) + return; + + if (!svm->vmcb->control.event_inj) + return; + + if ((svm->vmcb->control.event_inj & SVM_EVTINJ_VEC_MASK) !=3D HV_VECTOR) + return; + + /* + * Copy the information in the doorbell page into the event injection + * fields to complete the cancellation flow. + */ + hvdb =3D map_hvdb(vcpu, &hvdb_map); + if (!hvdb) + return; + + if (!hvdb->events.pending_events) { + /* No pending events, then event_inj field should be 0 */ + WARN_ON_ONCE(svm->vmcb->control.event_inj); + goto out; + } + + /* Copy info back into event_inj field (replaces #HV) */ + svm->vmcb->control.event_inj =3D SVM_EVTINJ_VALID; + + if (hvdb->events.vector) + svm->vmcb->control.event_inj |=3D hvdb->events.vector | + SVM_EVTINJ_TYPE_INTR; + + hvdb->events.pending_events =3D 0; + +out: + unmap_hvdb(vcpu, &hvdb_map); +} + +bool sev_snp_blocked(enum inject_type type, struct kvm_vcpu *vcpu) +{ + struct kvm_host_map hvdb_map; + struct hvdb *hvdb; + bool blocked; + + /* Indicate interrupts are blocked if doorbell page can't be mapped */ + hvdb =3D map_hvdb(vcpu, &hvdb_map); + if (!hvdb) + return true; + + /* Indicate interrupts blocked based on guest acknowledgment */ + blocked =3D !!hvdb->events.vector; + + unmap_hvdb(vcpu, &hvdb_map); + + return blocked; +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d6f252555ab3..a48388d99c97 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -447,6 +447,9 @@ static int svm_update_soft_interrupt_rip(struct kvm_vcp= u *vcpu) svm->soft_int_old_rip =3D old_rip; svm->soft_int_next_rip =3D rip; =20 + if (sev_snp_queue_exception(vcpu)) + return 0; + if (nrips) kvm_rip_write(vcpu, old_rip); =20 @@ -467,6 +470,9 @@ static void svm_inject_exception(struct kvm_vcpu *vcpu) svm_update_soft_interrupt_rip(vcpu)) return; =20 + if (sev_snp_queue_exception(vcpu)) + return; + svm->vmcb->control.event_inj =3D ex->vector | SVM_EVTINJ_VALID | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0) @@ -3662,10 +3668,12 @@ static void svm_inject_irq(struct kvm_vcpu *vcpu, b= ool reinjected) =20 trace_kvm_inj_virq(vcpu->arch.interrupt.nr, vcpu->arch.interrupt.soft, reinjected); - ++vcpu->stat.irq_injections; =20 - svm->vmcb->control.event_inj =3D vcpu->arch.interrupt.nr | - SVM_EVTINJ_VALID | type; + if (!sev_snp_inject(INJECT_IRQ, vcpu)) + svm->vmcb->control.event_inj =3D vcpu->arch.interrupt.nr | + SVM_EVTINJ_VALID | type; + + ++vcpu->stat.irq_injections; } =20 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_m= ode, @@ -3810,6 +3818,9 @@ bool svm_interrupt_blocked(struct kvm_vcpu *vcpu) if (!gif_set(svm)) return true; =20 + if (sev_snp_is_rinj_active(vcpu)) + return sev_snp_blocked(INJECT_IRQ, vcpu); + if (is_guest_mode(vcpu)) { /* As long as interrupts are being delivered... */ if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK) @@ -4128,6 +4139,8 @@ static void svm_cancel_injection(struct kvm_vcpu *vcp= u) struct vcpu_svm *svm =3D to_svm(vcpu); struct vmcb_control_area *control =3D &svm->vmcb->control; =20 + sev_snp_cancel_injection(vcpu); + control->exit_int_info =3D control->event_inj; control->exit_int_info_err =3D control->event_inj_err; control->event_inj =3D 0; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index f0f14801e122..95c0a7070bd1 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -41,6 +41,10 @@ extern bool x2avic_enabled; extern bool vnmi; extern int lbrv; =20 +enum inject_type { + INJECT_IRQ, +}; + /* * Clean bits in VMCB. * VMCB_ALL_CLEAN_MASK might also need to @@ -751,6 +755,17 @@ void sev_snp_init_protected_guest_state(struct kvm_vcp= u *vcpu); int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_or= der); void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end); int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn); +bool sev_snp_queue_exception(struct kvm_vcpu *vcpu); +bool sev_snp_inject(enum inject_type type, struct kvm_vcpu *vcpu); +void sev_snp_cancel_injection(struct kvm_vcpu *vcpu); +bool sev_snp_blocked(enum inject_type type, struct kvm_vcpu *vcpu); +static inline bool sev_snp_is_rinj_active(struct kvm_vcpu *vcpu) +{ + struct kvm_sev_info *sev =3D &to_kvm_svm(vcpu->kvm)->sev_info; + + return sev_snp_guest(vcpu->kvm) && + (sev->vmsa_features & SVM_SEV_FEAT_RESTRICTED_INJECTION); +}; #else static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp) { @@ -781,7 +796,11 @@ static inline int sev_private_max_mapping_level(struct= kvm *kvm, kvm_pfn_t pfn) { return 0; } - +static inline bool sev_snp_queue_exception(struct kvm_vcpu *vcpu) { return= false; } +static inline bool sev_snp_inject(enum inject_type type, struct kvm_vcpu *= vcpu) { return false; } +static inline void sev_snp_cancel_injection(struct kvm_vcpu *vcpu) {} +static inline bool sev_snp_blocked(enum inject_type type, struct kvm_vcpu = *vcpu) { return false; } +static inline bool sev_snp_is_rinj_active(struct kvm_vcpu *vcpu) { return = false; } #endif =20 /* vmenter.S */ --=20 2.34.1 From nobody Sat Nov 30 10:51:03 2024 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2076.outbound.protection.outlook.com [40.107.223.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E790166F00; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 06:05:23.4701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9280c4e8-defd-48cd-2b0e-08dcd15e8f08 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8459 Content-Type: text/plain; charset="utf-8" When restricted injection is active, only #HV exceptions can be injected in= to the SEV-SNP guest. Detect that restricted injection feature is active for the guest, and then follow the #HV doorbell communication from the GHCB specification to inject NMIs. Co-developed-by: Thomas Lendacky Signed-off-by: Thomas Lendacky Signed-off-by: Melody Wang --- arch/x86/kvm/svm/sev.c | 19 ++++++++++++++++--- arch/x86/kvm/svm/svm.c | 8 ++++++++ arch/x86/kvm/svm/svm.h | 1 + 3 files changed, 25 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index f7623fa64307..9102f7e39c52 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -5070,7 +5070,10 @@ static bool __sev_snp_inject(enum inject_type type, = struct kvm_vcpu *vcpu) if (!hvdb) return false; =20 - hvdb->events.vector =3D vcpu->arch.interrupt.nr; + if (type =3D=3D INJECT_NMI) + hvdb->events.nmi =3D 1; + else + hvdb->events.vector =3D vcpu->arch.interrupt.nr; =20 prepare_hv_injection(svm, hvdb); =20 @@ -5148,10 +5151,17 @@ void sev_snp_cancel_injection(struct kvm_vcpu *vcpu) /* Copy info back into event_inj field (replaces #HV) */ svm->vmcb->control.event_inj =3D SVM_EVTINJ_VALID; =20 + /* + * KVM only injects a single event each time (prepare_hv_injection), + * so when events.nmi is true, the vector will be zero + */ if (hvdb->events.vector) svm->vmcb->control.event_inj |=3D hvdb->events.vector | SVM_EVTINJ_TYPE_INTR; =20 + if (hvdb->events.nmi) + svm->vmcb->control.event_inj |=3D SVM_EVTINJ_TYPE_NMI; + hvdb->events.pending_events =3D 0; =20 out: @@ -5169,8 +5179,11 @@ bool sev_snp_blocked(enum inject_type type, struct k= vm_vcpu *vcpu) if (!hvdb) return true; =20 - /* Indicate interrupts blocked based on guest acknowledgment */ - blocked =3D !!hvdb->events.vector; + /* Indicate NMIs and interrupts blocked based on guest acknowledgment */ + if (type =3D=3D INJECT_NMI) + blocked =3D hvdb->events.nmi; + else + blocked =3D !!hvdb->events.vector; =20 unmap_hvdb(vcpu, &hvdb_map); =20 diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index a48388d99c97..d9c572344f0c 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3602,6 +3602,9 @@ static void svm_inject_nmi(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 + if (sev_snp_inject(INJECT_NMI, vcpu)) + goto status; + svm->vmcb->control.event_inj =3D SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI; =20 if (svm->nmi_l1_to_l2) @@ -3616,6 +3619,8 @@ static void svm_inject_nmi(struct kvm_vcpu *vcpu) svm->nmi_masked =3D true; svm_set_iret_intercept(svm); } + +status: ++vcpu->stat.nmi_injections; } =20 @@ -3786,6 +3791,9 @@ bool svm_nmi_blocked(struct kvm_vcpu *vcpu) if (!gif_set(svm)) return true; =20 + if (sev_snp_is_rinj_active(vcpu)) + return sev_snp_blocked(INJECT_NMI, vcpu); + if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm)) return false; =20 diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 95c0a7070bd1..f60ff6229ff4 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -43,6 +43,7 @@ extern int lbrv; =20 enum inject_type { INJECT_IRQ, + INJECT_NMI, }; =20 /* --=20 2.34.1 From nobody Sat Nov 30 10:51:03 2024 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2047.outbound.protection.outlook.com [40.107.243.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED56D175D5A; Tue, 10 Sep 2024 06:05:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 10 Sep 2024 01:05:39 -0500 From: Melody Wang To: , , CC: Sean Christopherson , Paolo Bonzini , Tom Lendacky , Ashish Kalra , Michael Roth , Melody Wang Subject: [PATCH v2 5/6] KVM: SVM: Inject MCEs when restricted injection is active Date: Tue, 10 Sep 2024 06:03:35 +0000 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F4:EE_|PH7PR12MB7259:EE_ X-MS-Office365-Filtering-Correlation-Id: fd731b2b-6f35-439c-5c22-08dcd15e997b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1HL9QZ1HMc15uaj3sGyHhOja3gGT8lgVusY8xy6GJ6SZ9bWh1bb/O8lju8FU?= =?us-ascii?Q?/jLSaHGzTIovx0JTH5KCmYsDiM4eHq7EndMR+KHvrp5iFhnitrdWO7ZKpt4z?= =?us-ascii?Q?hX47rxYyCEKQNZmGUksmnZZ1nRdtyd4DoYL/Z8eBP+zsqjTo7SmGP2EC+a7a?= =?us-ascii?Q?WyGVYuo275AdVM7LuKPYi/7Bb3oc7fFdp5Aym/sXqex+FqhFp6t9o0bH6q95?= =?us-ascii?Q?4yDl80wTVDnIXswQaNtJqnL7yDzsZanH3w69ZCNngR2SeAg9KZbcd4ZKtrnV?= =?us-ascii?Q?IfNpWCS0psLrXTqhjH8m+etvw5siGOBSnl2/TkP1ur8H1W1Mchb9XrxJQkYE?= =?us-ascii?Q?D4vxyv2g31ZmPYJFSqnmW+b/cBv1ajZPMoRo3iB1ybJsC/vFT/hvGGuoMj8E?= =?us-ascii?Q?7H25ufHQpwWnU7J2LrNybUymAHtJrRnQ9t/eTpWKdwrUCDEHXjBKOfHbJz06?= =?us-ascii?Q?Vm02kRHODLKBCiNzpztekSVlkc3nsGUjr4u63wYyFenHtWbrNWtxzzYLpSAA?= =?us-ascii?Q?eZI1J+krXJ/qPzrxmIZwuh317dc9cISfQJc/epUxXU/ZmpfVJ3pb9xCFZToV?= =?us-ascii?Q?rmbap4dzhKMxbDao9NT8Pm+ijF8ZBrEyHW8SZ6zDit+csrLCaFTnUhJdEtui?= =?us-ascii?Q?5CCgx42Rk+Kv56NAM35JjXxgqFe8rGee/hE/rkBYdcKAWaweuwwMbHLAQoEI?= =?us-ascii?Q?R8ztOOrGvmmSDDcdSlCLhVJehZvvE229e43mAiK2TU4JptmlO+cSxdc/gyWd?= =?us-ascii?Q?BoHJ9PQClYRW7MCVik9PCx/ywwwTttF5a2lOnYlCHEO0K9+wrv7Hef7vjnhu?= =?us-ascii?Q?vgSYoqd7TNgoY7sL7lzNTR1GgHO0988DB8S+7gFOo9Hn57+PiAKxPVtPrwAr?= =?us-ascii?Q?84MeKpysL9vQKd1uz0Wgih5kCax6+57t5R5HBsBJIJ92JUIJNncqIDfnomjO?= =?us-ascii?Q?w2kF46v3IW8LaHO2+f68UqiX8q1Ydakf3oG/c+65vVM4X2BrCjHoym8nPvtE?= =?us-ascii?Q?xp8DSRu9pNaIsrnCAC95a496Fds64Eszk6TLkj5yHd1EpR5Pl8Hyfudy3Zem?= =?us-ascii?Q?0GVys1hSsep2EYAp2q7IVz89e2Hah88APvKs6aGsQSY0ZBQ2sdr3ue+bTU7B?= =?us-ascii?Q?dlGQRZQthtvegzY0BfrGQnGv91TOqa5ZHXFKkbj6n7EVMFRDq/GASUmuMw0F?= =?us-ascii?Q?V3LzGIzYrlrlmzk00G7+0nPNjDnauu3GygVhN6Gz40sBwrtNxzrLBFwHH4x7?= =?us-ascii?Q?wDn3vTwo+U+s5DhNekCnYcuGO8YCIjwb2XrdN3FoSxQNTtPDpDFABKfthNxg?= =?us-ascii?Q?0/saCe1Z67jaY07DUOXXT40N2NSK+YoqhX4lrs+SQFFmRKbTvY7zsgo0XwvN?= =?us-ascii?Q?xFvMeNRVWQJrAdHHO+37dtcP5nTQheEe+VIrFG7+KVrT2FXlWrQlVc46ITjx?= =?us-ascii?Q?sUdA/ArSxSXxcVYYzoxPRVO4+VaIvaKS?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 06:05:41.0334 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd731b2b-6f35-439c-5c22-08dcd15e997b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7259 Content-Type: text/plain; charset="utf-8" When restricted injection is active, only #HV exceptions can be injected in= to the SEV-SNP guest. Detect that restricted injection feature is active for the guest, and then follow the #HV doorbell communication from the GHCB specification to inject= the MCEs. Co-developed-by: Thomas Lendacky Signed-off-by: Thomas Lendacky Signed-off-by: Melody Wang --- arch/x86/include/asm/kvm-x86-ops.h | 1 + arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/svm/sev.c | 16 ++++++++++++++-- arch/x86/kvm/svm/svm.c | 17 +++++++++++++++++ arch/x86/kvm/svm/svm.h | 2 ++ arch/x86/kvm/vmx/main.c | 1 + arch/x86/kvm/vmx/vmx.c | 5 +++++ arch/x86/kvm/vmx/x86_ops.h | 1 + arch/x86/kvm/x86.c | 8 ++++++++ 9 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-= x86-ops.h index 68ad4f923664..9e5764a8e031 100644 --- a/arch/x86/include/asm/kvm-x86-ops.h +++ b/arch/x86/include/asm/kvm-x86-ops.h @@ -76,6 +76,7 @@ KVM_X86_OP(inject_exception) KVM_X86_OP(cancel_injection) KVM_X86_OP(interrupt_allowed) KVM_X86_OP(nmi_allowed) +KVM_X86_OP_OPTIONAL(mce_allowed) KVM_X86_OP(get_nmi_mask) KVM_X86_OP(set_nmi_mask) KVM_X86_OP(enable_nmi_window) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 94e7b5a4fafe..cb1608a69144 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1715,6 +1715,7 @@ struct kvm_x86_ops { void (*cancel_injection)(struct kvm_vcpu *vcpu); int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection); int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection); + int (*mce_allowed)(struct kvm_vcpu *vcpu); bool (*get_nmi_mask)(struct kvm_vcpu *vcpu); void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked); /* Whether or not a virtual NMI is pending in hardware. */ diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 9102f7e39c52..0b898b16026b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -5072,6 +5072,8 @@ static bool __sev_snp_inject(enum inject_type type, s= truct kvm_vcpu *vcpu) =20 if (type =3D=3D INJECT_NMI) hvdb->events.nmi =3D 1; + else if (type =3D=3D INJECT_MCE) + hvdb->events.mce =3D 1; else hvdb->events.vector =3D vcpu->arch.interrupt.nr; =20 @@ -5089,6 +5091,11 @@ bool sev_snp_queue_exception(struct kvm_vcpu *vcpu) if (!sev_snp_is_rinj_active(vcpu)) return false; =20 + if (vcpu->arch.exception.vector =3D=3D MC_VECTOR) { + if (__sev_snp_inject(INJECT_MCE, vcpu)) + return true; + } + /* * Restricted injection is enabled, only #HV is supported. * If the vector is not HV_VECTOR, do not inject the exception, @@ -5153,7 +5160,7 @@ void sev_snp_cancel_injection(struct kvm_vcpu *vcpu) =20 /* * KVM only injects a single event each time (prepare_hv_injection), - * so when events.nmi is true, the vector will be zero + * so when events.nmi is true, the mce and vector will be zero */ if (hvdb->events.vector) svm->vmcb->control.event_inj |=3D hvdb->events.vector | @@ -5162,6 +5169,9 @@ void sev_snp_cancel_injection(struct kvm_vcpu *vcpu) if (hvdb->events.nmi) svm->vmcb->control.event_inj |=3D SVM_EVTINJ_TYPE_NMI; =20 + if (hvdb->events.mce) + svm->vmcb->control.event_inj |=3D MC_VECTOR | SVM_EVTINJ_TYPE_EXEPT; + hvdb->events.pending_events =3D 0; =20 out: @@ -5179,9 +5189,11 @@ bool sev_snp_blocked(enum inject_type type, struct k= vm_vcpu *vcpu) if (!hvdb) return true; =20 - /* Indicate NMIs and interrupts blocked based on guest acknowledgment */ + /* Indicate NMIs, MCEs and interrupts blocked based on guest acknowledgme= nt */ if (type =3D=3D INJECT_NMI) blocked =3D hvdb->events.nmi; + else if (type =3D=3D INJECT_MCE) + blocked =3D hvdb->events.mce; else blocked =3D !!hvdb->events.vector; =20 diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index d9c572344f0c..1c13c5da6eea 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3867,6 +3867,22 @@ static int svm_interrupt_allowed(struct kvm_vcpu *vc= pu, bool for_injection) return 1; } =20 +bool svm_mce_blocked(struct kvm_vcpu *vcpu) +{ + if (sev_snp_is_rinj_active(vcpu)) + return sev_snp_blocked(INJECT_MCE, vcpu); + + return false; +} + +static int svm_mce_allowed(struct kvm_vcpu *vcpu) +{ + if (svm_mce_blocked(vcpu)) + return 0; + + return 1; +} + static void svm_enable_irq_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -5066,6 +5082,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata =3D { .cancel_injection =3D svm_cancel_injection, .interrupt_allowed =3D svm_interrupt_allowed, .nmi_allowed =3D svm_nmi_allowed, + .mce_allowed =3D svm_mce_allowed, .get_nmi_mask =3D svm_get_nmi_mask, .set_nmi_mask =3D svm_set_nmi_mask, .enable_nmi_window =3D svm_enable_nmi_window, diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index f60ff6229ff4..0cf32954589f 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -44,6 +44,7 @@ extern int lbrv; enum inject_type { INJECT_IRQ, INJECT_NMI, + INJECT_MCE, }; =20 /* @@ -602,6 +603,7 @@ void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long c= r4); void disable_nmi_singlestep(struct vcpu_svm *svm); bool svm_smi_blocked(struct kvm_vcpu *vcpu); bool svm_nmi_blocked(struct kvm_vcpu *vcpu); +bool svm_mce_blocked(struct kvm_vcpu *vcpu); bool svm_interrupt_blocked(struct kvm_vcpu *vcpu); void svm_set_gif(struct vcpu_svm *svm, bool value); int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code); diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 0bf35ebe8a1b..c3a49a3b7f21 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -84,6 +84,7 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { .cancel_injection =3D vmx_cancel_injection, .interrupt_allowed =3D vmx_interrupt_allowed, .nmi_allowed =3D vmx_nmi_allowed, + .mce_allowed =3D vmx_mce_allowed, .get_nmi_mask =3D vmx_get_nmi_mask, .set_nmi_mask =3D vmx_set_nmi_mask, .enable_nmi_window =3D vmx_enable_nmi_window, diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index f18c2d8c7476..b3dce5d95329 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -5093,6 +5093,11 @@ int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, boo= l for_injection) return !vmx_interrupt_blocked(vcpu); } =20 +int vmx_mce_allowed(struct kvm_vcpu *vcpu) +{ + return 1; +} + int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) { void __user *ret; diff --git a/arch/x86/kvm/vmx/x86_ops.h b/arch/x86/kvm/vmx/x86_ops.h index ce3221cd1d01..b2b1a3bb4eb3 100644 --- a/arch/x86/kvm/vmx/x86_ops.h +++ b/arch/x86/kvm/vmx/x86_ops.h @@ -92,6 +92,7 @@ void vmx_inject_exception(struct kvm_vcpu *vcpu); void vmx_cancel_injection(struct kvm_vcpu *vcpu); int vmx_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection); int vmx_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection); +int vmx_mce_allowed(struct kvm_vcpu *vcpu); bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu); void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked); void vmx_enable_nmi_window(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 70219e406987..2007598af873 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10485,6 +10485,12 @@ static int kvm_check_and_inject_events(struct kvm_= vcpu *vcpu, } } =20 + if (vcpu->arch.exception.vector =3D=3D MC_VECTOR) { + r =3D static_call(kvm_x86_mce_allowed)(vcpu); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2024 06:05:59.0791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ffd7be6-eaec-45af-abd5-08dcd15ea441 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4422 Content-Type: text/plain; charset="utf-8" Enable the restricted injection in an SEV-SNP guest by setting the restrict= ed injection bit in the VMSA SEV features field (SEV_FEATURES[3]) from QEMU. Add the restricted injection supporting the hypervisor advertised features. Co-developed-by: Thomas Lendacky Signed-off-by: Thomas Lendacky Signed-off-by: Melody Wang --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/sev-common.h | 1 + arch/x86/kvm/svm/sev.c | 26 +++++++++++++++++++++++++- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dd4682857c12..ff8466405409 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -446,6 +446,7 @@ #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" AMD Secure Encrypted = Virtualization - Secure Nested Paging */ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* AMD hardware-enforced cache= coherency */ +#define X86_FEATURE_RESTRICTED_INJECTION (19*32+12) /* AMD SEV Restricted = Injection */ #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" AMD SEV-ES full= debug state swap support */ #define X86_FEATURE_SVSM (19*32+28) /* "svsm" SVSM present */ =20 diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-c= ommon.h index 98726c2b04f8..f409893ad1a5 100644 --- a/arch/x86/include/asm/sev-common.h +++ b/arch/x86/include/asm/sev-common.h @@ -136,6 +136,7 @@ enum psc_op { =20 #define GHCB_HV_FT_SNP BIT_ULL(0) #define GHCB_HV_FT_SNP_AP_CREATION BIT_ULL(1) +#define GHCB_HV_FT_SNP_RINJ (BIT_ULL(2) | GHCB_HV_FT_SNP_AP_CREATION) #define GHCB_HV_FT_SNP_MULTI_VMPL BIT_ULL(5) =20 /* diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 0b898b16026b..bad50378c898 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -39,7 +39,9 @@ #define GHCB_VERSION_DEFAULT 2ULL #define GHCB_VERSION_MIN 1ULL =20 -#define GHCB_HV_FT_SUPPORTED (GHCB_HV_FT_SNP | GHCB_HV_FT_SNP_AP_CREATION) +#define GHCB_HV_FT_SUPPORTED (GHCB_HV_FT_SNP | \ + GHCB_HV_FT_SNP_AP_CREATION | \ + GHCB_HV_FT_SNP_RINJ) =20 /* enable/disable SEV support */ static bool sev_enabled =3D true; @@ -56,6 +58,10 @@ module_param_named(sev_snp, sev_snp_enabled, bool, 0444); /* enable/disable SEV-ES DebugSwap support */ static bool sev_es_debug_swap_enabled =3D true; module_param_named(debug_swap, sev_es_debug_swap_enabled, bool, 0444); + +/* enable/disable SEV-SNP Restricted Injection support */ +static bool sev_snp_restricted_injection_enabled =3D true; +module_param_named(restricted_injection, sev_snp_restricted_injection_enab= led, bool, 0444); static u64 sev_supported_vmsa_features; =20 #define AP_RESET_HOLD_NONE 0 @@ -3079,6 +3085,12 @@ void __init sev_hardware_setup(void) sev_supported_vmsa_features =3D 0; if (sev_es_debug_swap_enabled) sev_supported_vmsa_features |=3D SVM_SEV_FEAT_DEBUG_SWAP; + + if (!sev_snp_enabled || !cpu_feature_enabled(X86_FEATURE_RESTRICTED_INJEC= TION)) + sev_snp_restricted_injection_enabled =3D false; + + if (sev_snp_restricted_injection_enabled) + sev_supported_vmsa_features |=3D SVM_SEV_FEAT_RESTRICTED_INJECTION; } =20 void sev_hardware_unsetup(void) @@ -4556,6 +4568,15 @@ void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm) sev_es_vcpu_after_set_cpuid(svm); } =20 +static void sev_snp_init_vmcb(struct vcpu_svm *svm) +{ + struct kvm_sev_info *sev =3D &to_kvm_svm(svm->vcpu.kvm)->sev_info; + + /* V_NMI is not supported when Restricted Injection is enabled */ + if (sev->vmsa_features & SVM_SEV_FEAT_RESTRICTED_INJECTION) + svm->vmcb->control.int_ctl &=3D ~V_NMI_ENABLE_MASK; +} + static void sev_es_init_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb =3D svm->vmcb01.ptr; @@ -4613,6 +4634,9 @@ static void sev_es_init_vmcb(struct vcpu_svm *svm) /* Clear intercepts on selected MSRs */ set_msr_interception(vcpu, svm->msrpm, MSR_EFER, 1, 1); set_msr_interception(vcpu, svm->msrpm, MSR_IA32_CR_PAT, 1, 1); + + if (sev_snp_guest(vcpu->kvm)) + sev_snp_init_vmcb(svm); } =20 void sev_init_vmcb(struct vcpu_svm *svm) --=20 2.34.1