From nobody Sat Nov 30 16:31:47 2024 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3962169397 for ; Sun, 8 Sep 2024 17:32:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.227 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816766; cv=none; b=r7iJ6y9cdB4ActdvgSlwpx4jcgb11x0Q05e/v3KUjvQthegpnqpMLH9RvbF0Gkiy8TiakXC+evfQFll8Rn4gfF0ILiJ/0TXmH0/D/SGmkPCu0Bondxy6UmsX7SL1avPwjhORG+niWPr10CPndCzdkhZ7Ss3KX4w5pLqMQ8JkJhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816766; c=relaxed/simple; bh=ieZrb6nBNYizoVaRxWgq+w4P0Om1mIl5xlMgXmHJLpQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UliLiLR+P7w8+cSDy1ZXinPH/dG87pULNjVkvqzBhjexEHZYJp5o425SZ2gUfEH8QGtlAXYUwBASGR73tHR9QnzNIft2yuQC1lVhvgAA/nwHGmMCK82ht7JyfCICTSU3+mQLJEjTOjtSTC/nvfwYDTle3E78lZLForDjWhCDByA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b=D1O2x4TG; arc=none smtp.client-ip=185.136.64.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b="D1O2x4TG" Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 2024090817323594273e59d88fa356dc for ; Sun, 08 Sep 2024 19:32:36 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=7HUlfn1xmn+4ZGiB6aVKgQXPt7LJ9m0S52DW4howHBI=; b=D1O2x4TG8yerTvR8iz6SByB6PiPmdrGEBtnM7uIHThJXi54uj1hO1+hpr84L9fQGsGbrZr X6m94dl1/lK6jb3rWr389WAkOd2+Cg4ymkQrruP6KX3EyprHq7iA2rLzeoAQaa0JPqYESF8K 1sQoW4IF/r52NuYxJWkoZYB1WufD1TeI8vJMu4dhWLdIdagT8aMyySSgBC1lg1vtE5PSPO/g Dpa6Zv6WUjAqA9KqZw7Hn6jNS1MuzB+iwY+2Rn5iE5vwQMGVBMXEDP9oimKkRYxHSPsviXHf r0UkWwMOYmy2bYAANMLCnUqNCkgitHcLDny8YHu5WYdJclGqIEAK5wNQ==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo , Krzysztof Kozlowski Subject: [PATCH v5 1/7] dt-bindings: soc: ti: Add AM65 peripheral virtualization unit Date: Sun, 8 Sep 2024 19:32:27 +0200 Message-ID: <78294ee7ac10ce9f6fc3a57ba10cee92369d8aa8.1725816753.git.jan.kiszka@siemens.com> In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The PVU allows to define a limited set of mappings for incoming DMA requests to the system memory. It is not a real IOMMU, thus hooked up under the TI SoC bindings. Signed-off-by: Jan Kiszka Reviewed-by: Krzysztof Kozlowski --- .../bindings/soc/ti/ti,am654-pvu.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.y= aml diff --git a/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml b/D= ocumentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml new file mode 100644 index 000000000000..e4a5fc47d674 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,am654-pvu.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) Siemens AG, 2024 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/ti,am654-pvu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI AM654 Peripheral Virtualization Unit + +maintainers: + - Jan Kiszka + +properties: + compatible: + enum: + - ti,am654-pvu + + reg: + maxItems: 2 + + reg-names: + items: + - const: cfg + - const: tlbif + + interrupts: + items: + - description: fault interrupt + + interrupt-names: + items: + - const: pvu + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + iommu@30f80000 { + compatible =3D "ti,am654-pvu"; + reg =3D <0x30f80000 0x1000>, + <0x36000000 0x100000>; + reg-names =3D "cfg", "tlbif"; + interrupts-extended =3D <&intr_main_navss 390>; + interrupt-names =3D "pvu"; + }; --=20 2.43.0 From nobody Sat Nov 30 16:31:47 2024 Received: from mta-64-228.siemens.flowmailer.net (mta-64-228.siemens.flowmailer.net [185.136.64.228]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FD2C176230 for ; Sun, 8 Sep 2024 17:32:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.228 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816767; cv=none; b=SAF4DNOT5j+RU1s8ELLvR5n9duodeD/30YZS+suvBkUOwFmhFcLUKXCw1BAG6vJvr/h/dbQLNLKkqa8XpcOdkPyamfpJqM9O9FRFg2f0E4aF7GqA0kVqcvVaisBXF2GYnDiFThnt5PD2lBKD0BEUDyLgiuut7WOXfLgMQpytq5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816767; c=relaxed/simple; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer From: Jan Kiszka The PVU on the AM65 SoC is capable of restricting DMA from PCIe devices to specific regions of host memory. Add the optional property "memory-regions" to point to such regions of memory when PVU is used. Since the PVU deals with system physical addresses, utilizing the PVU with PCIe devices also requires setting up the VMAP registers to map the Requester ID of the PCIe device to the CBA Virtual ID, which in turn is mapped to the system physical address. Hence, describe the VMAP registers which are optional unless the PVU shall be used for PCIe. Signed-off-by: Jan Kiszka --- CC: Lorenzo Pieralisi CC: "Krzysztof Wilczy=C5=84ski" CC: Bjorn Helgaas CC: linux-pci@vger.kernel.org --- .../bindings/pci/ti,am65-pci-host.yaml | 29 +++++++++++++++++-- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/= Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index 0a9d10532cc8..0c297d12173c 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -20,14 +20,18 @@ properties: - ti,keystone-pcie =20 reg: - maxItems: 4 + minItems: 4 + maxItems: 6 =20 reg-names: + minItems: 4 items: - const: app - const: dbics - const: config - const: atu + - const: vmap_lp + - const: vmap_hp =20 interrupts: maxItems: 1 @@ -83,13 +87,30 @@ if: compatible: enum: - ti,am654-pcie-rc + then: + properties: + memory-region: + maxItems: 1 + description: | + phandle to a restricted DMA pool to be used for all devices behind + this controller. The regions should be defined according to + reserved-memory/shared-dma-pool.yaml. + required: - dma-coherent - power-domains - msi-map - num-viewport =20 +else: + properties: + reg: + maxItems: 4 + + reg-names: + maxItems: 4 + unevaluatedProperties: false =20 examples: @@ -104,8 +125,10 @@ examples: reg =3D <0x5500000 0x1000>, <0x5501000 0x1000>, <0x10000000 0x2000>, - <0x5506000 0x1000>; - reg-names =3D "app", "dbics", "config", "atu"; + <0x5506000 0x1000>, + <0x2900000 0x1000>, + <0x2908000 0x1000>; + reg-names =3D "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp= "; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.43.0 From nobody Sat Nov 30 16:31:47 2024 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C26F1741F8 for ; Sun, 8 Sep 2024 17:32:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816767; cv=none; b=sBpEyxLqMYi+yphOgq3LrWyYTpHPqnfTsRwLWHBjl+m6SBaYn3jQBY/WfiQwIyf7v5ZStbpXKG0cuqDIWZxwRbQeV7loyUn2a9qc5x4+vYrv7VIPwX+0u6mLGP0IyFeOKtN0bnHPxgDLhxhEnbO0C48BnFUCgx21HQALQNkbt5Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816767; c=relaxed/simple; bh=8qMrgAHX+pgQ14Qv8Pb3MvPr22VN9dN/SAnmJ4kJqxU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V2uvSqWmWgh1uVs8GMC1zXIzlDb6uXsQc/lXwafDQcJOj1DpxbITieImm1jJSKSwCviASeQk2A+uFMSmStl/BrzLllcm1//OITX03n+4AZ/tPyk1I8r0FkpJLdu8tM2vn4961DDpKlSk/RAC9A43JCcoWItA1vfgOqKPH0sRqkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b=hkI8Biwv; arc=none smtp.client-ip=185.136.65.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b="hkI8Biwv" Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 2024090817323756a6d58568a9d9af65 for ; Sun, 08 Sep 2024 19:32:37 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=qvfyyVm1iR121poii9xLpa2y/wAoo5hJX45IAlC66mk=; b=hkI8Biwv8Xj/nW2jtTqTb2uZhPNUwnzTwPXfD4wYDOLV+Mk+oKDLXnhtoMusXI7R/fOfmK po6w3gYWjKjEPYfKBjfm6j/PbfQ9/9V962sosqF1XCIV+T8YcSGyTMIB1UuRMkkN11AZThGZ rjNfgwAHz3K5DCexWLia8eizTZiS+E1nIImD2w8qGnij8UL8Z4nptQlsXrzeeYDNP46/aNZj fQPbUzrkyvuqnlYuUgjnUmSnlRWixIsaSsRMyDkT2HfixRQKPGBKFvf8z5hRrmV63FRn5YMR vB7zt0ewiHOMXWt2JoKvgxeBPyksYX6IB31ctfuH3xwQtsAk9iNYaG8A==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH v5 3/7] soc: ti: Add IOMMU-like PVU driver Date: Sun, 8 Sep 2024 19:32:29 +0200 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka The TI Peripheral Virtualization Unit (PVU) permits to define a limited set of mappings for DMA requests on the system memory. Unlike with an IOMMU, there is no fallback to a memory-backed page table, only a fixed set of register-backed TLBs. Emulating an IOMMU behavior appears to be the more fragile the more fragmentation of pending requests occur. Therefore, this driver does not expose the PVU as an IOMMU. It rather introduces a simple, static interface to devices that are under restricted-dma-pool constraints. They can register their pools with the PVUs, enabling only those pools to work for DMA. As also MSI is issued as DMA, the PVU already register the related translator region of the AM654 as valid DMA target. This driver is the essential building block for limiting DMA from untrusted devices to clearly defined memory regions in the absence of a real IOMMU (SMMU). Co-developed-by: Diogo Ivo Signed-off-by: Jan Kiszka --- drivers/soc/ti/Kconfig | 4 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/ti-pvu.c | 500 ++++++++++++++++++++++++++++++++++++++++ include/linux/ti-pvu.h | 16 ++ 4 files changed, 521 insertions(+) create mode 100644 drivers/soc/ti/ti-pvu.c create mode 100644 include/linux/ti-pvu.h diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 1a93001c9e36..af7173ad84de 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -82,6 +82,10 @@ config TI_PRUSS processors on various TI SoCs. It's safe to say N here if you're not interested in the PRU or if you are unsure. =20 +config TI_PVU + bool "TI Peripheral Virtualization Unit driver" + depends on ARCH_K3 && DMA_RESTRICTED_POOL + endif # SOC_TI =20 config TI_SCI_INTA_MSI_DOMAIN diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index cb800a745e66..ecff3fd8c433 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_TI_K3_RINGACC) +=3D k3-ringacc.o obj-$(CONFIG_TI_K3_SOCINFO) +=3D k3-socinfo.o obj-$(CONFIG_TI_PRUSS) +=3D pruss.o obj-$(CONFIG_POWER_AVS_OMAP) +=3D smartreflex.o +obj-$(CONFIG_TI_PVU) +=3D ti-pvu.o diff --git a/drivers/soc/ti/ti-pvu.c b/drivers/soc/ti/ti-pvu.c new file mode 100644 index 000000000000..8bce3845d5b6 --- /dev/null +++ b/drivers/soc/ti/ti-pvu.c @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Peripheral Virtualization Unit driver for static DMA isolation + * + * Copyright (c) 2024, Siemens AG + */ + +#include +#include +#include +#include +#include +#include + +#define PVU_CONFIG 0x4 +#define PVU_ENABLE 0x10 +#define PVU_VIRTID_MAP1 0x14 +#define PVU_VIRTID_MAP2 0x18 +#define PVU_EXCEPTION_LOGGING_CONTROL 0x120 +#define PVU_EXCEPTION_LOGGING_HEADER0 0x124 +#define PVU_EXCEPTION_LOGGING_HEADER1 0x128 +#define PVU_EXCEPTION_LOGGING_DATA0 0x12c +#define PVU_EXCEPTION_LOGGING_DATA1 0x130 +#define PVU_EXCEPTION_LOGGING_DATA2 0x134 +#define PVU_EXCEPTION_LOGGING_DATA2_SECURE BIT(0) +#define PVU_EXCEPTION_LOGGING_DATA2_PRIV BIT(1) +#define PVU_EXCEPTION_LOGGING_DATA2_CACHEABLE BIT(2) +#define PVU_EXCEPTION_LOGGING_DATA2_DEBUG BIT(3) +#define PVU_EXCEPTION_LOGGING_DATA2_READ BIT(4) +#define PVU_EXCEPTION_LOGGING_DATA2_WRITE BIT(5) +#define PVU_EXCEPTION_LOGGING_DATA3 0x138 +#define PVU_EXCEPTION_ENABLE_SET 0x148 +#define PVU_EOI_REG 0x150 + +#define PVU_CHAIN 0x0 +#define PVU_CHAIN_EN BIT(31) +#define PVU_CHAIN_LOG_DIS BIT(30) +#define PVU_CHAIN_FAULT BIT(29) +#define PVU_CHAIN_MASK 0xfff +#define PVU_ENTRY0 0x20 +#define PVU_ENTRY1 0x24 +#define PVU_ENTRY1_RESERVED_MASK 0xffff0000 +#define PVU_ENTRY1_VBASE_H_MASK 0xffff +#define PVU_ENTRY2 0x28 +#define PVU_ENTRY2_RESERVED_MASK 0x1fd00080 +#define PVU_ENTRY2_INVALID (0U << 30) +#define PVU_ENTRY2_VALID (2U << 30) +#define PVU_ENTRY2_MODE_MASK 0xc0000000 +#define PVU_ENTRY2_PSIZE_SHIFT 16 +#define PVU_ENTRY2_PSIZE_MASK 0xf +#define PVU_ENTRY2_PERM_SX BIT(15) +#define PVU_ENTRY2_PERM_SW BIT(14) +#define PVU_ENTRY2_PERM_SR BIT(13) +#define PVU_ENTRY2_PERM_UX BIT(12) +#define PVU_ENTRY2_PERM_UW BIT(11) +#define PVU_ENTRY2_PERM_UR BIT(10) +#define PVU_ENTRY2_MEM_WRITETHROUGH (2 << 8) +#define PVU_ENTRY2_OUTER_SHARABLE BIT(4) +#define PVU_ENTRY2_IS_NOALLOC (0 << 2) +#define PVU_ENTRY2_OS_NOALLOC (0 << 0) +#define PVU_ENTRY4 0x30 +#define PVU_ENTRY5 0x34 +#define PVU_ENTRY5_RESERVED_MASK 0xffff0000 +#define PVU_ENTRY5_PBASE_H_MASK 0xffff +#define PVU_ENTRY6 0x38 +#define PVU_ENTRY6_RESERVED_MASK 0xffffffe0 + +#define NUM_VIRTIDS 1 + +static const struct regmap_config pvu_cfg_regmap_cfg =3D { + .name =3D "pvu-cfg", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D PVU_EOI_REG, +}; + +enum pvu_cfg_regfields { + PVU_TLBS, + PVU_TLB_ENTRIES, + PVU_ENABLED, + PVU_DMA_CNT, + PVU_DMA_CL0, + PVU_DMA_CL1, + PVU_DMA_CL2, + PVU_DMA_CL3, + PVU_MAX_VIRTID, + PVU_EXC_SRC_ID, + PVU_EXC_CODE, + PVU_EXC_ADDR_L, + PVU_EXC_ADDR_H, + PVU_EXC_PRIV_ID, + PVU_EXC_PROPS, + PVU_EXC_ROUTE_ID, + PVU_EXC_BYTE_CNT, + PVU_EXC_ENABLE, + PVU_EOI, + PVU_MAX_CFG_FIELDS, +}; + +static const struct reg_field pvu_cfg_reg_fields[] =3D { + [PVU_TLBS] =3D REG_FIELD(PVU_CONFIG, 0, 15), + [PVU_TLB_ENTRIES] =3D REG_FIELD(PVU_CONFIG, 16, 23), + [PVU_ENABLED] =3D REG_FIELD(PVU_ENABLE, 0, 0), + [PVU_DMA_CNT] =3D REG_FIELD(PVU_VIRTID_MAP1, 0, 11), + [PVU_DMA_CL0] =3D REG_FIELD(PVU_VIRTID_MAP1, 16, 17), + [PVU_DMA_CL1] =3D REG_FIELD(PVU_VIRTID_MAP1, 18, 19), + [PVU_DMA_CL2] =3D REG_FIELD(PVU_VIRTID_MAP1, 20, 21), + [PVU_DMA_CL3] =3D REG_FIELD(PVU_VIRTID_MAP1, 22, 23), + [PVU_MAX_VIRTID] =3D REG_FIELD(PVU_VIRTID_MAP2, 0, 11), + [PVU_EXC_SRC_ID] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_HEADER0, 8, 23), + [PVU_EXC_CODE] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_HEADER1, 16, 23), + [PVU_EXC_ADDR_L] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA0, 0, 31), + [PVU_EXC_ADDR_H] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA1, 0, 15), + [PVU_EXC_PRIV_ID] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 0, 7), + [PVU_EXC_PROPS] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 8, 13), + [PVU_EXC_ROUTE_ID] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA2, 16, 27), + [PVU_EXC_BYTE_CNT] =3D REG_FIELD(PVU_EXCEPTION_LOGGING_DATA3, 0, 9), + [PVU_EXC_ENABLE] =3D REG_FIELD(PVU_EXCEPTION_ENABLE_SET, 0, 0), + [PVU_EOI] =3D REG_FIELD(PVU_EOI_REG, 0, 15), +}; + +struct ti_pvu { + struct list_head entry; + struct platform_device *pdev; + struct regmap *cfg; + struct regmap_field *cfg_fields[PVU_MAX_CFG_FIELDS]; + void __iomem *tlbif_base; + unsigned int num_tlbs; + unsigned int num_entries; +}; + +static const char *pvu_excp_code_string[] =3D { + "PVU miss", + "maximum VirtID violation", + "", + "read permission violation", + "write permission violation", + "execute permission violation", + "prefetch permission violation", + "", +}; + +static const u64 pvu_page_size[] =3D { + 4 * 1024ULL, + 16 * 1024ULL, + 64 * 1024ULL, + 2 * 1024 * 1024ULL, + 32 * 1024 * 1024ULL, + 512 * 1024 * 1024ULL, + 1 * 1024 * 1024 * 1024ULL, + 16 * 1024 * 1024 * 1024ULL +}; + +static DEFINE_MUTEX(ti_pvu_lock); +static LIST_HEAD(ti_pvu_list); + +static unsigned int pvu_field_read(struct ti_pvu *pvu, enum pvu_cfg_regfie= lds f) +{ + int ret; + unsigned int val; + + ret =3D regmap_field_read(pvu->cfg_fields[f], &val); + if (ret) + dev_err(&pvu->pdev->dev, "failed to read field\n"); + + return val; +} + +static void pvu_field_write(struct ti_pvu *pvu, enum pvu_cfg_regfields f, + unsigned int val) +{ + int ret; + + ret =3D regmap_field_write(pvu->cfg_fields[f], val); + if (ret) + dev_err(&pvu->pdev->dev, "failed to write field\n"); +} + +static irqreturn_t pvu_fault_isr(int irq, void *dev_id) +{ + u32 code, bytes, route_id, priv_id, props; + struct ti_pvu *pvu =3D dev_id; + const char *code_str; + u64 address; + + code =3D pvu_field_read(pvu, PVU_EXC_CODE); + code_str =3D pvu_excp_code_string[ + min(code, (u32)ARRAY_SIZE(pvu_excp_code_string) - 1)]; + + dev_err(&pvu->pdev->dev, "fault detected, code %d (%s)\n", + code, code_str); + + address =3D pvu_field_read(pvu, PVU_EXC_ADDR_L); + address |=3D (u64)pvu_field_read(pvu, PVU_EXC_ADDR_H) << 32; + + bytes =3D pvu_field_read(pvu, PVU_EXC_BYTE_CNT); + + route_id =3D pvu_field_read(pvu, PVU_EXC_ROUTE_ID); + priv_id =3D pvu_field_read(pvu, PVU_EXC_PRIV_ID); + props =3D pvu_field_read(pvu, PVU_EXC_PROPS); + + dev_err(&pvu->pdev->dev, + " address 0x%016llx size %d route-ID %d priv-ID %d flags %c%c%c%c%c%c\n= ", + address, bytes, route_id, priv_id, + (props & PVU_EXCEPTION_LOGGING_DATA2_WRITE) ? 'W' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_READ) ? 'R' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_DEBUG) ? 'D' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_CACHEABLE) ? 'C' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_PRIV) ? 'P' : '-', + (props & PVU_EXCEPTION_LOGGING_DATA2_SECURE) ? 'S' : '-'); + + pvu_field_write(pvu, PVU_EOI, 0); + + return IRQ_HANDLED; +} + +static void __iomem *pvu_get_entry_base(struct ti_pvu *pvu, unsigned int e= ntry) +{ + return pvu->tlbif_base + (entry / pvu->num_entries) * 0x1000 + + (entry % pvu->num_entries) * 0x20; +} + +static int pvu_get_free_entry(struct ti_pvu *pvu) +{ + unsigned int n; + u32 val; + + /* We use up to 2 TLBs via chainging */ + for (n =3D 0; n < pvu->num_entries * 2; n++) { + val =3D readl(pvu_get_entry_base(pvu, n) + PVU_ENTRY2); + if ((val & PVU_ENTRY2_MODE_MASK) =3D=3D PVU_ENTRY2_INVALID) + return n; + } + return -ENOSPC; +} + +static void pvu_write_entry(struct ti_pvu *pvu, unsigned int entry, + u64 addr, u32 psize) +{ + void __iomem *entry_base =3D pvu_get_entry_base(pvu, entry); + u32 val; + + writel((u32)addr, entry_base + PVU_ENTRY0); + + val =3D readl(entry_base + PVU_ENTRY1); + val &=3D PVU_ENTRY1_RESERVED_MASK; + val |=3D (addr >> 32) & PVU_ENTRY1_VBASE_H_MASK; + writel(val, entry_base + PVU_ENTRY1); + + writel((u32)addr, entry_base + PVU_ENTRY4); + + val =3D readl(entry_base + PVU_ENTRY5); + val &=3D PVU_ENTRY5_RESERVED_MASK; + val |=3D (addr >> 32) & PVU_ENTRY5_PBASE_H_MASK; + writel(val, entry_base + PVU_ENTRY5); + + val =3D readl(entry_base + PVU_ENTRY6); + val &=3D PVU_ENTRY6_RESERVED_MASK; + writel(val, entry_base + PVU_ENTRY6); + + val =3D readl(entry_base + PVU_ENTRY2); + val &=3D PVU_ENTRY2_RESERVED_MASK; + val |=3D psize << PVU_ENTRY2_PSIZE_SHIFT; + val |=3D PVU_ENTRY2_VALID | + PVU_ENTRY2_PERM_UR | PVU_ENTRY2_PERM_SR | + PVU_ENTRY2_PERM_UW | PVU_ENTRY2_PERM_SW | + PVU_ENTRY2_PERM_UX | PVU_ENTRY2_PERM_SX | + PVU_ENTRY2_MEM_WRITETHROUGH | PVU_ENTRY2_OUTER_SHARABLE | + PVU_ENTRY2_IS_NOALLOC | PVU_ENTRY2_OS_NOALLOC; + writel(val, entry_base + PVU_ENTRY2); +} + +static int pvu_create_region(struct ti_pvu *pvu, u64 addr, u64 size) +{ + u64 page_size; + int psize; + int entry; + + while (size > 0) { + entry =3D pvu_get_free_entry(pvu); + if (entry < 0) { + dev_err(&pvu->pdev->dev, "ran out of TLB entries\n"); + return -ENOSPC; + } + + for (psize =3D ARRAY_SIZE(pvu_page_size) - 1; psize >=3D 0; psize--) { + page_size =3D pvu_page_size[psize]; + if (size >=3D page_size && (addr & (page_size - 1)) =3D=3D 0) + break; + } + if (psize < 0) { + dev_err(&pvu->pdev->dev, "unaligned region provided\n"); + return -EINVAL; + } + + pvu_write_entry(pvu, entry, addr, psize); + dev_info(&pvu->pdev->dev, + "created TLB entry %d.%d: 0x%08llx, psize %d (0x%08llx)\n", + entry / pvu->num_entries, entry % pvu->num_entries, + addr, psize, page_size); + + size -=3D page_size; + addr +=3D page_size; + } + + return 0; +} + +static void pvu_remove_region(struct ti_pvu *pvu, u64 addr, u64 size) +{ + void __iomem *entry_base; + unsigned int n, psize; + u64 entry_addr; + u32 entry2; + + for (n =3D 0; n < pvu->num_entries * 2; n++) { + entry_base =3D pvu_get_entry_base(pvu, n); + entry2 =3D readl(entry_base + PVU_ENTRY2); + if ((entry2 & PVU_ENTRY2_MODE_MASK) !=3D PVU_ENTRY2_VALID) + continue; + + entry_addr =3D readl(entry_base + PVU_ENTRY0); + entry_addr |=3D (u64)(readl(entry_base + PVU_ENTRY1) & + PVU_ENTRY1_VBASE_H_MASK) << 32; + + psize =3D (entry2 >> PVU_ENTRY2_PSIZE_SHIFT) & + PVU_ENTRY2_PSIZE_MASK; + if (psize >=3D ARRAY_SIZE(pvu_page_size)) + continue; + + if (entry_addr >=3D addr && + (entry_addr + pvu_page_size[psize]) <=3D (addr + size)) { + entry2 &=3D ~PVU_ENTRY2_MODE_MASK; + entry2 |=3D PVU_ENTRY2_INVALID; + writel(entry2, entry_base + PVU_ENTRY2); + + dev_info(&pvu->pdev->dev, "removed TLB entry %d.%d\n", + n / pvu->num_entries, n % pvu->num_entries); + } + } +} + +int ti_pvu_create_region(unsigned int virt_id, const struct resource *regi= on) +{ + struct ti_pvu *pvu; + int err =3D 0; + + if (virt_id >=3D NUM_VIRTIDS) + return -EINVAL; + + mutex_lock(&ti_pvu_lock); + + list_for_each_entry(pvu, &ti_pvu_list, entry) { + err =3D pvu_create_region(pvu, region->start, + region->end + 1 - region->start); + if (err) + break; + } + + mutex_unlock(&ti_pvu_lock); + + return err; +} + +int ti_pvu_remove_region(unsigned int virt_id, const struct resource *regi= on) +{ + struct ti_pvu *pvu; + + if (virt_id >=3D NUM_VIRTIDS) + return -EINVAL; + + mutex_lock(&ti_pvu_lock); + + list_for_each_entry(pvu, &ti_pvu_list, entry) { + pvu_remove_region(pvu, region->start, + region->end + 1 - region->start); + } + + mutex_unlock(&ti_pvu_lock); + + return 0; +} + +static int ti_pvu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *its_node; + void __iomem *base; + struct ti_pvu *pvu; + u32 val; + int ret; + + pvu =3D devm_kzalloc(dev, sizeof(*pvu), GFP_KERNEL); + if (!pvu) + return -ENOMEM; + + pvu->pdev =3D pdev; + + base =3D devm_platform_ioremap_resource_byname(pdev, "cfg"); + if (IS_ERR(base)) + return PTR_ERR(base); + + pvu->cfg =3D devm_regmap_init_mmio(dev, base, &pvu_cfg_regmap_cfg); + if (IS_ERR(pvu->cfg)) + return dev_err_probe(dev, PTR_ERR(pvu->cfg), "failed to init cfg regmap"= ); + + ret =3D devm_regmap_field_bulk_alloc(dev, pvu->cfg, pvu->cfg_fields, + pvu_cfg_reg_fields, PVU_MAX_CFG_FIELDS); + if (ret) + return dev_err_probe(dev, ret, "failed to alloc cfg regmap fields"); + + pvu->num_tlbs =3D pvu_field_read(pvu, PVU_TLBS); + pvu->num_entries =3D pvu_field_read(pvu, PVU_TLB_ENTRIES); + dev_info(dev, "TLBs: %d, entries per TLB: %d\n", pvu->num_tlbs, + pvu->num_entries); + + pvu->tlbif_base =3D devm_platform_ioremap_resource_byname(pdev, "tlbif"); + if (IS_ERR(pvu->tlbif_base)) + return PTR_ERR(pvu->tlbif_base); + + its_node =3D of_find_compatible_node(0, 0, "arm,gic-v3-its"); + if (its_node) { + u32 pre_its_window[2]; + + ret =3D of_property_read_u32_array(its_node, + "socionext,synquacer-pre-its", + pre_its_window, + ARRAY_SIZE(pre_its_window)); + if (ret) { + dev_err(dev, "failed to read pre-its property\n"); + return ret; + } + + ret =3D pvu_create_region(pvu, pre_its_window[0], + pre_its_window[1]); + if (ret) + return ret; + } + + /* Enable the first two TLBs, chaining from 0 to 1 */ + val =3D readl(pvu->tlbif_base + PVU_CHAIN); + val |=3D PVU_CHAIN_EN | 1; + writel(val, pvu->tlbif_base + PVU_CHAIN); + + val =3D readl(pvu->tlbif_base + PVU_CHAIN + 0x1000); + val |=3D PVU_CHAIN_EN; + writel(val, pvu->tlbif_base + PVU_CHAIN + 0x1000); + + pvu_field_write(pvu, PVU_DMA_CNT, 0); + pvu_field_write(pvu, PVU_DMA_CL0, 0); + pvu_field_write(pvu, PVU_DMA_CL1, 0); + pvu_field_write(pvu, PVU_DMA_CL2, 0); + pvu_field_write(pvu, PVU_DMA_CL3, 0); + pvu_field_write(pvu, PVU_MAX_VIRTID, NUM_VIRTIDS); + + ret =3D platform_get_irq(pdev, 0); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to get irq\n"); + + ret =3D devm_request_irq(dev, ret, pvu_fault_isr, 0, dev_name(dev), pvu); + if (ret) + return dev_err_probe(dev, ret, "failed to request irq\n"); + + pvu_field_write(pvu, PVU_EXC_ENABLE, 1); + pvu_field_write(pvu, PVU_ENABLED, 1); + + dev_set_drvdata(dev, pvu); + + mutex_lock(&ti_pvu_lock); + list_add(&pvu->entry, &ti_pvu_list); + mutex_unlock(&ti_pvu_lock); + + return 0; +} + +static void ti_pvu_remove(struct platform_device *pdev) +{ + struct ti_pvu *pvu =3D dev_get_drvdata(&pdev->dev); + + mutex_lock(&ti_pvu_lock); + list_del(&pvu->entry); + mutex_unlock(&ti_pvu_lock); +} + +static const struct of_device_id ti_pvu_of_match[] =3D { + { .compatible =3D "ti,am654-pvu", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ti_pvu_of_match); + +static struct platform_driver ti_pvu_driver =3D { + .driver =3D { + .name =3D "ti-pvu", + .of_match_table =3D ti_pvu_of_match, + }, + .probe =3D ti_pvu_probe, + .remove_new =3D ti_pvu_remove, +}; +module_platform_driver(ti_pvu_driver); diff --git a/include/linux/ti-pvu.h b/include/linux/ti-pvu.h new file mode 100644 index 000000000000..acd4d9e0dc86 --- /dev/null +++ b/include/linux/ti-pvu.h @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TI Peripheral Virtualization Unit driver for static DMA isolation + * + * Copyright (c) 2024, Siemens AG + */ + +#ifndef _LINUX_TI_PVU_H +#define _LINUX_TI_PVU_H + +#include + +int ti_pvu_create_region(unsigned int virt_id, const struct resource *regi= on); +int ti_pvu_remove_region(unsigned int virt_id, const struct resource *regi= on); + +#endif /* _LINUX_TI_PVU_H */ --=20 2.43.0 From nobody Sat Nov 30 16:31:47 2024 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C460176AAD for ; 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From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas Subject: [PATCH v5 4/7] PCI: keystone: Add support for PVU-based DMA isolation on AM654 Date: Sun, 8 Sep 2024 19:32:30 +0200 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer From: Jan Kiszka The AM654 lacks an IOMMU, thus does not support isolating DMA requests from untrusted PCI devices to selected memory regions this way. Use static PVU-based protection instead. The PVU, when enabled, will only accept DMA requests that address previously configured regions. Use the availability of a restricted-dma-pool memory region as trigger and register it as valid DMA target with the PVU. In addition, enable the mapping of requester IDs to VirtIDs in the PCI RC. Use only a single VirtID so far, catching all devices. This may be extended later on. Signed-off-by: Jan Kiszka --- CC: Lorenzo Pieralisi CC: "Krzysztof Wilczy=C5=84ski" CC: Bjorn Helgaas CC: linux-pci@vger.kernel.org --- drivers/pci/controller/dwc/pci-keystone.c | 108 ++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/contro= ller/dwc/pci-keystone.c index 2219b1a866fa..a5954cae6d5d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,7 @@ #include #include #include +#include =20 #include "../../pci.h" #include "pcie-designware.h" @@ -111,6 +113,16 @@ =20 #define PCI_DEVICE_ID_TI_AM654X 0xb00c =20 +#define KS_PCI_VIRTID 0 + +#define PCIE_VMAP_xP_CTRL 0x0 +#define PCIE_VMAP_xP_REQID 0x4 +#define PCIE_VMAP_xP_VIRTID 0x8 + +#define PCIE_VMAP_xP_CTRL_EN BIT(0) + +#define PCIE_VMAP_xP_VIRTID_VID_MASK 0xfff + struct ks_pcie_of_data { enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; @@ -1125,6 +1137,96 @@ static const struct of_device_id ks_pcie_of_match[] = =3D { { }, }; =20 +#ifdef CONFIG_TI_PVU +static int ks_init_vmap(struct platform_device *pdev, const char *vmap_nam= e) +{ + struct resource *res; + void __iomem *base; + u32 val; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, vmap_name); + base =3D devm_pci_remap_cfg_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + writel(0, base + PCIE_VMAP_xP_REQID); + + val =3D readl(base + PCIE_VMAP_xP_VIRTID); + val &=3D ~PCIE_VMAP_xP_VIRTID_VID_MASK; + val |=3D KS_PCI_VIRTID; + writel(val, base + PCIE_VMAP_xP_VIRTID); + + val =3D readl(base + PCIE_VMAP_xP_CTRL); + val |=3D PCIE_VMAP_xP_CTRL_EN; + writel(val, base + PCIE_VMAP_xP_CTRL); + + return 0; +} + +static int ks_init_restricted_dma(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct of_phandle_iterator it; + struct resource phys; + int err; + + /* Only process the first restricted dma pool, more are not allowed */ + of_for_each_phandle(&it, err, dev->of_node, "memory-region", + NULL, 0) { + if (of_device_is_compatible(it.node, "restricted-dma-pool")) + break; + } + if (err) + return err =3D=3D -ENOENT ? 0 : err; + + err =3D of_address_to_resource(it.node, 0, &phys); + if (err < 0) { + dev_err(dev, "failed to parse memory region %pOF: %d\n", + it.node, err); + return 0; + } + + /* Map all incoming requests on low and high prio port to virtID 0 */ + err =3D ks_init_vmap(pdev, "vmap_lp"); + if (err) + return err; + err =3D ks_init_vmap(pdev, "vmap_hp"); + if (err) + return err; + + /* + * Enforce DMA pool usage with the help of the PVU. + * Any request outside will be dropped and raise an error at the PVU. + */ + return ti_pvu_create_region(KS_PCI_VIRTID, &phys); +} + +static void ks_release_restricted_dma(struct platform_device *pdev) +{ + struct of_phandle_iterator it; + struct resource phys; + int err; + + of_for_each_phandle(&it, err, pdev->dev.of_node, "memory-region", + NULL, 0) { + if (of_device_is_compatible(it.node, "restricted-dma-pool") && + of_address_to_resource(it.node, 0, &phys) =3D=3D 0) { + ti_pvu_remove_region(KS_PCI_VIRTID, &phys); + break; + } + } +} +#else +static inline int ks_init_restricted_dma(struct platform_device *pdev) +{ + return 0; +} + +static inline void ks_release_restricted_dma(struct platform_device *pdev) +{ +} +#endif + static int ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; @@ -1273,6 +1375,10 @@ static int ks_pcie_probe(struct platform_device *pde= v) if (ret < 0) goto err_get_sync; =20 + ret =3D ks_init_restricted_dma(pdev); + if (ret < 0) + goto err_get_sync; + switch (mode) { case DW_PCIE_RC_TYPE: if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { @@ -1354,6 +1460,8 @@ static void ks_pcie_remove(struct platform_device *pd= ev) int num_lanes =3D ks_pcie->num_lanes; struct device *dev =3D &pdev->dev; =20 + ks_release_restricted_dma(pdev); + pm_runtime_put(dev); pm_runtime_disable(dev); ks_pcie_disable_phy(ks_pcie); --=20 2.43.0 From nobody Sat Nov 30 16:31:47 2024 Received: from mta-64-226.siemens.flowmailer.net (mta-64-226.siemens.flowmailer.net [185.136.64.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16653176AC2 for ; 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From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH v5 5/7] arm64: dts: ti: k3-am65-main: Add PVU nodes Date: Sun, 8 Sep 2024 19:32:31 +0200 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Add nodes for the two PVUs of the AM65. Keep them disabled, though, because the board has to additionally define DMA pools and the devices to be isolated. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index ba43325c0eec..2582dad68dff 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -841,6 +841,26 @@ main_cpts_mux: refclk-mux { assigned-clock-parents =3D <&k3_clks 118 5>; }; }; + + ti_pvu0: iommu@30f80000 { + compatible =3D "ti,am654-pvu"; + reg =3D <0 0x30f80000 0 0x1000>, + <0 0x36000000 0 0x100000>; + reg-names =3D "cfg", "tlbif"; + interrupts-extended =3D <&intr_main_navss 390>; + interrupt-names =3D "pvu"; + status =3D "disabled"; + }; + + ti_pvu1: iommu@30f81000 { + compatible =3D "ti,am654-pvu"; + reg =3D <0 0x30f81000 0 0x1000>, + <0 0x36100000 0 0x100000>; + reg-names =3D "cfg", "tlbif"; + interrupts-extended =3D <&intr_main_navss 389>; + interrupt-names =3D "pvu"; + status =3D "disabled"; + }; }; =20 main_gpio0: gpio@600000 { --=20 2.43.0 From nobody Sat Nov 30 16:31:47 2024 Received: from mta-64-225.siemens.flowmailer.net (mta-64-225.siemens.flowmailer.net [185.136.64.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 051BB17625F for ; Sun, 8 Sep 2024 17:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.64.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816769; cv=none; b=r3cv5WciRMtSUrT5ZKE3nf+HN0vWLIR88nPGeerixgw1VhvInLsqoj0kq1Bqv2W45+zApKcFKGt64YCxqZ9bbzQZXi0/9oRtG2qrJI1XVhyXqtrV0ZbMElIWoEoZD1dzRmPTNJhTmZF62hHePqIK9l5ftfPB6PO0rElzsh7LsJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725816769; c=relaxed/simple; bh=ZQ5xnhl5tcxpDnHE2vmK0Jg4RiH5lFRh8/aBKQ90dWw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zj0HISFSC/0Bjb6PLNR1U6MaCasajCOyXBD6QTk7QvEHJX3fVVJYzNg7nYHwymhFiGmWSl0s7UIMq5pKTn7rQz6od9Zprcl7Hj1A9L+xR4m5Z883GMUJFZjP6W+uKf95KQomF76YidBOps7tR8fZAuA+gofXPX9BMtGNslzy+Yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b=YwB9DV+p; arc=none smtp.client-ip=185.136.64.225 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=jan.kiszka@siemens.com header.b="YwB9DV+p" Received: by mta-64-225.siemens.flowmailer.net with ESMTPSA id 20240908173238338e20522420b533f6 for ; Sun, 08 Sep 2024 19:32:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=AbNAvrLHi+QFmGP7oAo1eWelX8ED/CVynTahfKnv7FE=; b=YwB9DV+pv3hp+qwU1+WfztkiyCULXVSKEwqb1fc8BorF1yBVTY59kpDbjqXKVDWBUlAjzi OlzCvzH6vxNYZ/XApsW9r1IhuZS85ZGZh9uhJ8Xd1/s3nyI670G7xxgLYl0QMq13kQik6Ia+ Z7mZS1yxTyr1iEh8ebNAkCJTcgAUYnMzgd69j71Btib2NHCyKxdwwAgWpHazBAPZusMg6n7n dZmEogRs92e1SoQ33deY7wuqxlBtUESVtP/NijaX22q/Ba4zi8hNLXMyq2LZuW/cTm9kKNzQ 18Jlwt5hb3Dbg/4CjqISjZwen4HEIp6L34TdYvJJIjH73GkPW0IdliWg==; From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH v5 6/7] arm64: dts: ti: k3-am65-main: Add VMAP registers to PCI root complexes Date: Sun, 8 Sep 2024 19:32:32 +0200 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Rewrap the long lines at this chance. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am65-main.dtsi index 2582dad68dff..08a11ab38fbd 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -895,8 +895,13 @@ main_gpio1: gpio@601000 { =20 pcie0_rc: pcie@5500000 { compatible =3D "ti,am654-pcie-rc"; - reg =3D <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x1= 0000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; - reg-names =3D "app", "dbics", "config", "atu"; + reg =3D <0x0 0x5500000 0x0 0x1000>, + <0x0 0x5501000 0x0 0x1000>, + <0x0 0x10000000 0x0 0x2000>, + <0x0 0x5506000 0x0 0x1000>, + <0x0 0x2900000 0x0 0x1000>, + <0x0 0x2908000 0x0 0x1000>; + reg-names =3D "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains =3D <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <3>; #size-cells =3D <2>; @@ -916,8 +921,13 @@ pcie0_rc: pcie@5500000 { =20 pcie1_rc: pcie@5600000 { compatible =3D "ti,am654-pcie-rc"; - reg =3D <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x1= 8000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; - reg-names =3D "app", "dbics", "config", "atu"; + reg =3D <0x0 0x5600000 0x0 0x1000>, + <0x0 0x5601000 0x0 0x1000>, + <0x0 0x18000000 0x0 0x2000>, + <0x0 0x5606000 0x0 0x1000>, + <0x0 0x2910000 0x0 0x1000>, + <0x0 0x2918000 0x0 0x1000>; + reg-names =3D "app", "dbics", "config", "atu", "vmap_lp", "vmap_hp"; power-domains =3D <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; #address-cells =3D <3>; #size-cells =3D <2>; --=20 2.43.0 From nobody Sat Nov 30 16:31:47 2024 Received: from mta-64-226.siemens.flowmailer.net (mta-64-226.siemens.flowmailer.net [185.136.64.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CE72176FAB for ; Sun, 8 Sep 2024 17:32:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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From: Jan Kiszka To: Nishanth Menon , Santosh Shilimkar , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Siddharth Vadapalli , Bao Cheng Su , Hua Qian Li , Diogo Ivo Subject: [PATCH v5 7/7] arm64: dts: ti: iot2050: Add overlay for DMA isolation for devices behind PCI RC Date: Sun, 8 Sep 2024 19:32:33 +0200 Message-ID: In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Reserve a 64M memory region and ensure that all PCI devices do their DMA only inside that region. This is configured via a restricted-dma-pool and enforced with the help of the first PVU. Applying this isolation is not totally free in terms of overhead and memory consumption. It makes only sense for variants that support secure booting, and generally only when this is actually enable. Therefore model it as overlay that can be activated on demand. The firmware will take care of this via DT fixup during boot and will also provide a way to adjust the pool size. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/Makefile | 5 +++ ...am6548-iot2050-advanced-dma-isolation.dtso | 33 +++++++++++++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-i= solation.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index bcd392c3206e..b6ee943be8c6 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -74,8 +74,10 @@ k3-am654-gp-evm-dtbs :=3D k3-am654-base-board.dtb \ k3-am654-evm-dtbs :=3D k3-am654-base-board.dtb k3-am654-icssg2.dtbo k3-am654-idk-dtbs :=3D k3-am654-evm.dtb k3-am654-idk.dtbo k3-am654-pcie-us= b2.dtbo k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie-dtbs :=3D k3-am6548-iot2050-a= dvanced-m2.dtb \ + k3-am6548-iot2050-advanced-dma-isolation.dtbo \ k3-am6548-iot2050-advanced-m2-bkey-ekey-pcie.dtbo k3-am6548-iot2050-advanced-m2-bkey-usb3-dtbs :=3D k3-am6548-iot2050-advanc= ed-m2.dtb \ + k3-am6548-iot2050-advanced-dma-isolation.dtbo \ k3-am6548-iot2050-advanced-m2-bkey-usb3.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am6528-iot2050-basic-pg2.dtb @@ -240,7 +242,10 @@ DTC_FLAGS_k3-am62p5-sk +=3D -@ DTC_FLAGS_k3-am642-evm +=3D -@ DTC_FLAGS_k3-am642-phyboard-electra-rdk +=3D -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl +=3D -@ +DTC_FLAGS_k3-am6548-iot2050-advanced +=3D -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 +=3D -@ +DTC_FLAGS_k3-am6548-iot2050-advanced-pg2 +=3D -@ +DTC_FLAGS_k3-am6548-iot2050-advanced-sm +=3D -@ DTC_FLAGS_k3-am68-sk-base-board +=3D -@ DTC_FLAGS_k3-am69-sk +=3D -@ DTC_FLAGS_k3-j721e-common-proc-board +=3D -@ diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolatio= n.dtso b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dt= so new file mode 100644 index 000000000000..dfd75d2dc245 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-dma-isolation.dtso @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * IOT2050, overlay for isolating DMA requests via PVU + * Copyright (c) Siemens AG, 2024 + * + * Authors: + * Jan Kiszka + */ + +/dts-v1/; +/plugin/; + +&{/reserved-memory} { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pci_restricted_dma_region: restricted-dma@c0000000 { + compatible =3D "restricted-dma-pool"; + reg =3D <0 0xc0000000 0 0x4000000>; + }; +}; + +&pcie0_rc { + memory-region =3D <&pci_restricted_dma_region>; +}; + +&pcie1_rc { + memory-region =3D <&pci_restricted_dma_region>; +}; + +&ti_pvu0 { + status =3D "okay"; +}; --=20 2.43.0