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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:01.0269 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 664199a3-c850-45f2-7e5f-08dccd2fff66 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8901 Content-Type: text/plain; charset="utf-8" Users can create as many monitor groups as RMIDs supported by the hardware. However, bandwidth monitoring feature on AMD system only guarantees that RMIDs currently assigned to a processor will be tracked by hardware. The counters of any other RMIDs which are no longer being tracked will be reset to zero. The MBM event counters return "Unavailable" for the RMIDs that are not tracked by hardware. So, there can be only limited number of groups that can give guaranteed monitoring numbers. With ever changing configurations there is no way to definitely know which of these groups are being tracked for certain point of time. Users do not have the option to monitor a group or set of groups for certain period of time without worrying about RMID being reset in between. The ABMC feature provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. The assigned RMID will be tracked by the hardware until the user unassigns it manually. There is no need to worry about counters being reset during this period. Additionally, the user can specify a bitmask identifying the specific bandwidth types from the given source to track with the counte= r. Without ABMC enabled, monitoring will work in current mode without assignment option. Linux resctrl subsystem provides the interface to count maximum of two memory bandwidth events per group, from a combination of available total and local events. Keeping the current interface, users can enable a maximum of 2 ABMC counters per group. User will also have the option to enable only one counter to the group. If the system runs out of assignable ABMC counters, kernel will display an error. Users need to disable an already enabled counter to make space for new assignments. The feature can be detected via CPUID_Fn80000020_EBX_x00 bit 5. Bits Description 5 ABMC (Assignable Bandwidth Monitoring Counters) The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- Note: Checkpatch checks/warnings are ignored to maintain coding style. v7: Removed "" from feature flags. Not required anymore. https://lore.kernel.org/lkml/20240817145058.GCZsC40neU4wkPXeVR@fat_crat= e.local/ v6: Added Reinette's Reviewed-by. Moved the Checkpatch note below ---. v5: Minor rebase change and subject line update. v4: Changes because of rebase. Feature word 21 has few more additions now. Changed the text to "tracked by hardware" instead of active. v3: Change because of rebase. Actual patch did not change. v2: Added dependency on X86_FEATURE_BMEC. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 3 +++ arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dd4682857c12..4c514cb245ff 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -473,6 +473,7 @@ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enable= d */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch hi= story at vmexit using SW loop */ #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_ABMC (21*32 + 6) /* Assignable Bandwidth Monitoring C= ounters */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 8bd84114c2d9..7e4d63b381d6 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,9 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_TOTAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_BMEC }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index c84c30188fdf..87f63e6b2994 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2062.outbound.protection.outlook.com [40.107.95.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7DFE17BECA; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:09.6363 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e22763fd-2471-4c72-2f0a-08dccd300488 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7741 Content-Type: text/plain; charset="utf-8" Add the command line option to enable or disable the new resctrl feature ABMC (Assignable Bandwidth Monitoring Counters). Signed-off-by: Babu Moger --- v7: No changes v6: No changes v5: No changes v4: No changes v3: No changes v2: No changes --- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/arch/x86/resctrl.rst | 1 + arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 09126bb8cc9f..12cc0a26c82a 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5604,7 +5604,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, abmc. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index a824affd741d..30586728a4cd 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -26,6 +26,7 @@ MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_= mbm_local" MBA (Memory Bandwidth Allocation) "mba" SMBA (Slow Memory Bandwidth Allocation) "" BMEC (Bandwidth Monitoring Event Configuration) "" +ABMC (Assignable Bandwidth Monitoring Counters) "" =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 Historically, new features were made visible by default in /proc/cpuinfo. = This diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 8591d53c144b..668148ceda0b 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -809,6 +809,7 @@ enum { RDT_FLAG_MBA, RDT_FLAG_SMBA, RDT_FLAG_BMEC, + RDT_FLAG_ABMC, }; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:16.7217 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 296e8ddd-7165-4307-18e5-08dccd3008c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8356 Content-Type: text/plain; charset="utf-8" The cache allocation and memory bandwidth allocation feature properties are consolidated into struct resctrl_cache and struct resctrl_membw respectively. In preparation for more monitoring properties that will clobber the existing resource struct more, re-organize the monitoring specific properties to also be in a separate structure. Suggested-by: Reinette Chatre Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v7: Added kernel doc for data structure. Minor text update. v6: Update commit message and update kernel doc for rdt_resource. v5: Commit message update. Also changes related to data structure updates does to SNC support. v4: New patch. --- arch/x86/kernel/cpu/resctrl/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/monitor.c | 18 +++++++++--------- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 8 ++++---- include/linux/resctrl.h | 16 ++++++++++++---- 4 files changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 668148ceda0b..73bfc8d7a438 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -124,7 +124,7 @@ u32 resctrl_arch_system_num_rmid_idx(void) struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; =20 /* RMID are independent numbers for x86. num_rmid_idx =3D=3D num_rmid */ - return r->num_rmid; + return r->mon.num_rmid; } =20 /* @@ -625,7 +625,7 @@ static void domain_add_cpu_mon(int cpu, struct rdt_reso= urce *r) =20 arch_mon_domain_online(r, d); =20 - if (arch_domain_mbm_alloc(r->num_rmid, hw_dom)) { + if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { mon_domain_free(hw_dom); return; } diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 851b561850e0..795fe91a8feb 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -222,7 +222,7 @@ static int logical_rmid_to_physical_rmid(int cpu, int l= rmid) if (snc_nodes_per_l3_cache =3D=3D 1) return lrmid; =20 - return lrmid + (cpu_to_node(cpu) % snc_nodes_per_l3_cache) * r->num_rmid; + return lrmid + (cpu_to_node(cpu) % snc_nodes_per_l3_cache) * r->mon.num_r= mid; } =20 static int __rmid_read_phys(u32 prmid, enum resctrl_event_id eventid, u64 = *val) @@ -297,11 +297,11 @@ void resctrl_arch_reset_rmid_all(struct rdt_resource = *r, struct rdt_mon_domain * =20 if (is_mbm_total_enabled()) memset(hw_dom->arch_mbm_total, 0, - sizeof(*hw_dom->arch_mbm_total) * r->num_rmid); + sizeof(*hw_dom->arch_mbm_total) * r->mon.num_rmid); =20 if (is_mbm_local_enabled()) memset(hw_dom->arch_mbm_local, 0, - sizeof(*hw_dom->arch_mbm_local) * r->num_rmid); + sizeof(*hw_dom->arch_mbm_local) * r->mon.num_rmid); } =20 static u64 mbm_overflow_count(u64 prev_msr, u64 cur_msr, unsigned int widt= h) @@ -1083,14 +1083,14 @@ static struct mon_evt mbm_local_event =3D { */ static void l3_mon_evt_init(struct rdt_resource *r) { - INIT_LIST_HEAD(&r->evt_list); + INIT_LIST_HEAD(&r->mon.evt_list); =20 if (is_llc_occupancy_enabled()) - list_add_tail(&llc_occupancy_event.list, &r->evt_list); + list_add_tail(&llc_occupancy_event.list, &r->mon.evt_list); if (is_mbm_total_enabled()) - list_add_tail(&mbm_total_event.list, &r->evt_list); + list_add_tail(&mbm_total_event.list, &r->mon.evt_list); if (is_mbm_local_enabled()) - list_add_tail(&mbm_local_event.list, &r->evt_list); + list_add_tail(&mbm_local_event.list, &r->mon.evt_list); } =20 /* @@ -1186,7 +1186,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) =20 resctrl_rmid_realloc_limit =3D boot_cpu_data.x86_cache_size * 1024; hw_res->mon_scale =3D boot_cpu_data.x86_cache_occ_scale / snc_nodes_per_l= 3_cache; - r->num_rmid =3D (boot_cpu_data.x86_cache_max_rmid + 1) / snc_nodes_per_l3= _cache; + r->mon.num_rmid =3D (boot_cpu_data.x86_cache_max_rmid + 1) / snc_nodes_pe= r_l3_cache; hw_res->mbm_width =3D MBM_CNTR_WIDTH_BASE; =20 if (mbm_offset > 0 && mbm_offset <=3D MBM_CNTR_WIDTH_OFFSET_MAX) @@ -1201,7 +1201,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) * * For a 35MB LLC and 56 RMIDs, this is ~1.8% of the LLC. */ - threshold =3D resctrl_rmid_realloc_limit / r->num_rmid; + threshold =3D resctrl_rmid_realloc_limit / r->mon.num_rmid; =20 /* * Because num_rmid may not be a power of two, round the value diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index d7163b764c62..f9f3b5db1987 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1097,7 +1097,7 @@ static int rdt_num_rmids_show(struct kernfs_open_file= *of, { struct rdt_resource *r =3D of->kn->parent->priv; =20 - seq_printf(seq, "%d\n", r->num_rmid); + seq_printf(seq, "%d\n", r->mon.num_rmid); =20 return 0; } @@ -1108,7 +1108,7 @@ static int rdt_mon_features_show(struct kernfs_open_f= ile *of, struct rdt_resource *r =3D of->kn->parent->priv; struct mon_evt *mevt; =20 - list_for_each_entry(mevt, &r->evt_list, list) { + list_for_each_entry(mevt, &r->mon.evt_list, list) { seq_printf(seq, "%s\n", mevt->name); if (mevt->configurable) seq_printf(seq, "%s_config\n", mevt->name); @@ -3057,13 +3057,13 @@ static int mon_add_all_files(struct kernfs_node *kn= , struct rdt_mon_domain *d, struct mon_evt *mevt; int ret; =20 - if (WARN_ON(list_empty(&r->evt_list))) + if (WARN_ON(list_empty(&r->mon.evt_list))) return -EPERM; =20 priv.u.rid =3D r->rid; priv.u.domid =3D do_sum ? d->ci->id : d->hdr.id; priv.u.sum =3D do_sum; - list_for_each_entry(mevt, &r->evt_list, list) { + list_for_each_entry(mevt, &r->mon.evt_list, list) { priv.u.evtid =3D mevt->evtid; ret =3D mon_addfile(kn, mevt->name, priv.priv); if (ret) diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index d94abba1c716..3c2307c7c106 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -182,16 +182,26 @@ enum resctrl_scope { RESCTRL_L3_NODE, }; =20 +/** + * struct resctrl_mon - Monitoring related data of a resctrl resource + * @num_rmid: Number of RMIDs available + * @evt_list: List of monitoring events + */ +struct resctrl_mon { + int num_rmid; + struct list_head evt_list; +}; + /** * struct rdt_resource - attributes of a resctrl resource * @rid: The index of the resource * @alloc_capable: Is allocation available on this machine * @mon_capable: Is monitor feature available on this machine - * @num_rmid: Number of RMIDs available * @ctrl_scope: Scope of this resource for control functions * @mon_scope: Scope of this resource for monitor functions * @cache: Cache allocation related data * @membw: If the component has bandwidth controls, their properties. + * @mon: Monitoring related data. * @ctrl_domains: RCU list of all control domains for this resource * @mon_domains: RCU list of all monitor domains for this resource * @name: Name to use in "schemata" file. @@ -199,7 +209,6 @@ enum resctrl_scope { * @default_ctrl: Specifies default cache cbm or memory B/W percent. * @format_str: Per resource format string to show domain value * @parse_ctrlval: Per resource function pointer to parse control values - * @evt_list: List of monitoring events * @fflags: flags to choose base and info files * @cdp_capable: Is the CDP feature available on this resource */ @@ -207,11 +216,11 @@ struct rdt_resource { int rid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:24.0728 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bed4cd62-e35f-4533-06d7-08dccd300d23 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7844 Content-Type: text/plain; charset="utf-8" ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5. Bits Description 15:0 MAX_ABMC Maximum Supported Assignable Bandwidth Monitoring Counter ID + 1 The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Detect the feature and number of assignable monitoring counters supported. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v7: Removed WARN_ON for num_mbm_cntrs. Decided to dynamically allocate the bitmap. WARN_ON is not required anymore. Removed redundant comments. v6: Commit message update. Renamed abmc_capable to mbm_cntr_assignable. v5: Name change num_cntrs to num_mbm_cntrs. Moved abmc_capable to resctrl_mon. v4: Removed resctrl_arch_has_abmc(). Added all the code inline. We dont need to separate this as arch code. v3: Removed changes related to mon_features. Moved rdt_cpu_has to core.c and added new function resctrl_arch_has_abm= c. Also moved the fields mbm_assign_capable and mbm_assign_cntrs to rdt_resource. (James) v2: Changed the field name to mbm_assign_capable from abmc_capable. --- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ include/linux/resctrl.h | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 795fe91a8feb..6a792f06f5ce 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1229,6 +1229,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource= *r) mbm_local_event.configurable =3D true; mbm_config_rftype_init("mbm_local_bytes_config"); } + + if (rdt_cpu_has(X86_FEATURE_ABMC)) { + r->mon.mbm_cntr_assignable =3D true; + cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); + r->mon.num_mbm_cntrs =3D (ebx & 0xFFFF) + 1; + } } =20 l3_mon_evt_init(r); diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 3c2307c7c106..511cfce8fc21 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -185,10 +185,14 @@ enum resctrl_scope { /** * struct resctrl_mon - Monitoring related data of a resctrl resource * @num_rmid: Number of RMIDs available + * @num_mbm_cntrs: Number of assignable monitoring counters + * @mbm_cntr_assignable:Is system capable of supporting monitor assignment? * @evt_list: List of monitoring events */ struct resctrl_mon { int num_rmid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:31.7259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b7665636-b335-4c54-caa5-08dccd3011b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5771 Content-Type: text/plain; charset="utf-8" thread_throttle_mode_init() and mbm_config_rftype_init() both initialize fflags for resctrl files. Adding new files will involve adding another function to initialize the fflags. This can be simplified by adding a new function resctrl_file_fflags_init() and passing the file name and flags to be initialized. Consolidate fflags initialization into resctrl_file_fflags_init() and remove thread_throttle_mode_init() and mbm_config_rftype_init(). Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v7: No changes. v6: Added Reviewed-by from Reinette. v5: Commit message update. v4: Commit message update. v3: New patch to display ABMC capability. --- arch/x86/kernel/cpu/resctrl/core.c | 4 +++- arch/x86/kernel/cpu/resctrl/internal.h | 4 ++-- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++-- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 16 +++------------- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 73bfc8d7a438..186d8047578b 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -234,7 +234,9 @@ static bool __get_mem_config_intel(struct rdt_resource = *r) r->membw.throttle_mode =3D THREAD_THROTTLE_PER_THREAD; else r->membw.throttle_mode =3D THREAD_THROTTLE_MAX; - thread_throttle_mode_init(); + + resctrl_file_fflags_init("thread_throttle_mode", + RFTYPE_CTRL_INFO | RFTYPE_RES_MB); =20 r->alloc_capable =3D true; =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 955999aecfca..2bd207624eec 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -647,8 +647,8 @@ void cqm_handle_limbo(struct work_struct *work); bool has_busy_rmid(struct rdt_mon_domain *d); void __check_limbo(struct rdt_mon_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); -void __init thread_throttle_mode_init(void); -void __init mbm_config_rftype_init(const char *config); +void __init resctrl_file_fflags_init(const char *config, + unsigned long fflags); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 6a792f06f5ce..71fab31e20da 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1223,11 +1223,13 @@ int __init rdt_get_mon_l3_config(struct rdt_resourc= e *r) =20 if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; - mbm_config_rftype_init("mbm_total_bytes_config"); + resctrl_file_fflags_init("mbm_total_bytes_config", + RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { mbm_local_event.configurable =3D true; - mbm_config_rftype_init("mbm_local_bytes_config"); + resctrl_file_fflags_init("mbm_local_bytes_config", + RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } =20 if (rdt_cpu_has(X86_FEATURE_ABMC)) { diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f9f3b5db1987..7e76f8d839fc 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2020,24 +2020,14 @@ static struct rftype *rdtgroup_get_rftype_by_name(c= onst char *name) return NULL; } =20 -void __init thread_throttle_mode_init(void) -{ - struct rftype *rft; - - rft =3D rdtgroup_get_rftype_by_name("thread_throttle_mode"); - if (!rft) - return; - - rft->fflags =3D RFTYPE_CTRL_INFO | RFTYPE_RES_MB; -} - -void __init mbm_config_rftype_init(const char *config) +void __init resctrl_file_fflags_init(const char *config, + unsigned long fflags) { struct rftype *rft; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:40.6134 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a19321d0-40d0-4e3a-7583-08dccd301708 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4088 Content-Type: text/plain; charset="utf-8" Add the functionality to enable/disable AMD ABMC feature. AMD ABMC feature is enabled by setting enabled bit(0) in MSR L3_QOS_EXT_CFG. When the state of ABMC is changed, the MSR needs to be updated on all the logical processors in the QOS Domain. Hardware counters will reset when ABMC state is changed. Reset the architectural state maintained by resctrl so that reading of a hardware counter is not considered as an overflow in next update. The ABMC feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v7: Renamed the function resctrl_arch_get_abmc_enabled() to resctrl_arch_mbm_cntr_assign_enabled(= ). Merged resctrl_arch_mbm_cntr_assign_disable, resctrl_arch_mbm_cntr_assign= _disable and renamed to resctrl_arch_mbm_cntr_assign_set(). Moved the function definition to linux/resctrl.h. Passed the struct rdt_resource to these functions. Removed resctrl_arch_reset_rmid_all() from arch code. This will be done from the caller. v6: Renamed abmc_enabled to mbm_cntr_assign_enabled. Used msr_set_bit and msr_clear_bit for msr updates. Renamed resctrl_arch_abmc_enable() to resctrl_arch_mbm_cntr_assign_enab= le(). Renamed resctrl_arch_abmc_disable() to resctrl_arch_mbm_cntr_assign_dis= able(). Made _resctrl_abmc_enable to return void. v5: Renamed resctrl_abmc_enable to resctrl_arch_abmc_enable. Renamed resctrl_abmc_disable to resctrl_arch_abmc_disable. Introduced resctrl_arch_get_abmc_enabled to get abmc state from non-arch code. Renamed resctrl_abmc_set_all to _resctrl_abmc_enable(). Modified commit log to make it clear about AMD ABMC feature. v3: No changes. v2: Few text changes in commit message. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/core.c | 5 ++++ arch/x86/kernel/cpu/resctrl/internal.h | 5 ++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 35 ++++++++++++++++++++++++++ include/linux/resctrl.h | 3 +++ 5 files changed, 49 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 82c6a4d350e0..d86469bf5d41 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1182,6 +1182,7 @@ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff =20 /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 186d8047578b..49d147e2e4e5 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -405,6 +405,11 @@ void rdt_ctrl_update(void *arg) hw_res->msr_update(m); } =20 +bool resctrl_arch_mbm_cntr_assign_enabled(struct rdt_resource *r) +{ + return resctrl_to_arch_res(r)->mbm_cntr_assign_enabled; +} + /* * rdt_find_domain - Search for a domain id in a resource domain list. * diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 2bd207624eec..a45ae410274c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +/* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ +#define ABMC_ENABLE_BIT 0 + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -477,6 +480,7 @@ struct rdt_parse_data { * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource + * @mbm_cntr_assign_enabled: ABMC feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -491,6 +495,7 @@ struct rdt_hw_resource { unsigned int mbm_width; unsigned int mbm_cfg_mask; bool cdp_enabled; + bool mbm_cntr_assign_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 7e76f8d839fc..0178555bf3f6 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2402,6 +2402,41 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_le= vel l, bool enable) return 0; } =20 +/* + * Update L3_QOS_EXT_CFG MSR on all the CPUs associated with the resource. + */ +static void resctrl_abmc_set_one_amd(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); +} + +static void _resctrl_abmc_enable(struct rdt_resource *r, bool enable) +{ + struct rdt_mon_domain *d; + + list_for_each_entry(d, &r->mon_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, + resctrl_abmc_set_one_amd, &enable, 1); +} + +int resctrl_arch_mbm_cntr_assign_set(struct rdt_resource *r, bool enable) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + if (r->mon.mbm_cntr_assignable && + hw_res->mbm_cntr_assign_enabled !=3D enable) { + _resctrl_abmc_enable(r, enable); + hw_res->mbm_cntr_assign_enabled =3D enable; + } + + return 0; +} + /* * We don't allow rdtgroup directories to be created anywhere * except the root directory. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:47.9605 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cfb99b19-d0ef-4396-fd7b-08dccd301b5f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8709 Content-Type: text/plain; charset="utf-8" Introduce the interface file "mbm_assign_mode" to list monitor modes supported. The "mbm_cntr_assign" mode provides the option to assign a hardware counter to an RMID and monitor the bandwidth as long as it is assigned. On AMD systems "mbm_cntr_assign" is backed by the ABMC (Assignable Bandwidth Monitoring Counters) hardware feature. "mbm_cntr_assign" mode is enabled by default when supported. The "default" mode is the existing monitoring mode that works without the explicit counter assignment, instead relying on dynamic counter assignment by hardware that may result in hardware not dedicating a counter resulting in monitoring data reads returning "Unavailable". Provide an interface to display the monitor mode on the system. $cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_cntr_assign] default Switching the mbm_assign_mode will reset all the MBM counters of all resctrl groups. Signed-off-by: Babu Moger --- v7: Updated the descriptions/commit log in resctrl.rst to generic text. Thanks to James and Reinette. Rename mbm_mode to mbm_assign_mode. Introduced mutex lock in rdtgroup_mbm_mode_show(). v6: Added documentation for mbm_cntr_assign and legacy mode. Moved mbm_mode fflags initialization to static initialization. v5: Changed interface name to mbm_mode. It will be always available even if ABMC feature is not supported. Added description in resctrl.rst about ABMC mode. Fixed display abmc and legacy consistantly. v4: Fixed the checks for legacy and abmc mode. Default it ABMC. v3: New patch to display ABMC capability. --- Documentation/arch/x86/resctrl.rst | 33 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 31 ++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 30586728a4cd..a7b17ad8acb9 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -257,6 +257,39 @@ with the following files: # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=3D0x30;1=3D0x30;3=3D0x15;4=3D0x15 =20 +"mbm_assign_mode": + Reports the list of monitoring modes supported. The enclosed brackets + indicate which feature is enabled. + :: + + cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + [mbm_cntr_assign] + default + + "mbm_cntr_assign": + + In mbm_cntr_assign mode user-space is able to specify which control + or monitor groups in resctrl should have a hardware counter assigned + using the 'mbm_control' file. The number of hardware counters available + is described in the 'num_mbm_cntrs' file. Changing to this mode will + cause all counters on a resource to reset. + + The feature is needed on platforms which support more control and monitor + groups than hardware counters, meaning 'unassigned' control or monitor + groups will report 'Unavailable' or not count all the traffic in an + unpredictable way. + + AMD Platforms with ABMC (Assignable Bandwidth Monitoring Counters) feature + enable this mode by default so that counters remain assigned even when the + corresponding RMID is not in use by any processor. + + "default": + + By default resctrl assumes each control and monitor group has a hardware = counter. + Hardware without this property will still allow more control or monitor g= roups + than 'num_mbm_cntrs' to be created. Reading the mbm files may report 'Una= vailable' + if there is no hardware resource assigned. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 0178555bf3f6..dbc8c5e63213 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -845,6 +845,30 @@ static int rdtgroup_rmid_show(struct kernfs_open_file = *of, return ret; } =20 +static int rdtgroup_mbm_assign_mode_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + mutex_lock(&rdtgroup_mutex); + + if (r->mon.mbm_cntr_assignable) { + if (resctrl_arch_mbm_cntr_assign_enabled(r)) { + seq_puts(s, "[mbm_cntr_assign]\n"); + seq_puts(s, "default\n"); + } else { + seq_puts(s, "mbm_cntr_assign\n"); + seq_puts(s, "[default]\n"); + } + } else { + seq_puts(s, "[default]\n"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:22:54.5822 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f5607f59-fe1c-4e1c-6201-08dccd301f52 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8076 Content-Type: text/plain; charset="utf-8" The mbm_assign_cntr mode provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as the counter is assigned. Number of assignments depend on number of monitoring counters available. Provide the interface to display the number of monitoring counters supported. Signed-off-by: Babu Moger --- v7: Minor commit log text changes. v6: No changes. v5: Changed the display name from num_cntrs to num_mbm_cntrs. Updated the commit message. Moved the patch after mbm_mode is introduced. v4: Changed the counter name to num_cntrs. And few text changes. v3: Changed the field name to mbm_assign_cntrs. v2: Changed the field name to mbm_assignable_counters from abmc_counte --- Documentation/arch/x86/resctrl.rst | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index a7b17ad8acb9..3e9302971faf 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -290,6 +290,9 @@ with the following files: than 'num_mbm_cntrs' to be created. Reading the mbm files may report 'Una= vailable' if there is no hardware resource assigned. =20 +"num_mbm_cntrs": + The number of monitoring counters available for assignment. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 71fab31e20da..e3e71843401a 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1236,6 +1236,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) r->mon.mbm_cntr_assignable =3D true; cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); r->mon.num_mbm_cntrs =3D (ebx & 0xFFFF) + 1; + resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index dbc8c5e63213..ba737890d5c2 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -869,6 +869,16 @@ static int rdtgroup_mbm_assign_mode_show(struct kernfs= _open_file *of, return 0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:03.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8d0fc62-9319-48bb-3749-08dccd302472 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7176 Content-Type: text/plain; charset="utf-8" Hardware provides a set of counters when mbm_cntr_assignable feature is supported. These counters are used for assigning the events in resctrl a group when the feature is enabled. The kernel must manage and track the number of available counters. Introduce mbm_cntr_free_map bitmap to track available counters and set of routines to allocate and free the counters. Signed-off-by: Babu Moger --- v7: Removed the static allocation and now allocating bitmap mbm_cntr_free_m= ap dynamically. Passed the struct rdt_resource mbm_cntr_alloc and mbm_cntr_free. Removed the reference of ABMC and changed it mbm_cntr_assign. Few other text changes. v6: Removed the variable mbm_cntrs_free_map_len. This is not required. Removed the call mbm_cntrs_init() in arch code. This needs to be done at higher level. Used DECLARE_BITMAP to initialize mbm_cntrs_free_map. Moved all the counter interfaces mbm_cntr_alloc() and mbm_cntr_free() in here as part of separating arch and fs bits. v5: Updated the comments and commit log. Few renames num_cntrs_free_map -> mbm_cntrs_free_map num_cntrs_init -> mbm_cntrs_init Added initialization in rdt_get_tree because the default ABMC enablement happens during the init. v4: Changed the name to num_cntrs where applicable. Used bitmap apis. Added more comments for the globals. v3: Changed the bitmap name to assign_cntrs_free_map. Removed abmc from the name. v2: Changed the bitmap name to assignable_counter_free_map from abmc_counter_free_map. --- arch/x86/kernel/cpu/resctrl/core.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 4 +++- arch/x86/kernel/cpu/resctrl/monitor.c | 31 +++++++++++++++++++++++++- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 19 ++++++++++++++++ include/linux/resctrl.h | 2 ++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 49d147e2e4e5..00ad00258df2 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1140,7 +1140,7 @@ static void __exit resctrl_exit(void) rdtgroup_exit(); =20 if (r->mon_capable) - rdt_put_mon_l3_config(); + rdt_put_mon_l3_config(r); } =20 __exitcall(resctrl_exit); diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index a45ae410274c..99f9103a35ba 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -633,7 +633,7 @@ void closid_free(int closid); int alloc_rmid(u32 closid); void free_rmid(u32 closid, u32 rmid); int rdt_get_mon_l3_config(struct rdt_resource *r); -void __exit rdt_put_mon_l3_config(void); +void __exit rdt_put_mon_l3_config(struct rdt_resource *r); bool __init rdt_cpu_has(int flag); void mon_event_count(void *info); int rdtgroup_mondata_show(struct seq_file *m, void *arg); @@ -654,6 +654,8 @@ void __check_limbo(struct rdt_mon_domain *d, bool force= _free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init resctrl_file_fflags_init(const char *config, unsigned long fflags); +int mbm_cntr_alloc(struct rdt_resource *r); +void mbm_cntr_free(struct rdt_resource *r, u32 cntr_id); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index e3e71843401a..f98cc5b9bebc 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1175,6 +1175,30 @@ static __init int snc_get_config(void) return ret; } =20 +/* + * Counter bitmap for tracking the available counters. + * 'mbm_cntr_assign' mode provides set of hardware counters for assigning + * RMID, event pair. Each RMID and event pair takes one hardware counter. + * Kernel needs to keep track of the number of available counters. + */ +static int mbm_cntrs_init(struct rdt_resource *r) +{ + if (r->mon.mbm_cntr_assignable) { + r->mon.mbm_cntr_free_map =3D bitmap_zalloc(r->mon.num_mbm_cntrs, + GFP_KERNEL); + if (!r->mon.mbm_cntr_free_map) + return -ENOMEM; + bitmap_fill(r->mon.mbm_cntr_free_map, r->mon.num_mbm_cntrs); + } + return 0; +} + +static void __exit mbm_cntrs_exit(struct rdt_resource *r) +{ + if (r->mon.mbm_cntr_assignable) + bitmap_free(r->mon.mbm_cntr_free_map); +} + int __init rdt_get_mon_l3_config(struct rdt_resource *r) { unsigned int mbm_offset =3D boot_cpu_data.x86_cache_mbm_width_offset; @@ -1240,6 +1264,10 @@ int __init rdt_get_mon_l3_config(struct rdt_resource= *r) } } =20 + ret =3D mbm_cntrs_init(r); + if (ret) + return ret; + l3_mon_evt_init(r); =20 r->mon_capable =3D true; @@ -1247,9 +1275,10 @@ int __init rdt_get_mon_l3_config(struct rdt_resource= *r) return 0; } =20 -void __exit rdt_put_mon_l3_config(void) +void __exit rdt_put_mon_l3_config(struct rdt_resource *r) { dom_data_exit(); + mbm_cntrs_exit(r); } =20 void __init intel_rdt_mbm_apply_quirk(void) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index ba737890d5c2..a51992984832 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -185,6 +185,25 @@ bool closid_allocated(unsigned int closid) return !test_bit(closid, &closid_free_map); } =20 +int mbm_cntr_alloc(struct rdt_resource *r) +{ + int cntr_id; + + cntr_id =3D find_first_bit(r->mon.mbm_cntr_free_map, + r->mon.num_mbm_cntrs); + if (cntr_id >=3D r->mon.num_mbm_cntrs) + return -ENOSPC; + + __clear_bit(cntr_id, r->mon.mbm_cntr_free_map); + + return cntr_id; +} + +void mbm_cntr_free(struct rdt_resource *r, u32 cntr_id) +{ + __set_bit(cntr_id, r->mon.mbm_cntr_free_map); +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index f11d6fdfd977..aab22ff8e0c1 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -187,12 +187,14 @@ enum resctrl_scope { * @num_rmid: Number of RMIDs available * @num_mbm_cntrs: Number of assignable monitoring counters * @mbm_cntr_assignable:Is system capable of supporting monitor assignment? + * @mbm_cntr_free_map: bitmap of number of assignable MBM counters * @evt_list: List of monitoring events */ struct resctrl_mon { int num_rmid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:09.8486 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 426bdc02-f98a-4e3e-db89-08dccd30286b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5810 Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured to track specific events. The event configuration is domain specific. ABMC (Assignable Bandwidth Monitoring Counters) feature needs event configuration information to assign hardware counter to an RMID. Event configurations are not stored in resctrl but instead always read from or written to hardware directly when prompted by user space. Read the event configuration from the hardware during the domain initialization. Save the configuration value in rdt_hw_mon_domain, so it can be used for counter assignment. Signed-off-by: Babu Moger --- v7: Fixed initializing INVALID_CONFIG_VALUE to mbm_local_cfg in case of err= or. v6: Renamed resctrl_arch_mbm_evt_config -> resctrl_mbm_evt_config_init Initialized value to INVALID_CONFIG_VALUE if it is not configurable. Minor commit message update. v5: Exported mon_event_config_index_get. Renamed arch_domain_mbm_evt_config to resctrl_arch_mbm_evt_config. v4: Read the configuration information from the hardware to initialize. Added few commit messages. Fixed the tab spaces. v3: Minor changes related to rebase in mbm_config_write_domain. v2: No changes. --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++ arch/x86/kernel/cpu/resctrl/monitor.c | 26 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 +--- 4 files changed, 38 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 00ad00258df2..2a4be004a2df 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -632,6 +632,8 @@ static void domain_add_cpu_mon(int cpu, struct rdt_reso= urce *r) =20 arch_mon_domain_online(r, d); =20 + resctrl_mbm_evt_config_init(hw_dom); + if (arch_domain_mbm_alloc(r->mon.num_rmid, hw_dom)) { mon_domain_free(hw_dom); return; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 99f9103a35ba..6107101f2d8a 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +#define INVALID_CONFIG_VALUE U32_MAX +#define INVALID_CONFIG_INDEX UINT_MAX + /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ #define ABMC_ENABLE_BIT 0 =20 @@ -401,6 +404,8 @@ struct rdt_hw_ctrl_domain { * @d_resctrl: Properties exposed to the resctrl file system * @arch_mbm_total: arch private state for MBM total bandwidth * @arch_mbm_local: arch private state for MBM local bandwidth + * @mbm_total_cfg: MBM total bandwidth configuration + * @mbm_local_cfg: MBM local bandwidth configuration * * Members of this structure are accessed via helpers that provide abstrac= tion. */ @@ -408,6 +413,8 @@ struct rdt_hw_mon_domain { struct rdt_mon_domain d_resctrl; struct arch_mbm_state *arch_mbm_total; struct arch_mbm_state *arch_mbm_local; + u32 mbm_total_cfg; + u32 mbm_local_cfg; }; =20 static inline struct rdt_hw_ctrl_domain *resctrl_to_arch_ctrl_dom(struct r= dt_ctrl_domain *r) @@ -656,6 +663,8 @@ void __init resctrl_file_fflags_init(const char *config, unsigned long fflags); int mbm_cntr_alloc(struct rdt_resource *r); void mbm_cntr_free(struct rdt_resource *r, u32 cntr_id); +void resctrl_mbm_evt_config_init(struct rdt_hw_mon_domain *hw_dom); +unsigned int mon_event_config_index_get(u32 evtid); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f98cc5b9bebc..09b1d8bb0aa0 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1275,6 +1275,32 @@ int __init rdt_get_mon_l3_config(struct rdt_resource= *r) return 0; } =20 +void resctrl_mbm_evt_config_init(struct rdt_hw_mon_domain *hw_dom) +{ + unsigned int index; + u64 msrval; + + /* + * Read the configuration registers QOS_EVT_CFG_n, where is + * the BMEC event number (EvtID). + */ + if (mbm_total_event.configurable) { + index =3D mon_event_config_index_get(QOS_L3_MBM_TOTAL_EVENT_ID); + rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); + hw_dom->mbm_total_cfg =3D msrval & MAX_EVT_CONFIG_BITS; + } else { + hw_dom->mbm_total_cfg =3D INVALID_CONFIG_VALUE; + } + + if (mbm_local_event.configurable) { + index =3D mon_event_config_index_get(QOS_L3_MBM_LOCAL_EVENT_ID); + rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); + hw_dom->mbm_local_cfg =3D msrval & MAX_EVT_CONFIG_BITS; + } else { + hw_dom->mbm_local_cfg =3D INVALID_CONFIG_VALUE; + } +} + void __exit rdt_put_mon_l3_config(struct rdt_resource *r) { dom_data_exit(); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index a51992984832..299722b3fd90 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1601,8 +1601,6 @@ struct mon_config_info { u32 mon_config; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:17.3800 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4de047dc-fbab-4344-a9da-08dccd302ce6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5800 Content-Type: text/plain; charset="utf-8" The event configuration is domain specific and initialized during domain initialization. The values are stored in struct rdt_hw_mon_domain. It is not required to read the configuration register every time user asks for it. Use the value stored in struct rdt_hw_mon_domain instead. Introduce resctrl_arch_event_config_get() and resctrl_arch_event_config_set() to get/set architecture domain specific mbm_total_cfg/mbm_local_cfg values. Signed-off-by: Babu Moger --- v7: Removed check if (val =3D=3D INVALID_CONFIG_VALUE) as resctrl_arch_even= t_config_get already prints warning. Kept the Event config value definitions as is. v6: Fixed inconstancy with types. Made all the types to u32 for config value. Removed few rdt_last_cmd_puts as it is not necessary. Removed unused config value definitions. Few more updates to commit message. v5: Introduced resctrl_arch_event_config_get and resctrl_arch_event_config_get() based on our discussion. https://lore.kernel.org/lkml/68e861f9-245d-4496-a72e-46fc57d19c62@amd.c= om/ v4: New patch. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 103 ++++++++++++++----------- include/linux/resctrl.h | 4 + 2 files changed, 62 insertions(+), 45 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 299722b3fd90..cc101fbe8683 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1597,10 +1597,57 @@ static int rdtgroup_size_show(struct kernfs_open_fi= le *of, } =20 struct mon_config_info { + struct rdt_mon_domain *d; u32 evtid; u32 mon_config; }; =20 +u32 resctrl_arch_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid) +{ + struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); + + switch (eventid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + return hw_dom->mbm_total_cfg; + case QOS_L3_MBM_LOCAL_EVENT_ID: + return hw_dom->mbm_local_cfg; + } + + /* Never expect to get here */ + WARN_ON_ONCE(1); + + return INVALID_CONFIG_VALUE; +} + +void resctrl_arch_event_config_set(void *info) +{ + struct mon_config_info *mon_info =3D info; + struct rdt_hw_mon_domain *hw_dom; + unsigned int index; + + index =3D mon_event_config_index_get(mon_info->evtid); + if (index =3D=3D INVALID_CONFIG_INDEX) + return; + + wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); + + hw_dom =3D resctrl_to_arch_mon_dom(mon_info->d); + + switch (mon_info->evtid) { + case QOS_L3_OCCUP_EVENT_ID: + break; + case QOS_L3_MBM_TOTAL_EVENT_ID: + hw_dom->mbm_total_cfg =3D mon_info->mon_config; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + hw_dom->mbm_local_cfg =3D mon_info->mon_config; + break; + } +} + /** * mon_event_config_index_get - get the hardware index for the * configurable event @@ -1623,33 +1670,11 @@ unsigned int mon_event_config_index_get(u32 evtid) } } =20 -static void mon_event_config_read(void *info) -{ - struct mon_config_info *mon_info =3D info; - unsigned int index; - u64 msrval; - - index =3D mon_event_config_index_get(mon_info->evtid); - if (index =3D=3D INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); - - /* Report only the valid event configuration bits */ - mon_info->mon_config =3D msrval & MAX_EVT_CONFIG_BITS; -} - -static void mondata_config_read(struct rdt_mon_domain *d, struct mon_confi= g_info *mon_info) -{ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_read, mon_info, = 1); -} - static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32= evtid) { - struct mon_config_info mon_info =3D {0}; struct rdt_mon_domain *dom; bool sep =3D false; + u32 val; =20 cpus_read_lock(); mutex_lock(&rdtgroup_mutex); @@ -1658,11 +1683,8 @@ static int mbm_config_show(struct seq_file *s, struc= t rdt_resource *r, u32 evtid if (sep) seq_puts(s, ";"); =20 - memset(&mon_info, 0, sizeof(struct mon_config_info)); - mon_info.evtid =3D evtid; - mondata_config_read(dom, &mon_info); - - seq_printf(s, "%d=3D0x%02x", dom->hdr.id, mon_info.mon_config); + val =3D resctrl_arch_event_config_get(dom, evtid); + seq_printf(s, "%d=3D0x%02x", dom->hdr.id, val); sep =3D true; } seq_puts(s, "\n"); @@ -1693,33 +1715,23 @@ static int mbm_local_bytes_config_show(struct kernf= s_open_file *of, return 0; } =20 -static void mon_event_config_write(void *info) -{ - struct mon_config_info *mon_info =3D info; - unsigned int index; - - index =3D mon_event_config_index_get(mon_info->evtid); - if (index =3D=3D INVALID_CONFIG_INDEX) { - pr_warn_once("Invalid event id %d\n", mon_info->evtid); - return; - } - wrmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, 0); -} =20 static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_mon_domain *d, u32 evtid, u32 val) { struct mon_config_info mon_info =3D {0}; + u32 config_val; =20 /* - * Read the current config value first. If both are the same then + * Check the current config value first. If both are the same then * no need to write it again. */ - mon_info.evtid =3D evtid; - mondata_config_read(d, &mon_info); - if (mon_info.mon_config =3D=3D val) + config_val =3D resctrl_arch_event_config_get(d, evtid); + if (config_val =3D=3D INVALID_CONFIG_VALUE || config_val =3D=3D val) return; =20 + mon_info.d =3D d; + mon_info.evtid =3D evtid; mon_info.mon_config =3D val; =20 /* @@ -1728,7 +1740,8 @@ static void mbm_config_write_domain(struct rdt_resour= ce *r, * are scoped at the domain level. Writing any of these MSRs * on one CPU is observed by all the CPUs in the domain. */ - smp_call_function_any(&d->hdr.cpu_mask, mon_event_config_write, + smp_call_function_any(&d->hdr.cpu_mask, + resctrl_arch_event_config_set, &mon_info, 1); =20 /* diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index aab22ff8e0c1..757708cf5d3c 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -354,6 +354,10 @@ void resctrl_arch_reset_rmid(struct rdt_resource *r, s= truct rdt_mon_domain *d, */ void resctrl_arch_reset_rmid_all(struct rdt_resource *r, struct rdt_mon_do= main *d); =20 +void resctrl_arch_event_config_set(void *info); +u32 resctrl_arch_event_config_get(struct rdt_mon_domain *d, + enum resctrl_event_id eventid); + extern unsigned int resctrl_rmid_realloc_threshold; extern unsigned int resctrl_rmid_realloc_limit; =20 --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2077.outbound.protection.outlook.com [40.107.95.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91CFA17D8A6; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:24.9738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e785aca-a875-4e76-63c3-08dccd30316d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8274 Content-Type: text/plain; charset="utf-8" The MBM counters are allocated globally and assigned to RMID, event pair in a resctrl group. It is tracked by mbm_cntr_free_map. Then it is assigned to the domain based on the user input. It needs to be tracked at domain level also. Add the mbm_cntr_map bitmap in struct rdt_mon_domain to keep track of assignment at domain level. The global counter at mbm_cntr_free_map can be released when assignment at all the domains are cleared. Signed-off-by: Babu Moger --- v7: Added check mbm_cntr_assignable for allocating bitmap mbm_cntr_map v6: New patch to add domain level assignment. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 10 ++++++++++ include/linux/resctrl.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index cc101fbe8683..a014d5f4c0b3 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -4092,6 +4092,7 @@ static void __init rdtgroup_setup_default(void) =20 static void domain_destroy_mon_state(struct rdt_mon_domain *d) { + bitmap_free(d->mbm_cntr_map); bitmap_free(d->rmid_busy_llc); kfree(d->mbm_total); kfree(d->mbm_local); @@ -4165,6 +4166,15 @@ static int domain_setup_mon_state(struct rdt_resourc= e *r, struct rdt_mon_domain return -ENOMEM; } } + if (is_mbm_enabled() && r->mon.mbm_cntr_assignable) { + d->mbm_cntr_map =3D bitmap_zalloc(r->mon.num_mbm_cntrs, GFP_KERNEL); + if (!d->mbm_cntr_map) { + bitmap_free(d->rmid_busy_llc); + kfree(d->mbm_total); + kfree(d->mbm_local); + return -ENOMEM; + } + } =20 return 0; } diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 757708cf5d3c..882a6ec55f27 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -105,6 +105,7 @@ struct rdt_ctrl_domain { * @cqm_limbo: worker to periodically read CQM h/w counters * @mbm_work_cpu: worker CPU for MBM h/w counters * @cqm_work_cpu: worker CPU for CQM h/w counters + * @mbm_cntr_map: bitmap to track domain counter assignment */ struct rdt_mon_domain { struct rdt_domain_hdr hdr; @@ -116,6 +117,7 @@ struct rdt_mon_domain { struct delayed_work cqm_limbo; int mbm_work_cpu; int cqm_work_cpu; + unsigned long *mbm_cntr_map; }; =20 /** --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2069.outbound.protection.outlook.com [40.107.93.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B0AB18BB93; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:32.3020 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff90595e-e0fd-40fd-f7eb-08dccd3035cd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4457 The ABMC feature provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as the counter is assigned. The bandwidth events will be tracked by the hardware until the user changes the configuration. Each resctrl group can configure maximum two counters, one for total event and one for local event. The ABMC feature implements an MSR L3_QOS_ABMC_CFG (C000_03FDh). Configuration is done by setting the counter id, bandwidth source (RMID) and bandwidth configuration supported by BMEC (Bandwidth Monitoring Event Configuration). Attempts to read or write the MSR when ABMC is not enabled will result in a #GP(0) exception. Introduce the data structures and definitions for MSR L3_QOS_ABMC_CFG (0xC000_03FDh): =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Mnemonic Description Access Reset Type Value =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 63 CfgEn Configuration Enable R/W 0 62 CtrEn Enable/disable Tracking R/W 0 61:53 =E2=80=93 Reserved MBZ 0 52:48 CtrID Counter Identifier R/W 0 47 IsCOS BwSrc field is a CLOSID R/W 0 (not an RMID) 46:44 =E2=80=93 Reserved MBZ 0 43:32 BwSrc Bandwidth Source R/W 0 (RMID or CLOSID) 31:0 BwType Bandwidth configuration R/W 0 to track for this counter =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The feature details are documented in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v7: Removed the reference of L3_QOS_ABMC_DSC as it is not used anymore. Moved the configuration notes to kernel_doc. Adjusted the tabs for l3_qos_abmc_cfg and checkpatch seems happy. v6: Removed all the fs related changes. Added note on CfgEn,CtrEn. Removed the definitions which are not used. Removed cntr_id initialization. v5: Moved assignment flags here (path 10/19 of v4). Added MON_CNTR_UNSET definition to initialize cntr_id's. More details in commit log. Renamed few fields in l3_qos_abmc_cfg for readability. v4: Added more descriptions. Changed the name abmc_ctr_id to ctr_id. Added L3_QOS_ABMC_DSC. Used for reading the configuration. v3: No changes. v2: No changes. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 30 ++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index d86469bf5d41..dd988a082fa8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1183,6 +1183,7 @@ #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd =20 /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 6107101f2d8a..27617fe592ed 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -602,6 +602,36 @@ union cpuid_0x10_x_edx { unsigned int full; }; =20 +/* + * ABMC counters can be configured by writing to L3_QOS_ABMC_CFG. + * @bw_type : Bandwidth configuration(supported by BMEC) + * tracked by the @cntr_id. + * @bw_src : Bandwidth source (RMID or CLOSID). + * @reserved1 : Reserved. + * @is_clos : @bw_src field is a CLOSID (not an RMID). + * @cntr_id : Counter identifier. + * @reserved : Reserved. + * @cntr_en : Tracking enable bit. + * @cfg_en : Configuration enable bit. + * + * Configuration and tracking: + * CfgEn=3D1,CtrEn=3D0 : Configure CtrID and but no tracking the events ye= t. + * CfgEn=3D1,CtrEn=3D1 : Configure CtrID and start tracking events. + */ +union l3_qos_abmc_cfg { + struct { + unsigned long bw_type :32, + bw_src :12, + reserved1: 3, + is_clos : 1, + cntr_id : 5, + reserved : 9, + cntr_en : 1, + cfg_en : 1; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:44.0781 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de451cbb-b1d8-4c63-d8a8-08dccd303cd2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6662 Content-Type: text/plain; charset="utf-8" mbm_cntr_assign feature provides an option to the user to assign a hardware counter to an RMID and monitor the bandwidth as long as the counter is assigned. There can be two counters per monitor group, one for total event and another for local event. Introduce cntr_id to manage the assignments. Signed-off-by: Babu Moger --- v7: Minor comment update for cntr_id. v6: New patch. Separated FS and arch bits. --- arch/x86/kernel/cpu/resctrl/internal.h | 7 +++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 27617fe592ed..e0ae8b0b45b2 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -62,6 +62,11 @@ /* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ #define ABMC_ENABLE_BIT 0 =20 +/* Maximum assignable counters per resctrl group */ +#define MAX_CNTRS 2 + +#define MON_CNTR_UNSET U32_MAX + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -231,12 +236,14 @@ enum rdtgrp_mode { * @parent: parent rdtgrp * @crdtgrp_list: child rdtgroup node list * @rmid: rmid for this rdtgroup + * @cntr_id: IDs of hardware counters assigned to monitor group */ struct mongroup { struct kernfs_node *mon_data_kn; struct rdtgroup *parent; struct list_head crdtgrp_list; u32 rmid; + u32 cntr_id[MAX_CNTRS]; }; =20 /** diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index a014d5f4c0b3..7fa92143daa7 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -3529,6 +3529,9 @@ static int mkdir_rdt_prepare_rmid_alloc(struct rdtgro= up *rdtgrp) } rdtgrp->mon.rmid =3D ret; =20 + rdtgrp->mon.cntr_id[0] =3D MON_CNTR_UNSET; + rdtgrp->mon.cntr_id[1] =3D MON_CNTR_UNSET; + ret =3D mkdir_mondata_all(rdtgrp->kn, rdtgrp, &rdtgrp->mon.mon_data_kn); if (ret) { rdt_last_cmd_puts("kernfs subdir error\n"); @@ -4083,6 +4086,9 @@ static void __init rdtgroup_setup_default(void) rdtgroup_default.closid =3D RESCTRL_RESERVED_CLOSID; rdtgroup_default.mon.rmid =3D RESCTRL_RESERVED_RMID; rdtgroup_default.type =3D RDTCTRL_GROUP; + rdtgroup_default.mon.cntr_id[0] =3D MON_CNTR_UNSET; + rdtgroup_default.mon.cntr_id[1] =3D MON_CNTR_UNSET; + INIT_LIST_HEAD(&rdtgroup_default.mon.crdtgrp_list); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:48.3158 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ca551fe-bf0d-4c25-52d5-08dccd303f52 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6884 Content-Type: text/plain; charset="utf-8" The ABMC feature provides an option to the user to assign a hardware counter to an RMID, event pair and monitor the bandwidth as long as it is assigned. The assigned RMID will be tracked by the hardware until the user unassigns it manually. Counters are configured by writing to L3_QOS_ABMC_CFG MSR and specifying the counter id, bandwidth source, and bandwidth types. Provide the interface to assign the counter ids to RMID. The feature details are documented in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v7: Separated arch and fs functions. This patch only has arch implementatio= n. Added struct rdt_resource to the interface resctrl_arch_assign_cntr. Rename rdtgroup_abmc_cfg() to resctrl_abmc_config_one_amd(). v6: Removed mbm_cntr_alloc() from this patch to keep fs and arch code separate. Added code to update the counter assignment at domain level. v5: Few name changes to match cntr_id. Changed the function names to rdtgroup_assign_cntr resctr_arch_assign_cntr More comments on commit log. Added function summary. v4: Commit message update. User bitmap APIs where applicable. Changed the interfaces considering MPAM(arm). Added domain specific assignment. v3: Removed the static from the prototype of rdtgroup_assign_abmc. The function is not called directly from user anymore. These changes are related to global assignment interface. v2: Minor text changes in commit message. --- arch/x86/kernel/cpu/resctrl/internal.h | 3 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 45 ++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index e0ae8b0b45b2..57c31615eae7 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -702,6 +702,9 @@ int mbm_cntr_alloc(struct rdt_resource *r); void mbm_cntr_free(struct rdt_resource *r, u32 cntr_id); void resctrl_mbm_evt_config_init(struct rdt_hw_mon_domain *hw_dom); unsigned int mon_event_config_index_get(u32 evtid); +int resctrl_arch_assign_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 7fa92143daa7..7ad653b4e768 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1853,6 +1853,51 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static void resctrl_abmc_config_one_amd(void *info) +{ + u64 *msrval =3D info; + + wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, *msrval); +} + +/* + * Send an IPI to the domain to assign the counter to RMID, event pair. + */ +int resctrl_arch_assign_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, + enum resctrl_event_id evtid, u32 rmid, u32 closid, + u32 cntr_id, bool assign) +{ + struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); + union l3_qos_abmc_cfg abmc_cfg =3D { 0 }; + struct arch_mbm_state *arch_mbm; + + abmc_cfg.split.cfg_en =3D 1; + abmc_cfg.split.cntr_en =3D assign ? 1 : 0; + abmc_cfg.split.cntr_id =3D cntr_id; + abmc_cfg.split.bw_src =3D rmid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:23:55.4425 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d6f4e3d-2c7e-4133-66a5-08dccd30438f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8106 Content-Type: text/plain; charset="utf-8" The mbm_cntr_assign mode offers several hardware counters that can be assigned to an RMID-event pair and monitor the bandwidth as long as it is assigned. Counters are managed at two levels. The global assignment is tracked using the mbm_cntr_free_map field in the struct resctrl_mon, while domain-specific assignments are tracked using the mbm_cntr_map field in the struct rdt_mon_domain. Allocation begins at the global level and is then applied individually to each domain. Introduce an interface to allocate these counters and update the corresponding domains accordingly. Signed-off-by: Babu Moger --- v7: New patch. Moved all the FS code here. Merged rdtgroup_assign_cntr and rdtgroup_alloc_cntr. Adde new #define MBM_EVENT_ARRAY_INDEX. --- arch/x86/kernel/cpu/resctrl/internal.h | 2 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 46 ++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 57c31615eae7..6a90fc20be5b 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -705,6 +705,8 @@ unsigned int mon_event_config_index_get(u32 evtid); int resctrl_arch_assign_cntr(struct rdt_resource *r, struct rdt_mon_domain= *d, enum resctrl_event_id evtid, u32 rmid, u32 closid, u32 cntr_id, bool assign); +int rdtgroup_assign_cntr(struct rdt_resource *r, struct rdtgroup *rdtgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 7ad653b4e768..1d45120ff2b5 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -864,6 +864,13 @@ static int rdtgroup_rmid_show(struct kernfs_open_file = *of, return ret; } =20 +/* + * Get the counter index for the assignable counter + * 0 for evtid =3D=3D QOS_L3_MBM_TOTAL_EVENT_ID + * 1 for evtid =3D=3D QOS_L3_MBM_LOCAL_EVENT_ID + */ +#define MBM_EVENT_ARRAY_INDEX(_event) ((_event) - 2) + static int rdtgroup_mbm_assign_mode_show(struct kernfs_open_file *of, struct seq_file *s, void *v) { @@ -1898,6 +1905,45 @@ int resctrl_arch_assign_cntr(struct rdt_resource *r,= struct rdt_mon_domain *d, return 0; } =20 +/* + * Assign a hardware counter to the group. + * Counter will be assigned to all the domains if rdt_mon_domain is NULL + * else the counter will be allocated to specific domain. + */ +int rdtgroup_assign_cntr(struct rdt_resource *r, struct rdtgroup *rdtgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid) +{ + int index =3D MBM_EVENT_ARRAY_INDEX(evtid); + int cntr_id =3D rdtgrp->mon.cntr_id[index]; + + /* + * Allocate a new counter id to the group if the counter id is not + * is not assigned already. + */ + if (cntr_id =3D=3D MON_CNTR_UNSET) { + cntr_id =3D mbm_cntr_alloc(r); + if (cntr_id < 0) { + rdt_last_cmd_puts("Out of MBM assignable counters\n"); + return -ENOSPC; + } + rdtgrp->mon.cntr_id[index] =3D cntr_id; + } + + if (!d) { + list_for_each_entry(d, &r->mon_domains, hdr.list) { + resctrl_arch_assign_cntr(r, d, evtid, rdtgrp->mon.rmid, + rdtgrp->closid, cntr_id, true); + set_bit(cntr_id, d->mbm_cntr_map); + } + } else { + resctrl_arch_assign_cntr(r, d, evtid, rdtgrp->mon.rmid, + rdtgrp->closid, cntr_id, true); + set_bit(cntr_id, d->mbm_cntr_map); + } + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2088.outbound.protection.outlook.com [40.107.244.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7272179967; Wed, 4 Sep 2024 22:24:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 4 Sep 2024 17:24:01 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 17/24] x86/resctrl: Add the interface to unassign a MBM counter Date: Wed, 4 Sep 2024 17:21:32 -0500 Message-ID: <91e045eb3a3b461c44f61c64b826c9e05ac75abe.1725488488.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|CYYPR12MB8921:EE_ X-MS-Office365-Filtering-Correlation-Id: bc457430-10ec-46d3-7b85-08dccd30481a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:03.0805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc457430-10ec-46d3-7b85-08dccd30481a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8921 Content-Type: text/plain; charset="utf-8" The mbm_cntr_assign mode provides a limited number of hardware counters that can be assigned to an RMID-event pair to monitor bandwidth while assigned. If all counters are in use, the kernel will show an error message: "Out of MBM assignable counters" when a new assignment is requested. To make space for a new assignment, users must unassign an already assigned counter. Introduce an interface that allows for the unassignment of counter IDs from both the group and the domain. Additionally, ensure that the global counter is released if it is no longer assigned to any domains. Signed-off-by: Babu Moger --- v7: Merged rdtgroup_unassign_cntr and rdtgroup_free_cntr functions. Renamed rdtgroup_mbm_cntr_test() to rdtgroup_mbm_cntr_is_assigned(). Reworded the commit log little bit. v6: Removed mbm_cntr_free from this patch. Added counter test in all the domains and free if it is not assigned to any domains. v5: Few name changes to match cntr_id. Changed the function names to rdtgroup_unassign_cntr More comments on commit log. v4: Added domain specific unassign feature. Few name changes. v3: Removed the static from the prototype of rdtgroup_unassign_abmc. The function is not called directly from user anymore. These changes are related to global assignment interface. v2: No changes. --- arch/x86/kernel/cpu/resctrl/internal.h | 2 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 49 ++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 6a90fc20be5b..9a65a13ccbe9 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -707,6 +707,8 @@ int resctrl_arch_assign_cntr(struct rdt_resource *r, st= ruct rdt_mon_domain *d, u32 cntr_id, bool assign); int rdtgroup_assign_cntr(struct rdt_resource *r, struct rdtgroup *rdtgrp, struct rdt_mon_domain *d, enum resctrl_event_id evtid); +int rdtgroup_unassign_cntr(struct rdt_resource *r, struct rdtgroup *rdtgrp, + struct rdt_mon_domain *d, enum resctrl_event_id evtid); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 1d45120ff2b5..21b9ca4ce493 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1944,6 +1944,55 @@ int rdtgroup_assign_cntr(struct rdt_resource *r, str= uct rdtgroup *rdtgrp, return 0; } =20 +static int rdtgroup_mbm_cntr_is_assigned(struct rdt_resource *r, u32 cntr_= id) +{ + struct rdt_mon_domain *d; + + list_for_each_entry(d, &r->mon_domains, hdr.list) + if (test_bit(cntr_id, d->mbm_cntr_map)) + return 1; + + return 0; +} + +/* + * Unassign a hardware counter from the domain and the group. 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Wed, 4 Sep 2024 17:24:09 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 18/24] x86/resctrl: Auto Assign/unassign counters when mbm_cntr_assign is enabled Date: Wed, 4 Sep 2024 17:21:33 -0500 Message-ID: <5b02b069cfd7fc3ca30b1e17644d0ec73df7cef1.1725488488.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|DS7PR12MB8249:EE_ X-MS-Office365-Filtering-Correlation-Id: 519fd201-5132-42cd-74f7-08dccd304cd8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:11.0208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 519fd201-5132-42cd-74f7-08dccd304cd8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8249 Content-Type: text/plain; charset="utf-8" Assign/unassign counters on resctrl group creation/deletion. Two counters are required per group, one for MBM total event and one for MBM local event. There are a limited number of counters available for assignment. If these counters are exhausted, the kernel will display the error message: "Out of MBM assignable counters". However, it is not necessary to fail the creation of a group due to assignment failures. Users have the flexibility to modify the assignments at a later time. Signed-off-by: Babu Moger --- v7: Reworded the commit message. Removed the reference of ABMC with mbm_cntr_assign. Renamed the function rdtgroup_assign_cntrs to rdtgroup_assign_grp. v6: Removed the redundant comments on all the calls of rdtgroup_assign_cntrs. Updated the commit message. Dropped printing error message on every call of rdtgroup_assign_cntrs. v5: Removed the code to enable/disable ABMC during the mount. That will be another patch. Added arch callers to get the arch specific data. Renamed fuctions to match the other abmc function. Added code comments for assignment failures. v4: Few name changes based on the upstream discussion. Commit message update. v3: This is a new patch. Patch addresses the upstream comment to enable ABMC feature by default if the feature is available. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 21b9ca4ce493..bf94e4e05540 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2866,6 +2866,52 @@ static void schemata_list_destroy(void) } } =20 +/* + * Called when a new group is created. If `mbm_cntr_assign` mode is enable= d, + * counters are automatically assigned. Each group requires two counters: + * one for the total event and one for the local event. Due to the limited + * number of counters, assignments may fail in some cases. However, it is + * not necessary to fail the group creation. Users have the option to + * modify the assignments after the group has been created. + */ +static int rdtgroup_assign_grp(struct rdtgroup *rdtgrp) +{ + struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + int ret =3D 0; + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) + return 0; + + if (is_mbm_total_enabled()) + ret =3D rdtgroup_assign_cntr(r, rdtgrp, NULL, QOS_L3_MBM_TOTAL_EVENT_ID); + + if (!ret && is_mbm_local_enabled()) + ret =3D rdtgroup_assign_cntr(r, rdtgrp, NULL, QOS_L3_MBM_LOCAL_EVENT_ID); + + return ret; +} + +/* + * Called when a group is deleted. Counters are unassigned if it was in + * assigned state. + */ +static int rdtgroup_unassign_grp(struct rdtgroup *rdtgrp) +{ + struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + int ret =3D 0; + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) + return 0; + + if (is_mbm_total_enabled()) + ret =3D rdtgroup_unassign_cntr(r, rdtgrp, NULL, QOS_L3_MBM_TOTAL_EVENT_I= D); + + if (!ret && is_mbm_local_enabled()) + ret =3D rdtgroup_unassign_cntr(r, rdtgrp, NULL, QOS_L3_MBM_LOCAL_EVENT_I= D); + + return ret; +} + static int rdt_get_tree(struct fs_context *fc) { struct rdt_fs_context *ctx =3D rdt_fc2context(fc); @@ -2925,6 +2971,8 @@ static int rdt_get_tree(struct fs_context *fc) if (ret < 0) goto out_mongrp; rdtgroup_default.mon.mon_data_kn =3D kn_mondata; + + rdtgroup_assign_grp(&rdtgroup_default); } =20 ret =3D rdt_pseudo_lock_init(); @@ -2955,6 +3003,7 @@ static int rdt_get_tree(struct fs_context *fc) out_psl: rdt_pseudo_lock_release(); out_mondata: + rdtgroup_unassign_grp(&rdtgroup_default); if (resctrl_arch_mon_capable()) kernfs_remove(kn_mondata); out_mongrp: @@ -3214,6 +3263,8 @@ static void rdt_kill_sb(struct super_block *sb) resctrl_arch_disable_alloc(); if (resctrl_arch_mon_capable()) resctrl_arch_disable_mon(); + + rdtgroup_unassign_grp(&rdtgroup_default); resctrl_mounted =3D false; kernfs_kill_sb(sb); mutex_unlock(&rdtgroup_mutex); @@ -3805,6 +3856,8 @@ static int rdtgroup_mkdir_mon(struct kernfs_node *par= ent_kn, goto out_unlock; } =20 + rdtgroup_assign_grp(rdtgrp); + kernfs_activate(rdtgrp->kn); =20 /* @@ -3849,6 +3902,8 @@ static int rdtgroup_mkdir_ctrl_mon(struct kernfs_node= *parent_kn, if (ret) goto out_closid_free; =20 + rdtgroup_assign_grp(rdtgrp); + kernfs_activate(rdtgrp->kn); =20 ret =3D rdtgroup_init_alloc(rdtgrp); @@ -3874,6 +3929,7 @@ static int rdtgroup_mkdir_ctrl_mon(struct kernfs_node= *parent_kn, out_del_list: list_del(&rdtgrp->rdtgroup_list); out_rmid_free: + rdtgroup_unassign_grp(rdtgrp); mkdir_rdt_prepare_rmid_free(rdtgrp); out_closid_free: closid_free(closid); @@ -3944,6 +4000,9 @@ static int rdtgroup_rmdir_mon(struct rdtgroup *rdtgrp= , cpumask_var_t tmpmask) update_closid_rmid(tmpmask, NULL); =20 rdtgrp->flags =3D RDT_DELETED; + + rdtgroup_unassign_grp(rdtgrp); + free_rmid(rdtgrp->closid, rdtgrp->mon.rmid); =20 /* @@ -3990,6 +4049,8 @@ static int rdtgroup_rmdir_ctrl(struct rdtgroup *rdtgr= p, cpumask_var_t tmpmask) cpumask_or(tmpmask, tmpmask, &rdtgrp->cpu_mask); update_closid_rmid(tmpmask, NULL); =20 + rdtgroup_unassign_grp(rdtgrp); + free_rmid(rdtgrp->closid, rdtgrp->mon.rmid); closid_free(rdtgrp->closid); =20 --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2044.outbound.protection.outlook.com [40.107.244.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1849A188A17; Wed, 4 Sep 2024 22:24:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 4 Sep 2024 17:24:16 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 19/24] x86/resctrl: Report "Unassigned" for MBM events in mbm_cntr_assign mode Date: Wed, 4 Sep 2024 17:21:34 -0500 Message-ID: <1c5b054d8fbc3f7ad22c686d0d5e21e6573187bd.1725488488.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|IA1PR12MB6555:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cf2e772-be7f-4e2d-c07b-08dccd305144 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013|7416014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:18.4571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cf2e772-be7f-4e2d-c07b-08dccd305144 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6555 Content-Type: text/plain; charset="utf-8" In mbm_cntr_assign mode, the hardware counter should be assigned to read the MBM events. Report "Unassigned" in case the user attempts to read the events without assigning the counter. Signed-off-by: Babu Moger --- v7: Moved the documentation under "mon_data". Updated the text little bit. v6: Added more explaination in the resctrl.rst Added checks to detect "Unassigned" before reading RMID. v5: New patch. --- Documentation/arch/x86/resctrl.rst | 10 ++++++++++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 13 ++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 3e9302971faf..ff5397d19704 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -417,6 +417,16 @@ When monitoring is enabled all MON groups will also co= ntain: for the L3 cache they occupy). These are named "mon_sub_L3_YY" where "YY" is the node number. =20 + The mbm_cntr_assign mode allows users to assign a hardware counter + to an RMID-event pair, enabling bandwidth monitoring for as long + as the counter remains assigned. The hardware will continue tracking + the assigned RMID until the user manually unassigns it, ensuring + that counters are not reset during this period. With a limited number + of counters, the system may run out of assignable resources. In + mbm_cntr_assign mode, MBM event counters will return "Unassigned" + if the counter is not allocated to the event when read. Users must + manually assign a counter to read the events. + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 50fa1fe9a073..fc19b1d131b2 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -562,7 +562,7 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) struct rdtgroup *rdtgrp; struct rdt_resource *r; union mon_data_bits md; - int ret =3D 0; + int ret =3D 0, index; =20 rdtgrp =3D rdtgroup_kn_lock_live(of->kn); if (!rdtgrp) { @@ -576,6 +576,15 @@ int rdtgroup_mondata_show(struct seq_file *m, void *ar= g) evtid =3D md.u.evtid; r =3D &rdt_resources_all[resid].r_resctrl; =20 + if (resctrl_arch_mbm_cntr_assign_enabled(r) && evtid !=3D QOS_L3_OCCUP_EV= ENT_ID) { + index =3D mon_event_config_index_get(evtid); + if (index !=3D INVALID_CONFIG_INDEX && + rdtgrp->mon.cntr_id[index] =3D=3D MON_CNTR_UNSET) { + rr.err =3D -ENOENT; + goto checkresult; + } + } + if (md.u.sum) { /* * This file requires summing across all domains that share @@ -613,6 +622,8 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) seq_puts(m, "Error\n"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:26.1292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fe44ba0a-a0fe-4dd3-6c23-08dccd3055d7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7730 Content-Type: text/plain; charset="utf-8" Introduce interface to switch between mbm_cntr_assign and default modes. $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode [mbm_cntr_assign] default To enable the "mbm_cntr_assign" mode: $ echo "mbm_cntr_assign" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode To enable the default monitoring mode: $ echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode MBM event counters will reset when mbm_assign_mode is changed. Signed-off-by: Babu Moger --- v7: Changed the interface name to mbm_assign_mode. Removed the references of ABMC. Added the changes to reset global and domain bitmaps. Added the changes to reset rmid. v6: Changed the mode name to mbm_cntr_assign. Moved all the FS related code here. Added changes to reset mbm_cntr_map and resctrl group counters. v5: Change log and mode description text correction. v4: Minor commit text changes. Keep the default to ABMC when supported. Fixed comments to reflect changed interface "mbm_mode". v3: New patch to address the review comments from upstream. --- Documentation/arch/x86/resctrl.rst | 15 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 74 +++++++++++++++++++++++++- 2 files changed, 88 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index ff5397d19704..743c0b64a330 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -290,6 +290,21 @@ with the following files: than 'num_mbm_cntrs' to be created. Reading the mbm files may report 'Una= vailable' if there is no hardware resource assigned. =20 + * To enable ABMC feature: + :: + + # echo "mbm_cntr_assign" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mo= de + + * To enable the legacy monitoring feature: + :: + + # echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + + The MBM event counters will reset when mbm_assign_mode is changed. Moving= to + mbm_cntr_assign will require users to assign the counters to the events to + read the events. Otherwise, the MBM event counters will return "Unassigne= d" + when read. + "num_mbm_cntrs": The number of monitoring counters available for assignment. =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index bf94e4e05540..7a8ece12d7da 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -895,6 +895,77 @@ static int rdtgroup_mbm_assign_mode_show(struct kernfs= _open_file *of, return 0; } =20 +static void rdtgroup_mbm_cntr_reset(struct rdt_resource *r) +{ + struct rdtgroup *prgrp, *crgrp; + struct rdt_mon_domain *dom; + + /* + * Hardware counters will reset after switching the monitor mode. + * Reset the architectural state so that reading of hardware + * counter is not considered as an overflow in the next update. + * Also reset the domain counter bitmap. + */ + list_for_each_entry(dom, &r->mon_domains, hdr.list) { + bitmap_zero(dom->mbm_cntr_map, r->mon.num_mbm_cntrs); + resctrl_arch_reset_rmid_all(r, dom); + } + + /* Reset global MBM counter map */ + bitmap_fill(r->mon.mbm_cntr_free_map, r->mon.num_mbm_cntrs); + + /* Reset the cntr_id's for all the monitor groups */ + list_for_each_entry(prgrp, &rdt_all_groups, rdtgroup_list) { + prgrp->mon.cntr_id[0] =3D MON_CNTR_UNSET; + prgrp->mon.cntr_id[1] =3D MON_CNTR_UNSET; + list_for_each_entry(crgrp, &prgrp->mon.crdtgrp_list, + mon.crdtgrp_list) { + crgrp->mon.cntr_id[0] =3D MON_CNTR_UNSET; + crgrp->mon.cntr_id[1] =3D MON_CNTR_UNSET; + } + } +} + +static ssize_t rdtgroup_mbm_assign_mode_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + int ret =3D 0; + bool enable; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + if (!strcmp(buf, "default")) { + enable =3D 0; + } else if (!strcmp(buf, "mbm_cntr_assign")) { + enable =3D 1; + } else { + ret =3D -EINVAL; + rdt_last_cmd_puts("Unsupported assign mode\n"); + goto write_exit; + } + + if (enable !=3D resctrl_arch_mbm_cntr_assign_enabled(r)) { + rdtgroup_mbm_cntr_reset(r); + ret =3D resctrl_arch_mbm_cntr_assign_set(r, enable); + } + +write_exit: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + static int rdtgroup_num_mbm_cntrs_show(struct kernfs_open_file *of, struct seq_file *s, void *v) { @@ -2107,9 +2178,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "mbm_assign_mode", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D rdtgroup_mbm_assign_mode_show, + .write =3D rdtgroup_mbm_assign_mode_write, .fflags =3D RFTYPE_MON_INFO, }, { --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2052.outbound.protection.outlook.com [40.107.237.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B25AF1925A4; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:33.6955 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4aa820f5-bcfc-403f-f4c3-08dccd305a59 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7874 Content-Type: text/plain; charset="utf-8" Configure mbm_cntr_assign on AMD. 'mbm_cntr_assign' mode in AMD is ABMC (Assignable Bandwidth Monitoring Counters). When the ABMC is updated, it must be updated on all logical processors in the resctrl domain. Signed-off-by: Babu Moger --- v7: Introduced resctrl_arch_mbm_cntr_assign_configure() to configure. Moved the default settings to rdt_get_mon_l3_config(). It should be done before the hotplug handler is called. It cannot be done at rdtgroup_init(). v6: Keeping the default enablement in arch init code for now. This may need some discussion. Renamed resctrl_arch_configure_abmc to resctrl_arch_mbm_cntr_assign_co= nfigure. v5: New patch to enable ABMC by default. --- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 11 +++++++++++ 3 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 9a65a13ccbe9..3250561f0187 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -709,6 +709,7 @@ int rdtgroup_assign_cntr(struct rdt_resource *r, struct= rdtgroup *rdtgrp, struct rdt_mon_domain *d, enum resctrl_event_id evtid); int rdtgroup_unassign_cntr(struct rdt_resource *r, struct rdtgroup *rdtgrp, struct rdt_mon_domain *d, enum resctrl_event_id evtid); +void resctrl_arch_mbm_cntr_assign_configure(struct rdt_resource *r); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 09b1d8bb0aa0..314c0b297470 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1261,6 +1261,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); r->mon.num_mbm_cntrs =3D (ebx & 0xFFFF) + 1; resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); + hw_res->mbm_cntr_assign_enabled =3D true; } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 7a8ece12d7da..1054583bef9d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2726,6 +2726,13 @@ int resctrl_arch_mbm_cntr_assign_set(struct rdt_reso= urce *r, bool enable) return 0; } =20 +void resctrl_arch_mbm_cntr_assign_configure(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + resctrl_abmc_set_one_amd(&hw_res->mbm_cntr_assign_enabled); +} + /* * We don't allow rdtgroup directories to be created anywhere * except the root directory. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:41.4420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9029aa6b-56d1-48af-facc-08dccd305ef7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6212 Content-Type: text/plain; charset="utf-8" Users can modify the configuration of assignable events. Whenever the event configuration is updated, MBM assignments must be revised across all monitor groups within the impacted domains. Signed-off-by: Babu Moger --- v7: New patch to update the assignments. Missed it earlier. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 53 ++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 1054583bef9d..0b1490d71e77 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -871,6 +871,15 @@ static int rdtgroup_rmid_show(struct kernfs_open_file = *of, */ #define MBM_EVENT_ARRAY_INDEX(_event) ((_event) - 2) =20 +static bool resctrl_mbm_event_assigned(struct rdtgroup *rdtg, + struct rdt_mon_domain *d, u32 evtid) +{ + int index =3D MBM_EVENT_ARRAY_INDEX(evtid); + int cntr_id =3D rdtg->mon.cntr_id[index]; + + return (cntr_id !=3D MON_CNTR_UNSET && test_bit(cntr_id, d->mbm_cntr_map= )); +} + static int rdtgroup_mbm_assign_mode_show(struct kernfs_open_file *of, struct seq_file *s, void *v) { @@ -1793,12 +1802,48 @@ static int mbm_local_bytes_config_show(struct kernf= s_open_file *of, return 0; } =20 +static int resctrl_mbm_event_update_assign(struct rdt_resource *r, + struct rdt_mon_domain *d, u32 evtid) +{ + struct rdt_mon_domain *dom; + struct rdtgroup *rdtg; + int ret =3D 0; + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) + return ret; + + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) { + struct rdtgroup *crg; + + list_for_each_entry(dom, &r->mon_domains, hdr.list) { + if (d =3D=3D dom && resctrl_mbm_event_assigned(rdtg, dom, evtid)) { + ret =3D rdtgroup_assign_cntr(r, rdtg, dom, evtid); + if (ret) + goto out_done; + } + } + + list_for_each_entry(crg, &rdtg->mon.crdtgrp_list, mon.crdtgrp_list) { + list_for_each_entry(dom, &r->mon_domains, hdr.list) { + if (d =3D=3D dom && resctrl_mbm_event_assigned(crg, dom, evtid)) { + ret =3D rdtgroup_assign_cntr(r, crg, dom, evtid); + if (ret) + goto out_done; + } + } + } + } + +out_done: + return ret; +} =20 static void mbm_config_write_domain(struct rdt_resource *r, struct rdt_mon_domain *d, u32 evtid, u32 val) { struct mon_config_info mon_info =3D {0}; u32 config_val; + int ret; =20 /* * Check the current config value first. If both are the same then @@ -1822,6 +1867,14 @@ static void mbm_config_write_domain(struct rdt_resou= rce *r, resctrl_arch_event_config_set, &mon_info, 1); =20 + /* + * Counter assignments needs to be updated to match the event + * configuration. + */ + ret =3D resctrl_mbm_event_update_assign(r, d, evtid); + if (ret) + rdt_last_cmd_puts("Assign failed, event will be Unavailable\n"); + /* * When an Event Configuration is changed, the bandwidth counters * for all RMIDs and Events will be cleared by the hardware. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:48.8988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a961cee6-ba29-44bc-2bee-08dccd30636c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4038 Content-Type: text/plain; charset="utf-8" Provide the interface to list the assignment states of all the resctrl groups in mbm_cntr_assign mode. Example: $cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control List follows the following format: "//=3D" Format for specific type of groups: - Default CTRL_MON group: "//=3D" - Non-default CTRL_MON group: "//=3D" - Child MON group of default CTRL_MON group: "//=3D" - Child MON group of non-default CTRL_MON group: "//=3D" Flags can be one of the following: t MBM total event is enabled l MBM local event is enabled tl Both total and local MBM events are enabled _ None of the MBM events are enabled Signed-off-by: Babu Moger --- v7: Renamed the interface name from 'mbm_control' to 'mbm_assign_control' to match 'mbm_assign_mode'. Removed Arch references from FS code. Added rdt_last_cmd_clear() before the command processing. Added rdtgroup_mutex before all the calls. Removed references of ABMC from FS code. v6: The domain specific assignment can be determined looking at mbm_cntr_ma= p. Removed rdtgroup_abmc_dom_cfg() and rdtgroup_abmc_dom_state(). Removed the switch statement for the domain_state detection. Determined the flags incremently. Removed special handling of default group while printing.. v5: Replaced "assignment flags" with "flags". Changes related to mon structure. Changes related renaming the interface from mbm_assign_control to mbm_control. v4: Added functionality to query domain specific assigment in. rdtgroup_abmc_dom_state(). v3: New patch. Addresses the feedback to provide the global assignment interface. https://lore.kernel.org/lkml/c73f444b-83a1-4e9a-95d3-54c5165ee782@intel= .com/ --- Documentation/arch/x86/resctrl.rst | 44 +++++++++++++++++ arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 68 ++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 743c0b64a330..a72cb3a6b07a 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -308,6 +308,50 @@ with the following files: "num_mbm_cntrs": The number of monitoring counters available for assignment. =20 +"mbm_assign_control": + Reports the resctrl group and monitor status of each group. + + List follows the following format: + "//=3D" + + Format for specific type of groups: + + * Default CTRL_MON group: + "//=3D" + + * Non-default CTRL_MON group: + "//=3D" + + * Child MON group of default CTRL_MON group: + "//=3D" + + * Child MON group of non-default CTRL_MON group: + "//=3D" + + Flags can be one of the following: + :: + + t MBM total event is assigned. + l MBM local event is assigned. + tl Both total and local MBM events are assigned. + _ None of the MBM events are assigned. + + Examples: + :: + + # mkdir /sys/fs/resctrl/mon_groups/child_default_mon_grp + # mkdir /sys/fs/resctrl/non_default_ctrl_mon_grp + # mkdir /sys/fs/resctrl/non_default_ctrl_mon_grp/mon_groups/child_non_de= fault_mon_grp + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dtl; + + There are four resctrl groups. All the groups have total and local MBM e= vents + assigned on domain 0 and 1. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 314c0b297470..74db63402482 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1262,6 +1262,7 @@ int __init rdt_get_mon_l3_config(struct rdt_resource = *r) r->mon.num_mbm_cntrs =3D (ebx & 0xFFFF) + 1; resctrl_file_fflags_init("num_mbm_cntrs", RFTYPE_MON_INFO); hw_res->mbm_cntr_assign_enabled =3D true; + resctrl_file_fflags_init("mbm_assign_control", RFTYPE_MON_INFO); } } =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 0b1490d71e77..ffa0ed98efbe 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -985,6 +985,68 @@ static int rdtgroup_num_mbm_cntrs_show(struct kernfs_o= pen_file *of, return 0; } =20 +static char *rdtgroup_mon_state_to_str(struct rdtgroup *rdtgrp, + struct rdt_mon_domain *d, char *str) +{ + char *tmp =3D str; + + /* Query the total and local event flags for the domain */ + if (resctrl_mbm_event_assigned(rdtgrp, d, QOS_L3_MBM_TOTAL_EVENT_ID)) + *tmp++ =3D 't'; + + if (resctrl_mbm_event_assigned(rdtgrp, d, QOS_L3_MBM_LOCAL_EVENT_ID)) + *tmp++ =3D 'l'; + + if (tmp =3D=3D str) + *tmp++ =3D '_'; + + *tmp =3D '\0'; + return str; +} + +static int rdtgroup_mbm_assign_control_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + struct rdt_mon_domain *dom; + struct rdtgroup *rdtg; + char str[10]; + + mutex_lock(&rdtgroup_mutex); + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) { + rdt_last_cmd_puts("mbm_cntr_assign mode is not enabled\n"); + mutex_unlock(&rdtgroup_mutex); + return -EINVAL; + } + + rdt_last_cmd_clear(); + + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) { + struct rdtgroup *crg; + + seq_printf(s, "%s//", rdtg->kn->name); + + list_for_each_entry(dom, &r->mon_domains, hdr.list) + seq_printf(s, "%d=3D%s;", dom->hdr.id, + rdtgroup_mon_state_to_str(rdtg, dom, str)); + seq_putc(s, '\n'); + + list_for_each_entry(crg, &rdtg->mon.crdtgrp_list, + mon.crdtgrp_list) { + seq_printf(s, "%s/%s/", rdtg->kn->name, crg->kn->name); + + list_for_each_entry(dom, &r->mon_domains, hdr.list) + seq_printf(s, "%d=3D%s;", dom->hdr.id, + rdtgroup_mon_state_to_str(crg, dom, str)); + seq_putc(s, '\n'); + } + } + + mutex_unlock(&rdtgroup_mutex); + return 0; +} + #ifdef CONFIG_PROC_CPU_RESCTRL =20 /* @@ -2251,6 +2313,12 @@ static struct rftype res_common_files[] =3D { .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D rdtgroup_num_mbm_cntrs_show, }, + { + .name =3D "mbm_assign_control", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D rdtgroup_mbm_assign_control_show, + }, { .name =3D "cpus_list", .mode =3D 0644, --=20 2.34.1 From nobody Fri Dec 19 16:42:10 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2069.outbound.protection.outlook.com [40.107.92.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36C2917BEC3; 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Wed, 4 Sep 2024 17:24:55 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 24/24] x86/resctrl: Introduce interface to modify assignment states of the groups Date: Wed, 4 Sep 2024 17:21:39 -0500 Message-ID: <68c8ef0592c653c5b99cd26d982966cd4a41cb31.1725488488.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|SA3PR12MB9227:EE_ X-MS-Office365-Filtering-Correlation-Id: 11dcb5d7-4468-481a-8839-08dccd306839 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|36860700013|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Sep 2024 22:24:56.9242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 11dcb5d7-4468-481a-8839-08dccd306839 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB9227 Introduce the interface to assign MBM events in mbm_cntr_assign mode. Events can be enabled or disabled by writing to file /sys/fs/resctrl/info/L3_MON/mbm_assign_control Format is similar to the list format with addition of opcode for the assignment operation. "//" Format for specific type of groups: * Default CTRL_MON group: "//" * Non-default CTRL_MON group: "//" * Child MON group of default CTRL_MON group: "//" * Child MON group of non-default CTRL_MON group: "//" Domain_id '*' will apply the flags on all the domains. Opcode can be one of the following: =3D Update the assignment to match the flags + Assign a new MBM event without impacting existing assignments. - Unassign a MBM event from currently assigned events. Assignment flags can be one of the following: t MBM total event l MBM local event tl Both total and local MBM events _ None of the MBM events. Valid only with '=3D' opcode. Signed-off-by: Babu Moger --- v7: Simplified the parsing (strsep(&token, "//") in rdtgroup_mbm_assign_con= trol_write(). Added mutex lock in rdtgroup_mbm_assign_control_write() while processin= g. Renamed rdtgroup_find_grp to rdtgroup_find_grp_by_name. Fixed rdtgroup_str_to_mon_state to return error for invalid flags. Simplified the calls rdtgroup_assign_cntr by merging few functions earl= ier. Removed ABMC reference in FS code. Reinette commented about handling the combination of flags like 'lt_' a= nd '_lt'. Not sure if we need to change the behaviour here. Processed them sequen= cially right now. Users have the liberty to pass the flags. Restricting it might be a pro= blem later. v6: Added support assign all if domain id is '*' Fixed the allocation of counter id if it not assigned already. v5: Interface name changed from mbm_assign_control to mbm_control. Fixed opcode and flags combination. '=3D_" is valid. "-_" amd "+_" is not valid. Minor message update. Renamed the function with prefix - rdtgroup_. Corrected few documentation mistakes. Rebase related changes after SNC support. v4: Added domain specific assignments. Fixed the opcode parsing. v3: New patch. Addresses the feedback to provide the global assignment interface. https://lore.kernel.org/lkml/c73f444b-83a1-4e9a-95d3-54c5165ee782@intel= .com/ --- Documentation/arch/x86/resctrl.rst | 94 +++++++++- arch/x86/kernel/cpu/resctrl/internal.h | 10 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 234 ++++++++++++++++++++++++- 3 files changed, 336 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index a72cb3a6b07a..e46ec63d920e 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -334,7 +334,7 @@ with the following files: t MBM total event is assigned. l MBM local event is assigned. tl Both total and local MBM events are assigned. - _ None of the MBM events are assigned. + _ None of the MBM events are assigned. Only works with opcode '=3D' for= write. =20 Examples: :: @@ -352,6 +352,98 @@ with the following files: There are four resctrl groups. All the groups have total and local MBM e= vents assigned on domain 0 and 1. =20 + Assignment state can be updated by writing to the interface. + + Format is similar to the list format with addition of opcode for the + assignment operation. + + "//" + + Format for each type of groups: + + * Default CTRL_MON group: + "//" + + * Non-default CTRL_MON group: + "//" + + * Child MON group of default CTRL_MON group: + "//" + + * Child MON group of non-default CTRL_MON group: + "//" + + Domain_id '*' will apply the flags on all the domains. + + Opcode can be one of the following: + :: + + =3D Update the assignment to match the MBM event. + + Assign a new MBM event without impacting existing assignments. + - Unassign a MBM event from currently assigned events. + + Examples: + :: + + Initial group status: + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dtl; + + To update the default group to assign only total MBM event on domain 0: + # echo "//0=3Dt" > /sys/fs/resctrl/info/L3_MON/mbm_assign_control + + Assignment status after the update: + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dt;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dtl; + + To update the MON group child_default_mon_grp to remove total MBM event= on domain 1: + # echo "/child_default_mon_grp/1-t" > /sys/fs/resctrl/info/L3_MON/mbm_a= ssign_control + + Assignment status after the update: + $ cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3Dtl; + //0=3Dt;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + + To update the MON group non_default_ctrl_mon_grp/child_non_default_mon_= grp to + unassign both local and total MBM events on domain 1: + # echo "non_default_ctrl_mon_grp/child_non_default_mon_grp/1=3D_" > + /sys/fs/resctrl/info/L3_MON/mbm_assign_control + + Assignment status after the update: + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3D_; + //0=3Dt;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + + To update the default group to add a local MBM event domain 0. + # echo "//0+l" > /sys/fs/resctrl/info/L3_MON/mbm_assign_control + + Assignment status after the update: + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3Dtl;1=3Dtl; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3D_; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + + To update the non default CTRL_MON group non_default_ctrl_mon_grp to un= assign all + the MBM events on all the domains. + # echo "non_default_ctrl_mon_grp//*=3D_" > /sys/fs/resctrl/info/L3_MON/= mbm_assign_control + + Assignment status after the update: + #cat /sys/fs/resctrl/info/L3_MON/mbm_assign_control + non_default_ctrl_mon_grp//0=3D_;1=3D_; + non_default_ctrl_mon_grp/child_non_default_mon_grp/0=3Dtl;1=3D_; + //0=3Dtl;1=3Dtl; + /child_default_mon_grp/0=3Dtl;1=3Dl; + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 3250561f0187..799f36eef2b6 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -67,6 +67,16 @@ =20 #define MON_CNTR_UNSET U32_MAX =20 +/* + * Assignment flags for mbm_cntr_assign feature + */ +enum { + ASSIGN_NONE =3D 0, + ASSIGN_TOTAL =3D BIT(QOS_L3_MBM_TOTAL_EVENT_ID), + ASSIGN_LOCAL =3D BIT(QOS_L3_MBM_LOCAL_EVENT_ID), + ASSIGN_INVALID, +}; + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index ffa0ed98efbe..56ecdf7406ae 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1047,6 +1047,237 @@ static int rdtgroup_mbm_assign_control_show(struct = kernfs_open_file *of, return 0; } =20 +static int rdtgroup_str_to_mon_state(char *flag) +{ + int i, mon_state =3D ASSIGN_NONE; + + for (i =3D 0; i < strlen(flag); i++) { + switch (*(flag + i)) { + case 't': + mon_state |=3D ASSIGN_TOTAL; + break; + case 'l': + mon_state |=3D ASSIGN_LOCAL; + break; + case '_': + mon_state =3D ASSIGN_NONE; + break; + default: + return ASSIGN_INVALID; + } + } + + return mon_state; +} + +static struct rdtgroup *rdtgroup_find_grp_by_name(enum rdt_group_type rtyp= e, + char *p_grp, char *c_grp) +{ + struct rdtgroup *rdtg, *crg; + + if (rtype =3D=3D RDTCTRL_GROUP && *p_grp =3D=3D '\0') { + return &rdtgroup_default; + } else if (rtype =3D=3D RDTCTRL_GROUP) { + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) + if (!strcmp(p_grp, rdtg->kn->name)) + return rdtg; + } else if (rtype =3D=3D RDTMON_GROUP) { + list_for_each_entry(rdtg, &rdt_all_groups, rdtgroup_list) { + if (!strcmp(p_grp, rdtg->kn->name)) { + list_for_each_entry(crg, &rdtg->mon.crdtgrp_list, + mon.crdtgrp_list) { + if (!strcmp(c_grp, crg->kn->name)) + return crg; + } + } + } + } + + return NULL; +} + +static int rdtgroup_process_flags(struct rdt_resource *r, + enum rdt_group_type rtype, + char *p_grp, char *c_grp, char *tok) +{ + int op, mon_state, assign_state, unassign_state; + char *dom_str, *id_str, *op_str; + struct rdt_mon_domain *d; + struct rdtgroup *rdtgrp; + unsigned long dom_id; + int ret, found =3D 0; + + rdtgrp =3D rdtgroup_find_grp_by_name(rtype, p_grp, c_grp); + + if (!rdtgrp) { + rdt_last_cmd_puts("Not a valid resctrl group\n"); + return -EINVAL; + } + +next: + if (!tok || tok[0] =3D=3D '\0') + return 0; + + /* Start processing the strings for each domain */ + dom_str =3D strim(strsep(&tok, ";")); + + op_str =3D strpbrk(dom_str, "=3D+-"); + + if (op_str) { + op =3D *op_str; + } else { + rdt_last_cmd_puts("Missing operation =3D, +, -, _ character\n"); + return -EINVAL; + } + + id_str =3D strsep(&dom_str, "=3D+-"); + + /* Check for domain id '*' which means all domains */ + if (id_str && *id_str =3D=3D '*') { + d =3D NULL; + goto check_state; + } else if (!id_str || kstrtoul(id_str, 10, &dom_id)) { + rdt_last_cmd_puts("Missing domain id\n"); + return -EINVAL; + } + + /* Verify if the dom_id is valid */ + list_for_each_entry(d, &r->mon_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + found =3D 1; + break; + } + } + + if (!found) { + rdt_last_cmd_printf("Invalid domain id %ld\n", dom_id); + return -EINVAL; + } + +check_state: + mon_state =3D rdtgroup_str_to_mon_state(dom_str); + + if (mon_state =3D=3D ASSIGN_INVALID) { + rdt_last_cmd_puts("Invalid assign flag\n"); + goto out_fail; + } + + assign_state =3D 0; + unassign_state =3D 0; + + switch (op) { + case '+': + if (mon_state =3D=3D ASSIGN_NONE) { + rdt_last_cmd_puts("Invalid assign opcode\n"); + goto out_fail; + } + assign_state =3D mon_state; + break; + case '-': + if (mon_state =3D=3D ASSIGN_NONE) { + rdt_last_cmd_puts("Invalid assign opcode\n"); + goto out_fail; + } + unassign_state =3D mon_state; + break; + case '=3D': + assign_state =3D mon_state; + unassign_state =3D (ASSIGN_TOTAL | ASSIGN_LOCAL) & ~assign_state; + break; + default: + break; + } + + if (assign_state & ASSIGN_TOTAL) { + ret =3D rdtgroup_assign_cntr(r, rdtgrp, d, QOS_L3_MBM_TOTAL_EVENT_ID); + if (ret) + goto out_fail; + } + + if (assign_state & ASSIGN_LOCAL) { + ret =3D rdtgroup_assign_cntr(r, rdtgrp, d, QOS_L3_MBM_LOCAL_EVENT_ID); + if (ret) + goto out_fail; + } + + if (unassign_state & ASSIGN_TOTAL) { + ret =3D rdtgroup_unassign_cntr(r, rdtgrp, d, QOS_L3_MBM_TOTAL_EVENT_ID); + if (ret) + goto out_fail; + } + + if (unassign_state & ASSIGN_LOCAL) { + ret =3D rdtgroup_unassign_cntr(r, rdtgrp, d, QOS_L3_MBM_LOCAL_EVENT_ID); + if (ret) + goto out_fail; + } + + goto next; + +out_fail: + + return -EINVAL; +} + +static ssize_t rdtgroup_mbm_assign_control_write(struct kernfs_open_file *= of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + char *token, *cmon_grp, *mon_grp; + enum rdt_group_type rtype; + int ret; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + if (!resctrl_arch_mbm_cntr_assign_enabled(r)) { + rdt_last_cmd_puts("mbm_cntr_assign mode is not enabled\n"); + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + return -EINVAL; + } + + rdt_last_cmd_clear(); + + while ((token =3D strsep(&buf, "\n")) !=3D NULL) { + if (strstr(token, "/")) { + /* + * The write command follows the following format: + * =E2=80=9C//=E2= =80=9D + * Extract the CTRL_MON group. + */ + cmon_grp =3D strsep(&token, "/"); + + /* + * Extract the MON_GROUP. + * strsep returns empty string for contiguous delimiters. + * Empty mon_grp here means it is a RDTCTRL_GROUP. + */ + mon_grp =3D strsep(&token, "/"); + + if (*mon_grp =3D=3D '\0') + rtype =3D RDTCTRL_GROUP; + else + rtype =3D RDTMON_GROUP; + + ret =3D rdtgroup_process_flags(r, rtype, cmon_grp, mon_grp, token); + if (ret) + break; + } + } + + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + #ifdef CONFIG_PROC_CPU_RESCTRL =20 /* @@ -2315,9 +2546,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "mbm_assign_control", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D rdtgroup_mbm_assign_control_show, + .write =3D rdtgroup_mbm_assign_control_write, }, { .name =3D "cpus_list", --=20 2.34.1