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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:16:39.8519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ccb7009-4808-4633-6506-08dcbe0ecf83 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8772 Content-Type: text/plain; charset="utf-8" Smart Data Cache Injection (SDCI) is a mechanism that enables direct insertion of data from I/O devices into the L3 cache. By directly caching data from I/O devices rather than first storing the I/O data in DRAM, SDCI reduces demands on DRAM bandwidth and reduces latency to the processor consuming the I/O data. The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to limit the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register where n maximum supported CLOSID. Add CPUID feature bit that can be used to configure SDCIAE. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index dd4682857c12..5ca39431d423 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -473,6 +473,7 @@ #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enable= d */ #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch hi= story at vmexit using SW loop */ #define X86_FEATURE_FAST_CPPC (21*32 + 5) /* AMD Fast CPPC */ +#define X86_FEATURE_SDCIAE (21*32 + 6) /* "" L3 Smart Data Cache Injectio= n Allocation Enforcement */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index b7d9f530ae16..1ef42cc4cc75 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_SDCIAE, X86_FEATURE_RDT_A }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index c84c30188fdf..88f00575c9ff 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_SDCIAE, CPUID_EBX, 6, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_PMC_FREEZE, CPUID_EAX, 2, 0x80000022, 0 }, --=20 2.34.1 From nobody Sat Feb 7 15:09:54 2026 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2081.outbound.protection.outlook.com [40.107.212.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDCCB1BF30D; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:16:46.8356 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac237447-d3ba-4049-c8e8-08dcbe0ed3b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5882 Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE). Signed-off-by: Babu Moger --- Documentation/admin-guide/kernel-parameters.txt | 2 +- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 09126bb8cc9f..63f17d23b8f4 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5604,7 +5604,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, sdciae. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:16:54.3820 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf14ab07-2874-4f35-48e0-08dcbe0ed831 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4354 Content-Type: text/plain; charset="utf-8" Detect SDCIAE`(L3 Smart Data Cache Injection Allocation Enforcement) feature and initialize sdciae_capable. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 7 +++++++ include/linux/resctrl.h | 2 ++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index c4dfc768ddf5..e4381e3feb75 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -296,6 +296,11 @@ static void rdt_get_cdp_config(int level) rdt_resources_all[level].r_resctrl.cdp_capable =3D true; } =20 +static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r) +{ + r->sdciae_capable =3D true; +} + static void rdt_get_cdp_l3_config(void) { rdt_get_cdp_config(RDT_RESOURCE_L3); @@ -921,6 +926,8 @@ static __init bool get_rdt_alloc_resources(void) rdt_get_cache_alloc_cfg(1, r); if (rdt_cpu_has(X86_FEATURE_CDP_L3)) rdt_get_cdp_l3_config(); + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) + rdt_get_sdciae_alloc_cfg(r); ret =3D true; } if (rdt_cpu_has(X86_FEATURE_CAT_L2)) { diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index b0875b99e811..281ba4fb8972 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -202,6 +202,7 @@ enum resctrl_scope { * @evt_list: List of monitoring events * @fflags: flags to choose base and info files * @cdp_capable: Is the CDP feature available on this resource + * @sdciae_capable: Is SDCIAE feature available on this resource */ struct rdt_resource { int rid; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:17:04.5431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8e8f644-154b-4ce4-f6f1-08dcbe0ede3a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB8610 Content-Type: text/plain; charset="utf-8" SDCIAE feature can be enabled by setting bit 1 in MSR L3_QOS_EXT_CFG. When the state of SDCIAE is changed, it must be changed to the updated value on all logical processors in the QOS Domain. By default, the SDCIAE feature is disabled. Introduce arch handlers to detect and enable/disable the feature. The SDCIAE feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.4.7 L3 Smart Data Cache Injection Allocation Enforcement (SDCIAE) Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 12 +++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 61 ++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 82c6a4d350e0..c78afed3c21f 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1181,6 +1181,7 @@ /* - AMD: */ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff #define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 /* MSR_IA32_VMX_MISC bits */ diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 955999aecfca..ceb0e8e1ed76 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) =20 +/* Setting bit 1 in L3_QOS_EXT_CFG enables the SDCIAE feature. */ +#define SDCIAE_ENABLE_BIT 1 + /** * cpumask_any_housekeeping() - Choose any CPU in @mask, preferring those = that * aren't marked nohz_full @@ -477,6 +480,7 @@ struct rdt_parse_data { * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource + * @sdciae_enabled: SDCIAE feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -491,6 +495,7 @@ struct rdt_hw_resource { unsigned int mbm_width; unsigned int mbm_cfg_mask; bool cdp_enabled; + bool sdciae_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) @@ -536,6 +541,13 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_leve= l l, bool enable); =20 void arch_mon_domain_online(struct rdt_resource *r, struct rdt_mon_domain = *d); =20 +static inline bool resctrl_arch_get_sdciae_enabled(enum resctrl_res_level = l) +{ + return rdt_resources_all[l].sdciae_enabled; +} + +int resctrl_arch_set_sdciae_enabled(enum resctrl_res_level l, bool enable); + /* * To return the common struct rdt_resource, which is contained in struct * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index d7163b764c62..c62d6183bfe4 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1789,6 +1789,67 @@ static ssize_t mbm_local_bytes_config_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static void resctrl_sdciae_msrwrite(void *arg) +{ + bool *enable =3D arg; + + if (*enable) + msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + else + msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); +} + +static int resctrl_sdciae_setup(enum resctrl_res_level l, bool enable) +{ + struct rdt_resource *r =3D &rdt_resources_all[l].r_resctrl; + struct rdt_ctrl_domain *d; + + /* Update L3_QOS_EXT_CFG MSR on all the CPUs in all domains*/ + list_for_each_entry(d, &r->ctrl_domains, hdr.list) + on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_msrwrite, &enable, 1); + + return 0; +} + +static int resctrl_sdciae_enable(enum resctrl_res_level l) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[l]; + int ret =3D 0; + + if (!hw_res->sdciae_enabled) { + ret =3D resctrl_sdciae_setup(l, true); + if (!ret) + hw_res->sdciae_enabled =3D true; + } + + return ret; +} + +static void resctrl_sdciae_disable(enum resctrl_res_level l) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[l]; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:17:09.8981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbd2f6fa-c09e-4abe-75dc-08dcbe0ee16e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7518 Content-Type: text/plain; charset="utf-8" The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to configure the portion of the L3 cache used for SDCI. When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register as reported by CPUID Fn0000_0010_EDX_x1.MAX_COS. For example, if MAX_COS=3D15, SDCI lines will be allocated into the L3 cache partitions determined by the bitmask in the L3_MASK_15 register. Introduce interface to enable/disable SDCIAE feature on user input. Signed-off-by: Babu Moger --- Documentation/arch/x86/resctrl.rst | 22 +++++++ arch/x86/kernel/cpu/resctrl/core.c | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 88 ++++++++++++++++++++++++++ 4 files changed, 112 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index a824affd741d..cb1532dd843f 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -135,6 +135,28 @@ related to allocation: "1": Non-contiguous 1s value in CBM is supported. =20 +"sdciae": + Indicates if the system can support SDCIAE (L3 Smart Data Cache + Injection Allocation Enforcement) feature. + + Smart Data Cache Injection (SDCI) is a mechanism that enables + direct insertion of data from I/O devices into the L3 cache. + By directly caching data from I/O devices rather than first + storing the I/O data in DRAM, SDCI reduces demands on DRAM + bandwidth and reduces latency to the processor consuming the + I/O data. The SDCIAE feature allows system software to configure + limit the portion of the L3 cache used for SDCI. + + "0": + Feature is not enabled. + "1": + Feature is enabled. + + Feature can be enabled/disabled by writing to the interface. + Example:: + + # echo 1 > /sys/fs/resctrl/info/L3/sdciae + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index e4381e3feb75..6a9512008a4a 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -299,6 +299,7 @@ static void rdt_get_cdp_config(int level) static void rdt_get_sdciae_alloc_cfg(struct rdt_resource *r) { r->sdciae_capable =3D true; + resctrl_sdciae_rftype_init(); } =20 static void rdt_get_cdp_l3_config(void) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index ceb0e8e1ed76..9a3da6d49144 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -662,6 +662,7 @@ void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init thread_throttle_mode_init(void); void __init mbm_config_rftype_init(const char *config); void rdt_staged_configs_clear(void); +void __init resctrl_sdciae_rftype_init(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index c62d6183bfe4..58e4df195207 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -171,6 +171,27 @@ void closid_free(int closid) __set_bit(closid, &closid_free_map); } =20 +/* + * SDCIAE feature uses max CLOSID to route the SDCI traffic. + * Get the max CLOSID number + */ +static u32 get_sdciae_closid(struct rdt_resource *r) +{ + return resctrl_arch_get_num_closid(r) - 1; +} + +static int closid_alloc_sdciae(struct rdt_resource *r) +{ + u32 sdciae_closid =3D get_sdciae_closid(r); + + if (closid_free_map & (1 << sdciae_closid)) { + closid_free_map &=3D ~(1 << sdciae_closid); + return sdciae_closid; + } else { + return -ENOSPC; + } +} + /** * closid_allocated - test if provided closid is in use * @closid: closid to be tested @@ -1850,6 +1871,57 @@ int resctrl_arch_set_sdciae_enabled(enum resctrl_res= _level l, bool enable) return 0; } =20 +static int resctrl_sdciae_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + seq_printf(seq, "%x\n", resctrl_arch_get_sdciae_enabled(RDT_RESOURCE_L3)); + return 0; +} + +static ssize_t resctrl_sdciae_write(struct kernfs_open_file *of, char *buf, + size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + unsigned int enable; + u32 sdciae_closid; + int ret; + + if (!r->sdciae_capable) + return -EINVAL; + + ret =3D kstrtouint(buf, 0, &enable); + if (ret) + return ret; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + + /* Update the MSR only when there is a change */ + if (resctrl_arch_get_sdciae_enabled(RDT_RESOURCE_L3) !=3D enable) { + if (enable) { + ret =3D closid_alloc_sdciae(r); + if (ret < 0) { + rdt_last_cmd_puts("SDCIAE CLOSID is not available\n"); + goto out_sdciae; + } + } else { + sdciae_closid =3D get_sdciae_closid(r); + closid_free(sdciae_closid); + } + + ret =3D resctrl_arch_set_sdciae_enabled(RDT_RESOURCE_L3, enable); + } + +out_sdciae: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2002,6 +2074,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdtgroup_schemata_show, .fflags =3D RFTYPE_CTRL_BASE, }, + { + .name =3D "sdciae", + .mode =3D 0644, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_sdciae_show, + .write =3D resctrl_sdciae_write, + }, { .name =3D "mode", .mode =3D 0644, @@ -2101,6 +2180,15 @@ void __init mbm_config_rftype_init(const char *confi= g) rft->fflags =3D RFTYPE_MON_INFO | RFTYPE_RES_CACHE; } =20 +void __init resctrl_sdciae_rftype_init(void) +{ + struct rftype *rft; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:17:17.3668 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d8c4d35-9a33-48f8-19e9-08dcbe0ee5e2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7488 Content-Type: text/plain; charset="utf-8" When enabled, SDCIAE forces all SDCI lines to be placed into the L3 cache partitions identified by the highest-supported L3_MASK_n register where n is the maximum CLOSID supported. Add the interface to display CBMs (Capacity Bit Mask) of the SDCIAE. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 29 +++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 50fa1fe9a073..fc99f4d17e6c 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -439,7 +439,7 @@ u32 resctrl_arch_get_config(struct rdt_resource *r, str= uct rdt_ctrl_domain *d, return hw_dom->ctrl_val[idx]; } =20 -static void show_doms(struct seq_file *s, struct resctrl_schema *schema, i= nt closid) +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id) { struct rdt_resource *r =3D schema->res; struct rdt_ctrl_domain *dom; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 9a3da6d49144..f2c87ca37b13 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -663,6 +663,7 @@ void __init thread_throttle_mode_init(void); void __init mbm_config_rftype_init(const char *config); void rdt_staged_configs_clear(void); void __init resctrl_sdciae_rftype_init(void); +void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 58e4df195207..51bc715bb6ae 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1922,6 +1922,25 @@ static ssize_t resctrl_sdciae_write(struct kernfs_op= en_file *of, char *buf, return ret ?: nbytes; } =20 +static int resctrl_sdciae_cbm_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 sdciae_closid; + + if (!resctrl_arch_get_sdciae_enabled(RDT_RESOURCE_L3)) { + rdt_last_cmd_puts("SDCIAE is not enabled\n"); + return -EINVAL; + } + + sdciae_closid =3D get_sdciae_closid(r); + + show_doms(seq, s, sdciae_closid); + + return 0; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2081,6 +2100,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D resctrl_sdciae_show, .write =3D resctrl_sdciae_write, }, + { + .name =3D "sdciae_cbm", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D resctrl_sdciae_cbm_show, + }, { .name =3D "mode", .mode =3D 0644, @@ -2187,6 +2212,10 @@ void __init resctrl_sdciae_rftype_init(void) rft =3D rdtgroup_get_rftype_by_name("sdciae"); if (rft) rft->fflags =3D RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE; + + rft =3D rdtgroup_get_rftype_by_name("sdciae_cbm"); + if (rft) + rft->fflags =3D RFTYPE_CTRL_INFO | RFTYPE_RES_CACHE; } =20 /** --=20 2.34.1 From nobody Sat Feb 7 15:09:54 2026 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2076.outbound.protection.outlook.com [40.107.102.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A734F1C0DC7; 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Fri, 16 Aug 2024 11:17:23 -0500 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 7/7] x86/resctrl: Introduce interface to modify SDCIAE Capacity Bit Masks Date: Fri, 16 Aug 2024 11:16:24 -0500 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E7:EE_|MW5PR12MB5682:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ff54788-5cc5-4f50-c2f4-08dcbe0eea64 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?3zPoAndhN1Mgzr4wa60hrTWjn2tHWyeoZfGeDbM2FlcDfTOv7dObLkwCkQHK?= =?us-ascii?Q?BAs6KQKfYgBuG11kCWacZVwvGxQUXseGEHM7jRV8alUR3VL5nysnDS2le2af?= =?us-ascii?Q?jmk4/QPBMS5uAr2hJa0GgyP2yLqUY6mkz206ivhorJEYQAyEgIA//2UzfYtF?= =?us-ascii?Q?JKofYFtOuysoTO/3oaVaapBZ2vUHDhlHt/EZFO4IDkAMB1xMoKHTRfdq37Ef?= =?us-ascii?Q?aEjdFS14wb9ta1And9tPD+8ET+g1ey47zUA1CiQ71Pchik2YquOkXtgJz2XY?= =?us-ascii?Q?1R3CKhMEk6hAUBiM23pRbBcxRTVgQWwHKJQmudQWpjt+JVj+8EjJZvFQtfUB?= =?us-ascii?Q?4uo3psDHa6iO3T0uRl5MU74qPHMb7ENl9lEtmoLcFfrR3tdV6+5+o4W7Q4CS?= =?us-ascii?Q?7op9ULMFVniYynrhdrS685gfiF1HnPvqK79nrA6MSBchL9sK23pPkspSmlBH?= =?us-ascii?Q?QpQ2+sAWlShBM340A50mxb2fAmVRln0S01eCxmLHxJjA0hgeDPUq5WIjyaem?= =?us-ascii?Q?l/A2onBWROULzF0rEKcW8FjFDWZVeHchRYUhBSh8P4EfSC0hejXD/8ye/z0U?= =?us-ascii?Q?d87fi4zPQiKTtEdvksiLV9LH+WsSZcAeQXYKScibDSheAsBaaYpAuPFBffNI?= =?us-ascii?Q?z0u+zzwmct7y1niuJG2knMXzbI7hSqBbrJJXYoWiQ5Zt9u0vdptNjalNIvTo?= =?us-ascii?Q?LVoUkG3GjpvlTuFoC0TEvSdxD5O5l1xQ95Cojc6yQ4RIwzX2eDXXU7POFjVY?= =?us-ascii?Q?jP44lTKjDGLLKlN4DIirsOYYgVrQF/v1rLFKrNfWiuZllDFAN6gj8cqYvLBR?= =?us-ascii?Q?+KAJfqEWL3W0R4KheeNTN0PAb9U+hU5eY2lTGRmwgs+H7LKi+uJVVY/TqzNA?= =?us-ascii?Q?f38uIdxLQVB29/1+YFXW0+To7F2sGr2FzDlJTASVKLjNqF+x8iASqeb9eNQ0?= =?us-ascii?Q?YHnD2qo2PUnZImBSDHfm+aSTqtitjQlePGM/nI6EfgRTjjGO+UfWgFEbaYt0?= =?us-ascii?Q?SUyTvqISGmjh5c06+KGRKdwyh+3xRsJ1Zgf9nJzRmjnIe9AGMjRH+iFHVyVq?= =?us-ascii?Q?0X5EFFDLo77GkofTUNauyZklyQZB0XFxKwVtVW+KrvxLRk8gnqa4ufOBQlTo?= =?us-ascii?Q?27RwkEj3jRy4c/XEF/3POeAlBWypB4NwWw5+xNuMBIHs95+IbrnWLBIFtCvC?= =?us-ascii?Q?0aM5z0ziVCMBSxOKWCyopQmMf4fngVsSJTCfLrwECwNTWcUgoMlttIFH0szx?= =?us-ascii?Q?eJepfpiL/xoQ5jlsSu23uBs6trCU8aQlP5nrLwPukLgav9BCRoP1LtMGkEmy?= =?us-ascii?Q?WwTTOcyVvyYrnAOf0CeDfhMbtZdPFY1J3cSoAWJJx5uGnajIxmEHIpqVg2DV?= =?us-ascii?Q?wkdMXpBwi4pn5c1IrTKPVN/L5y+I/YnCWPPs6+rCDeEu1txtWiabAGH27GVR?= =?us-ascii?Q?KCDHXn3hTMCmzj3s9bTK/rK3k43XvyR2?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 16:17:24.9496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ff54788-5cc5-4f50-c2f4-08dcbe0eea64 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5682 Content-Type: text/plain; charset="utf-8" The SDCIAE (SDCI Allocation Enforcement) PQE feature allows system software to limit the portion of the L3 cache used for SDCI. Provide the interface to modify SDCIAE CBMs (Capacity Bit Masks). Signed-off-by: Babu Moger --- Documentation/arch/x86/resctrl.rst | 7 ++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 122 +++++++++++++++++++++- 4 files changed, 130 insertions(+), 2 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index cb1532dd843f..33de17387980 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -157,6 +157,13 @@ related to allocation: =20 # echo 1 > /sys/fs/resctrl/info/L3/sdciae =20 +"sdciae_cbm": + Capacity Bit Mask (CBM) available to SDCIAE supported devices. + CBM can be configured by writing to the interface in the + following format:: + + L3:=3D;=3D;... + Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: =20 diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index fc99f4d17e6c..cf39eee5fba9 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -97,7 +97,7 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_= schema *s, * requires at least two bits set. * AMD allows non-contiguous bitmasks. */ -static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) +bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) { unsigned long first_bit, zero_bit, val; unsigned int cbm_len =3D r->cache.cbm_len; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index f2c87ca37b13..66428950a326 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -664,6 +664,7 @@ void __init mbm_config_rftype_init(const char *config); void rdt_staged_configs_clear(void); void __init resctrl_sdciae_rftype_init(void); void show_doms(struct seq_file *s, struct resctrl_schema *schema, int clos= id); +bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); =20 diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 51bc715bb6ae..247909461ab3 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1941,6 +1941,125 @@ static int resctrl_sdciae_cbm_show(struct kernfs_op= en_file *of, return 0; } =20 +/* + * Read the CBM and check the validity. Make sure CBM is not shared + * with any other exclusive resctrl groups. + */ +static int resctrl_parse_cbm(char *buf, struct resctrl_schema *s, + struct rdt_ctrl_domain *d) +{ + struct resctrl_staged_config *cfg; + struct rdt_resource *r =3D s->res; + u32 sdciae_closid; + u32 cbm_val; + + cfg =3D &d->staged_config[s->conf_type]; + if (cfg->have_new_ctrl) { + rdt_last_cmd_printf("Duplicate domain %d\n", d->hdr.id); + return -EINVAL; + } + + if (!cbm_validate(buf, &cbm_val, r)) + return -EINVAL; + + /* + * The CBM may not overlap with other exclusive group. + */ + sdciae_closid =3D get_sdciae_closid(r); + if (rdtgroup_cbm_overlaps(s, d, cbm_val, sdciae_closid, true)) { + rdt_last_cmd_puts("Overlaps with exclusive group\n"); + return -EINVAL; + } + + cfg->new_ctrl =3D cbm_val; + cfg->have_new_ctrl =3D true; + + return 0; +} + +static int resctrl_parse_line(char *line, struct rdt_resource *r, + struct resctrl_schema *s) +{ + struct rdt_ctrl_domain *d; + char *dom =3D NULL, *id; + unsigned long dom_id; + +next: + if (!line || line[0] =3D=3D '\0') + return 0; + + dom =3D strsep(&line, ";"); + id =3D strsep(&dom, "=3D"); + if (!dom || kstrtoul(id, 10, &dom_id)) { + rdt_last_cmd_puts("Missing '=3D' or non-numeric domain\n"); + return -EINVAL; + } + + dom =3D strim(dom); + list_for_each_entry(d, &r->ctrl_domains, hdr.list) { + if (d->hdr.id =3D=3D dom_id) { + if (resctrl_parse_cbm(dom, s, d)) + return -EINVAL; + goto next; + } + } + return -EINVAL; +} + +static ssize_t resctrl_sdciae_cbm_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct resctrl_schema *s =3D of->kn->parent->priv; + struct rdt_resource *r =3D s->res; + u32 sdciae_closid; + char *resname; + int ret =3D 0; + + /* Valid input requires a trailing newline */ + if (nbytes =3D=3D 0 || buf[nbytes - 1] !=3D '\n') + return -EINVAL; + + buf[nbytes - 1] =3D '\0'; + + cpus_read_lock(); + mutex_lock(&rdtgroup_mutex); + + rdt_last_cmd_clear(); + rdt_staged_configs_clear(); + + resname =3D strim(strsep(&buf, ":")); + if (!buf) { + rdt_last_cmd_puts("Missing ':'\n"); + ret =3D -EINVAL; + goto out; + } + + if (strcmp(resname, "L3")) { + rdt_last_cmd_printf("Unsupported resource name '%s'\n", resname); + ret =3D -EINVAL; + goto out; + } + + if (buf[0] =3D=3D '\0') { + rdt_last_cmd_printf("Missing '%s' value\n", resname); + ret =3D -EINVAL; + goto out; + } + + ret =3D resctrl_parse_line(buf, r, s); + if (ret) + goto out; + + sdciae_closid =3D get_sdciae_closid(r); + ret =3D resctrl_arch_update_domains(r, sdciae_closid); + +out: + mutex_unlock(&rdtgroup_mutex); + cpus_read_unlock(); + + return ret ?: nbytes; +} + /* rdtgroup information files for one cache resource. */ static struct rftype res_common_files[] =3D { { @@ -2102,9 +2221,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "sdciae_cbm", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D resctrl_sdciae_cbm_show, + .write =3D resctrl_sdciae_cbm_write, }, { .name =3D "mode", --=20 2.34.1