From nobody Fri Dec 19 05:59:45 2025 Received: from mail.manjaro.org (mail.manjaro.org [116.203.91.91]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E26713D24D; Sun, 30 Jun 2024 16:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.91.91 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719763250; cv=none; b=lKxQBTcFZ80b/Zv38lcxts1mgNMdQF0GhD29eFYWZ0IOreov2QhizoU0iomnO9+9YzOVoRPXhuF+tPmLvCPrb1Uy2ANFFt4838UVakxQuHq4UJ7DFrT9ZdS06jn4cGa6cMcejsew8yog0x0vB+VlaFlse3QZ0oYAGmDGtlisQVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719763250; c=relaxed/simple; bh=xRk41s21xgdhBMtCScNxenFDjTyNNLqJd6TznaRc6SI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iOUj0Hw/OjZz3OsPJXM62pbDpTl3Wu9Hs1tUoZFE2LjyuW9Tu/le5dlOO9T5rK1HEY+XZTxWruEf6J9DPa91XZ9ljPYY63Gr57jGn6j+dKfyU/6JrGWiiXKBGFeBT/PPBDbVuVr8LEjwSXfxTXn9BUyAKjYF+jwnDXifzR22H6o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=manjaro.org; spf=pass smtp.mailfrom=manjaro.org; dkim=pass (2048-bit key) header.d=manjaro.org header.i=@manjaro.org header.b=FmPBVSk3; arc=none smtp.client-ip=116.203.91.91 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=manjaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=manjaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=manjaro.org header.i=@manjaro.org header.b="FmPBVSk3" From: Dragan Simic DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=manjaro.org; s=2021; t=1719763245; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vf64E0kNlbgeCg1YuEunVC6IdAgC+52ElMh5y13hzkU=; b=FmPBVSk3Jw1in4Cz0sCkplCERgOplzAF2U/gtA7OgHD5Qq+ql2aI5yj8p/5JxRUZLUPiKX 0JQ7Lcjk1AZj61wMi9lu9dZz8IGeonxvirs52/uJ9PQeJj2hYGVN5G2oh9sK6vBEm4RnbS 2SenhLqZC+3qQBqIKP0Df7zTxpVwQxoFISGZRHsmT8xuunDj+bnNTvvd9ukt/yXYirK7ni /Z3B/jpb1S9P9z3idpnMMhBll/7KOzEkxvoMMv5pZcnsViS/N0OUkIVwyjJpkXhm4xf3gc wNjbAiXsXsDKAOFma/Ii8sp7DDmKKQYbbJIdJuChfPcOykfZzMybmlUoxDj9sg== To: linux-rockchip@lists.infradead.org Cc: heiko@sntech.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, didi.debian@cknow.org, jonas@kwiboo.se Subject: [PATCH v3 1/2] arm64: dts: rockchip: Add GPU OPP voltage ranges to RK356x SoC dtsi Date: Sun, 30 Jun 2024 18:00:40 +0200 Message-Id: <7e9ba70fd54a21d6f1f267df11e0acabff8d24e0.1719763100.git.dsimic@manjaro.org> In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: ORIGINATING; auth=pass smtp.auth=dsimic@manjaro.org smtp.mailfrom=dsimic@manjaro.org Content-Type: text/plain; charset="utf-8" Add support for voltage ranges to the GPU OPPs defined in the SoC dtsi for Rockchip RK356x. This is, for example, useful for RK356x-based boards that are designed to use the same power supply for the GPU and NPU portions of the SoC, which is described further in the following documents: - Rockchip RK3566 Hardware Design Guide, version 1.1.0, page 37 - Rockchip RK3568 Hardware Design Guide, version 1.2, page 78 The values for the exact GPU OPP voltages and the lower limits for the GPU OPP voltage ranges differ from the values found in the vendor kernel source (cf. downstream commit f8b9431ee38e ("arm64: dts: rockchip: rk3568: support adjust opp-table by otp")), [1][2] and present the exact GPU OPP voltage values that have served us well so far. [1] https://github.com/rockchip-linux/kernel/commit/f8b9431ee38ed561650be70= 92ab93f564598daa9 [2] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed56= 1650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi Suggested-by: Diederik de Haas Helped-by: Jonas Karlman Signed-off-by: Dragan Simic --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index d8543b5557ee..ec772bce359a 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -195,32 +195,32 @@ gpu_opp_table: opp-table-1 { =20 opp-200000000 { opp-hz =3D /bits/ 64 <200000000>; - opp-microvolt =3D <825000>; + opp-microvolt =3D <825000 825000 1000000>; }; =20 opp-300000000 { opp-hz =3D /bits/ 64 <300000000>; - opp-microvolt =3D <825000>; + opp-microvolt =3D <825000 825000 1000000>; }; =20 opp-400000000 { opp-hz =3D /bits/ 64 <400000000>; - opp-microvolt =3D <825000>; + opp-microvolt =3D <825000 825000 1000000>; }; =20 opp-600000000 { opp-hz =3D /bits/ 64 <600000000>; - opp-microvolt =3D <825000>; + opp-microvolt =3D <825000 825000 1000000>; }; =20 opp-700000000 { opp-hz =3D /bits/ 64 <700000000>; - opp-microvolt =3D <900000>; + opp-microvolt =3D <900000 900000 1000000>; }; =20 opp-800000000 { opp-hz =3D /bits/ 64 <800000000>; - opp-microvolt =3D <1000000>; + opp-microvolt =3D <1000000 1000000 1000000>; }; }; From nobody Fri Dec 19 05:59:45 2025 Received: from mail.manjaro.org (mail.manjaro.org [116.203.91.91]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C08913DBBE; Sun, 30 Jun 2024 16:00:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.203.91.91 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719763250; cv=none; b=XwNBE/BYAvm8JImQ4sZaKZ5Bcx0Pv2oGEtxHYFaZgANmEFy55wbJpjLcJgdWh5S22cf3QAAPNwAr0kj18lupt81+2yg9vlI2uqGBytloJBAW1Tmq6t9VsI5SYqbg2/Hu8ubk/pSlTnNxC3Ezt0ROg2V3rvgbMisqM8+QYH6RruM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719763250; c=relaxed/simple; bh=UXJgWksWglnFs3muIQpJ7TNHZ3RJRjmZTfDMGVRRZcg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bTEe4YVmtJ3SPpghFnvaqRuH170Vf4SOgfBMdc59JNvSUo7v2j7AFooriMSC+zf9gh9XkPm4RDecnL03aFx4rNtY07IA0ifz8/tJawOKgzS7PRLsWxM+wXsrrAj46zYkGvaom88r9WMzFizZLhTveCOEjXyjQCH8LtusmXmen5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=manjaro.org; spf=pass smtp.mailfrom=manjaro.org; dkim=pass (2048-bit key) header.d=manjaro.org header.i=@manjaro.org header.b=UNNtXGRc; arc=none smtp.client-ip=116.203.91.91 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=manjaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=manjaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=manjaro.org header.i=@manjaro.org header.b="UNNtXGRc" From: Dragan Simic DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=manjaro.org; s=2021; t=1719763246; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Guv1sE7D+9DIv1Ejtj1tQsUSVZc3puEsRvEvnQebVMM=; b=UNNtXGRc4LwBEU3X/kQ1BtSCnp6NZxC8faJEiyINdG8haStOfiAW+kHXJo8pvo0THTEFb6 9BX5+/HdxOX/AokQUqQ8q93xef5QKVG8i53ZzJuB/wfzG6YHO/6Tg7OZ6qKgExk9Z/xw0Q oHDCPIIictYkSM5V8atUmi2cDiv0O+qUsVDpNSfLDi6eAWWAIJsr0jkawJP42PIyrNJQX5 UxGqRWGSHADptp6iqRJ/4yeegnU5kYk+0V6SROa3DV8WldAkZtqmX6VzolIU7LrNfMgr41 lfCbx0RnbucyTT9X9R2El4jqllrce+woVXrC4gXNUMWQ794LwyFNwd7lRKFVKw== To: linux-rockchip@lists.infradead.org Cc: heiko@sntech.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, didi.debian@cknow.org, jonas@kwiboo.se Subject: [PATCH v3 2/2] arm64: dts: rockchip: Update GPU OPP voltages in RK356x SoC dtsi Date: Sun, 30 Jun 2024 18:00:41 +0200 Message-Id: <80301764e8983c8410c806ed2256403823709897.1719763100.git.dsimic@manjaro.org> In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: ORIGINATING; auth=pass smtp.auth=dsimic@manjaro.org smtp.mailfrom=dsimic@manjaro.org Content-Type: text/plain; charset="utf-8" Update the values for the exact Rockchip RK356x GPU OPP voltages and the lower limits for the GPU OPP voltage ranges, using the most conservative values (i.e. the highest per-OPP voltages) found in the vendor kernel source (cf. downstream commit f8b9431ee38e ("arm64: dts: rockchip: rk3568: support adjust opp-table by otp")). [1][2] Using the most conservative per-OPP voltages ensures reliable GPU operation regardless of the actual GPU binning, with the downside of possibly using a bit more power than absolutely needed. [1] https://github.com/rockchip-linux/kernel/commit/f8b9431ee38ed561650be70= 92ab93f564598daa9 [2] https://raw.githubusercontent.com/rockchip-linux/kernel/f8b9431ee38ed56= 1650be7092ab93f564598daa9/arch/arm64/boot/dts/rockchip/rk3568.dtsi Suggested-by: Diederik de Haas Helped-by: Jonas Karlman Signed-off-by: Dragan Simic --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts= /rockchip/rk356x.dtsi index ec772bce359a..e3c77dabc72b 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -195,27 +195,27 @@ gpu_opp_table: opp-table-1 { =20 opp-200000000 { opp-hz =3D /bits/ 64 <200000000>; - opp-microvolt =3D <825000 825000 1000000>; + opp-microvolt =3D <850000 850000 1000000>; }; =20 opp-300000000 { opp-hz =3D /bits/ 64 <300000000>; - opp-microvolt =3D <825000 825000 1000000>; + opp-microvolt =3D <850000 850000 1000000>; }; =20 opp-400000000 { opp-hz =3D /bits/ 64 <400000000>; - opp-microvolt =3D <825000 825000 1000000>; + opp-microvolt =3D <850000 850000 1000000>; }; =20 opp-600000000 { opp-hz =3D /bits/ 64 <600000000>; - opp-microvolt =3D <825000 825000 1000000>; + opp-microvolt =3D <900000 900000 1000000>; }; =20 opp-700000000 { opp-hz =3D /bits/ 64 <700000000>; - opp-microvolt =3D <900000 900000 1000000>; + opp-microvolt =3D <950000 950000 1000000>; }; =20 opp-800000000 {