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[87.16.233.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a63570e5d0esm217427966b.214.2024.05.30.03.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:50 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta , Conor Dooley , Krzysztof Kozlowski Subject: [PATCH v5 1/4] dt-bindings: arm: bcm: Add BCM2712 SoC support Date: Thu, 30 May 2024 12:11:58 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 SoC is found on Raspberry Pi 5. Add compatible string to acknowledge its new chipset. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Docum= entation/devicetree/bindings/arm/bcm/bcm2835.yaml index 162a39dab218..e4ff71f006b8 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -23,6 +23,12 @@ properties: - raspberrypi,4-model-b - const: brcm,bcm2711 =20 + - description: BCM2712 based Boards + items: + - enum: + - raspberrypi,5-model-b + - const: brcm,bcm2712 + - description: BCM2835 based Boards items: - enum: --=20 2.35.3 From nobody Tue Dec 16 14:49:35 2025 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3A8E176AAE for ; Thu, 30 May 2024 10:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063916; cv=none; b=YFENUm1cwtkXbKpZRmVRh94c+ckprvPLiZAHxRPy/HuT4qrNF/cXDWDt01rBSLd0B+oFWATj9SGj1WEzY0gC8cUMGmP6Ldxp8dlC6lrXTHI5kHOJt3magdnYckjr+lMw/9BHXlA//kEupFOi11dAsMsJXUgz2ihK82EsijTx4j8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063916; c=relaxed/simple; bh=wEWzUb64Vc7F2Q3LuJkl752STUy+7RzVyEj0EIa99AM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kTCc9RByEoz1TQkyNZC+BFqSMAJrHS1fCCKYTGS4anuz01MV+fkrtXokr5ju2fBesV8zC96U1TY1SROoag3fLuCSEr7knOj5SmFCrT6exp+paz0nX6ba3beLx/ZMik6PCu6oW1jB02cBfA6j555cDI047Mhs207yib3Ni5Nw3aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=DR0iGjrP; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="DR0iGjrP" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-52ae38957e8so811049e87.1 for ; Thu, 30 May 2024 03:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1717063913; x=1717668713; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r4ruLk9Ftm9+QjaAcWOvP48LMnKLjWaDjJj5/jKtjp0=; b=DR0iGjrPS4QuMbaSjqmYLQZncSxGa/Bci/lJQ6iLLPWgCGgY0FNGNyzbSh7KPPu653 RhU+Py9BaZoXN3/zFui+17x/v/3jRhde8np9wFQ36uQMt7CkKgdubkB15gRNZK+uymza E0zmx8dS4TxVyz50mChK5xNaNfdD+8atC9Wef8q97H9lHAA31N4Z5V5Ftfoumj/laVZL P3UpmJMmoWG1PHxCCavUT61JDftfUqknUrmMxj3WQwWXXPLYmZz4WMqfJHU2UWa7TaTh E9hj83bQBPYxwLh7huOSiut2ewgOyLuiwAJP4yFMKz4vOqb6qvrJA5tYmMyZyWswXYDl O/4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717063913; x=1717668713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r4ruLk9Ftm9+QjaAcWOvP48LMnKLjWaDjJj5/jKtjp0=; b=uxY+u/NwYNgVk3nTxaJOrNLH9zGwt/6wCwKGGjYJ48wm/VnZg68NAIpSOjyeubv0j2 Y5Bt/v/PKyR8TheFY4hcotkSVxBr0L5AcllUAfme9Lqs8z8onjrlebg8luU0T35ofrOV nw9fKYe9Gat/mlq40Wjkq8qIgJ3xfG5hMD3F8CPG40BNkSV7DwOb1M4OUdP3Eudxb8vQ MGuAlAUwNrft+yJa6KtqvfJiuGm51KxIqqfemz/FTqw2lL8U101a8gn6GIKEoAj45DMk bBUi25Pcgja9fYhA26awHgsq/3xmRbiuqeJ5v6N+RWxukBzx5G33TmB+QeoaV1o9jjBH nLaA== X-Forwarded-Encrypted: i=1; AJvYcCURs2sid4rY4B8X2aXCoBBfvqjfLNpqZWYYRIW78ScNE1mOK88AWpNNx6a5V6CZM66CQuLMSKUmnL0v9KAhfzLO+1hxZXeiw8/aCFVQ X-Gm-Message-State: AOJu0Yy2eDiNAmwAFCyO1GHLnz8LFT8elqDfV6JpJvTxNASBtipTftYo rPS8DBkIUofv5Yoe9CQrsw7QmhImo1On/+7o/qCzxTZTGzT2z+beDJY9fIyce6c= X-Google-Smtp-Source: AGHT+IHKELWEC1v/nerdFhSEuhPemYySFWzIWZQFDT3Ps3RHOrqqWa9HWxlgaztorNoQN9pOQkFXRQ== X-Received: by 2002:ac2:5496:0:b0:529:1dd4:3e76 with SMTP id 2adb3069b0e04-52b7d480865mr883981e87.59.1717063912908; Thu, 30 May 2024 03:11:52 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a22aa3f8bsm530025a12.22.2024.05.30.03.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:52 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta , Krzysztof Kozlowski Subject: [PATCH v5 2/4] dt-bindings: mmc: Add support for BCM2712 SD host controller Date: Thu, 30 May 2024 12:11:59 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 has an SDHCI capable host interface similar to the one found in other STB chipsets. Add the relevant compatible string. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml = b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index cbd3d6c6c77f..eee6be7a7867 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -20,6 +20,7 @@ properties: - const: brcm,sdhci-brcmstb - items: - enum: + - brcm,bcm2712-sdhci - brcm,bcm74165b0-sdhci - brcm,bcm7445-sdhci - brcm,bcm7425-sdhci --=20 2.35.3 From nobody Tue Dec 16 14:49:35 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B8D0E433B3 for ; Thu, 30 May 2024 10:11:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063917; cv=none; b=Sg6J5xhu78V7+iX5NLjTRIrFDfFQaj3Vn5HWl1UUmYM+b4eNpvjQ/Znuy2ThaMTcir/vAaGWBnPMR83mXdq8zEezmdzAKMRE16+cFRyyh/c10dJSSPpwFUNB19XNuJM/NKOUdGvEXFZXzHs52tqkAS5oQ4MY1llzCTBcoOZlkto= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1717063917; c=relaxed/simple; bh=8YJzfOxtb2vvyOn+74RaUQ/JpxlU3h6ek91ya4OtG8M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=akbcpSIQXciRdPJAQKLuCDHZ8jqD7aC/TCsfo6qyvZiFCF6+qOZkjfgtRSu/g17lpj/BIycA/ccV/6mPS+2dKaWB19+hQ3M28og8ifcrIQ0Bi6c2aLhHB1frzA4LtRI5bx2yJeXmTM4mUB9xgVT6adVOwHoJME8blcU1MpjSthw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=HlD9mdqz; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="HlD9mdqz" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-5755fafa5a7so784020a12.1 for ; Thu, 30 May 2024 03:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1717063914; x=1717668714; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dcRXedB2L/K4Z2DKMFe1HwvDzR0/ipx5LpIH3TLEmVs=; b=HlD9mdqzIQ5SR5sgl+C20VPE/JmjZqiKk9xeiQQMr9T7TG7iTfJhcW86jJ5OI7ptys zev+pcw3MxVPmIznQW4ewsetqAk1XXJo31kX7kpIEk5dCRP8AzdMzBOXCvD1lUQnt+bn suc1eNfmvUk/OcSTt3ypUGZ7EVy5MLxcJEZdcEnTMc1kknibKfWLc6/YJfkLGuu1YYX2 88l3urg8ydY0ZIjqtyzwTd2lEGf2xpJSi37e4OKvzSKXHRCNmvycgmceuRkEP4PcWp6O Km5B2Y3XJ6pl15JtHOot4YtuXqJ++c3nTbBEkGnztPxOjzphSNZju+UxAHJ/CTBJ8wYp ilcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1717063914; x=1717668714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dcRXedB2L/K4Z2DKMFe1HwvDzR0/ipx5LpIH3TLEmVs=; b=w6yUA0tSr/7TJNfcCPF7jlIALfVhaASzjeuehQfjMcW23THdbvF6h6COpZZgYfgzus +CKPDltNrKLmFNa4SVBnQVwm0bDKIPhxp6Apdgo94+qJW7cYW7/nN3G7ojTM+dmXzWDf tvKPANVisBHcoPPzKXRAtjc3IGmb7JotgdHW6bBnKE7zQolpBgzW5yfmwJEMrsF+Xenh U4Ja7v1snjBOirxPCrlN19S37J9tWO5EH6XDWFnPOP3H1ekHPkyJ7pAa6VbYohqWL9sE nlIU+jYNp7XjsyM8wwEvnfjCyD0I7g9vtowwPG5QcYtrn7U/FUKt3EXGIUahqJUZ1RGI 8cog== X-Forwarded-Encrypted: i=1; AJvYcCU8dBdunXUTWCuWK1G9QUvmJR1dA82Qdmu2xKpYcrdVK+9JgIeqeLhuPEavMGdm3N3Kr9v45VLq04/orde9wa/2n9CBhM3G1cwtuyPX X-Gm-Message-State: AOJu0YyrVNAX1a8JfxqnCaaPE9tz9qAPxSiUYn0euMe9X8oQmW2kj6aG HvWmN7ucacQ64sPJIvzj0d78LvHcEjJtwo47kwsX6Kb3tKiCgGR7b0e4ZXU5qPM= X-Google-Smtp-Source: AGHT+IEWYcNoqLpEebhmlHEI02E4bUTWw3UCMc2lMorAyO49bD2UFIdo4HXmbVIbm2kIcWz8uAGOeA== X-Received: by 2002:a50:d69b:0:b0:57a:2ae5:70e7 with SMTP id 4fb4d7f45d1cf-57a2ae57134mr31613a12.7.1717063914160; Thu, 30 May 2024 03:11:54 -0700 (PDT) Received: from localhost (host-87-16-233-11.retail.telecomitalia.it. [87.16.233.11]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-579c2026406sm6815197a12.37.2024.05.30.03.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:53 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v5 3/4] mmc: sdhci-brcmstb: Add BCM2712 support Date: Thu, 30 May 2024 12:12:00 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG register block present on other STB chips. Add support for BCM2712 SD capabilities of this chipset. The silicon is SD Express capable but this driver port does not currently include that feature yet. Based on downstream driver by raspberry foundation maintained kernel. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-brcmstb.c | 60 ++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 9053526fa212..db1c7f5cd5fd 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -30,6 +30,21 @@ =20 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 =20 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) + +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) + +#define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V) +/* Select all SD UHS type I SDR speed above 50MB/s */ +#define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; @@ -38,6 +53,7 @@ struct sdhci_brcmstb_priv { }; =20 struct brcmstb_match_priv { + void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; const unsigned int flags; @@ -168,6 +184,33 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdh= ci_host *host, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } =20 +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *brcmstb_priv =3D sdhci_pltfm_priv(pltfm_host); + u32 reg; + + /* + * If we support a speed that requires tuning, + * then select the delay line PHY as the clock source. + */ + if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC= _CAP_HSE_MASK)) { + reg =3D readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + reg &=3D ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; + reg |=3D SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + } + + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg =3D readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + reg &=3D ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |=3D SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + } +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -200,6 +243,14 @@ static struct sdhci_ops sdhci_brcmstb_ops =3D { .set_uhs_signaling =3D sdhci_set_uhs_signaling, }; =20 +static struct sdhci_ops sdhci_brcmstb_ops_2712 =3D { + .set_clock =3D sdhci_set_clock, + .set_power =3D sdhci_set_power_and_bus_voltage, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_set_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 =3D { .set_clock =3D sdhci_brcmstb_set_clock, .set_bus_width =3D sdhci_set_bus_width, @@ -214,6 +265,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 =3D { .set_uhs_signaling =3D sdhci_brcmstb_set_uhs_signaling, }; =20 +static const struct brcmstb_match_priv match_priv_2712 =3D { + .cfginit =3D sdhci_brcmstb_cfginit_2712, + .ops =3D &sdhci_brcmstb_ops_2712, +}; + static struct brcmstb_match_priv match_priv_7425 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -238,6 +294,7 @@ static struct brcmstb_match_priv match_priv_74165b0 =3D= { }; =20 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] =3D { + { .compatible =3D "brcm,bcm2712-sdhci", .data =3D &match_priv_2712 }, { .compatible =3D "brcm,bcm7425-sdhci", .data =3D &match_priv_7425 }, { .compatible =3D "brcm,bcm7445-sdhci", .data =3D &match_priv_7445 }, { .compatible =3D "brcm,bcm7216-sdhci", .data =3D &match_priv_7216 }, @@ -370,6 +427,9 @@ static int sdhci_brcmstb_probe(struct platform_device *= pdev) (host->mmc->caps2 & MMC_CAP2_HS400_ES)) host->mmc_host_ops.hs400_enhanced_strobe =3D match_priv->hs400es; =20 + if (match_priv->cfginit) + match_priv->cfginit(host); + /* * Supply the existing CAPS, but clear the UHS modes. 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[87.16.233.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a626cda4151sm801020466b.197.2024.05.30.03.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 03:11:55 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v5 4/4] arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 Date: Thu, 30 May 2024 12:12:01 +0200 Message-ID: <874589f6c621036620cca944986e5be7238b4784.1717061147.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta Reviewed-by: Stefan Wahren --- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 64 ++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 283 ++++++++++++++++++ 3 files changed, 348 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/br= oadcom/Makefile index 8b4591ddd27c..92565e9781ad 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -6,6 +6,7 @@ DTC_FLAGS :=3D -@ dtb-$(CONFIG_ARCH_BCM2835) +=3D bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ + bcm2712-rpi-5-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/= boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 index 000000000000..2bdbb6780242 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/dts-v1/; + +#include +#include "bcm2712.dtsi" + +/ { + compatible =3D "raspberrypi,5-model-b", "brcm,bcm2712"; + model =3D "Raspberry Pi 5"; + + aliases { + serial10 =3D &uart10; + }; + + chosen: chosen { + stdout-path =3D "serial10:115200n8"; + }; + + /* Will be filled by the bootloader */ + memory@0 { + device_type =3D "memory"; + reg =3D <0 0 0 0x28000000>; + }; + + sd_io_1v8_reg: sd-io-1v8-reg { + compatible =3D "regulator-gpio"; + regulator-name =3D "vdd-sd-io"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us =3D <5000>; + gpios =3D <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states =3D <1800000 1>, + <3300000 0>; + }; + + sd_vcc_reg: sd-vcc-reg { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&gio_aon 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector + * labeled "UART", i.e. the interface with the system console. + */ +&uart10 { + status =3D "okay"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + vqmmc-supply =3D <&sd_io_1v8_reg>; + vmmc-supply =3D <&sd_vcc_reg>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi new file mode 100644 index 000000000000..bccb7318ce7e --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +#include + +/ { + compatible =3D "brcm,bcm2712"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + interrupt-parent =3D <&gicv2>; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "osc"; + clock-frequency =3D <54000000>; + }; + + clk_vpu: clk-vpu { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <750000000>; + clock-output-names =3D "vpu-clock"; + }; + + clk_uart: clk-uart { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <9216000>; + clock-output-names =3D "uart-clock"; + }; + + clk_emmc2: clk-emmc2 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <200000000>; + clock-output-names =3D "emmc2-clock"; + }; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Source for L1 d/i cache-line-size, cache-sets, cache-size + * https://developer.arm.com/documentation/100798/0401/L1-memory-system/= About-the-L1-memory-system?lang=3Den + * Source for L2 cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100798/0401/L2-memory-system/= About-the-L2-memory-system?lang=3Den + * and for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#b= cm2712 + */ + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x000>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l0>; + + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x100>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l1>; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x200>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l2>; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x300>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l3>; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; //512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=3Den + * Source for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#b= cm2712 + */ + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <0x200000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; // 2MiB(size)/64(line-size)=3D32768ways/16-way s= et + cache-level =3D <3>; + cache-unified; + }; + }; + + psci { + method =3D "smc"; + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + }; + + rmem: reserved-memory { + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; + + atf@0 { + reg =3D <0x0 0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + alloc-ranges =3D <0x0 0x00000000 0x0 0x40000000>; + }; + }; + + soc: soc@107c000000 { + compatible =3D "simple-bus"; + ranges =3D <0x00000000 0x10 0x00000000 0x80000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + sdio1: mmc@fff000 { + compatible =3D "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg =3D <0x00fff000 0x260>, + <0x00fff400 0x200>; + reg-names =3D "host", "cfg"; + interrupts =3D ; + clocks =3D <&clk_emmc2>; + clock-names =3D "sw_sdio"; + mmc-ddr-3_3v; + }; + + system_timer: timer@7c003000 { + compatible =3D "brcm,bcm2835-system-timer"; + reg =3D <0x7c003000 0x1000>; + interrupts =3D , + , + , + ; + clock-frequency =3D <1000000>; + }; + + mailbox: mailbox@7c013880 { + compatible =3D "brcm,bcm2835-mbox"; + reg =3D <0x7c013880 0x40>; + interrupts =3D ; + #mbox-cells =3D <0>; + }; + + local_intc: local-intc@7cd00000 { + compatible =3D "brcm,bcm2836-l1-intc"; + reg =3D <0x7cd00000 0x100>; + }; + + uart10: serial@7d001000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x7d001000 0x200>; + interrupts =3D ; + clocks =3D <&clk_uart>, <&clk_vpu>; + clock-names =3D "uartclk", "apb_pclk"; + arm,primecell-periphid =3D <0x00241011>; + status =3D "disabled"; + }; + + interrupt-controller@7d517000 { + compatible =3D "brcm,bcm7271-l2-intc"; + reg =3D <0x7d517000 0x10>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + + gio_aon: gpio@7d517c00 { + compatible =3D "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg =3D <0x7d517c00 0x40>; + gpio-controller; + #gpio-cells =3D <2>; + brcm,gpio-bank-widths =3D <17 6>; + /* The lack of 'interrupt-controller' property here is intended: + * don't use GIO_AON as an interrupt controller because it will + * clash with the firmware monitoring the PMIC interrupt via the VPU. + */ + }; + + gicv2: interrupt-controller@7fff9000 { + compatible =3D "arm,gic-400"; + reg =3D <0x7fff9000 0x1000>, + <0x7fffa000 0x2000>, + <0x7fffc000 0x2000>, + <0x7fffe000 0x2000>; + interrupt-controller; + #interrupt-cells =3D <3>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + , + ; + }; +}; --=20 2.35.3