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[95.235.217.160]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c7fc4sm191151166b.135.2024.05.10.07.35.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:35:25 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Eric Anholt , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v2 1/4] dt-bindings: arm: bcm: Add BCM2712 SoC support Date: Fri, 10 May 2024 16:35:27 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 SoC is found on Raspberry Pi 5. Add compatible string to acknowledge its new chipset. Signed-off-by: Andrea della Porta Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski Reviewed-by: Stefan Wahren --- Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml b/Docum= entation/devicetree/bindings/arm/bcm/bcm2835.yaml index 162a39dab218..e4ff71f006b8 100644 --- a/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml @@ -23,6 +23,12 @@ properties: - raspberrypi,4-model-b - const: brcm,bcm2711 =20 + - description: BCM2712 based Boards + items: + - enum: + - raspberrypi,5-model-b + - const: brcm,bcm2712 + - description: BCM2835 based Boards items: - enum: --=20 2.35.3 From nobody Mon Feb 9 17:56:53 2026 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9577616F910 for ; Fri, 10 May 2024 14:35:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715351730; cv=none; b=IZr0W38p+nxNcTNajsA5pBy+q9jMElmioFxeFgIEkGmaDHeT4ONku1Cikn/oDZtT68QYJ4PKS5slqg7h/7Ao60jh+ATfzFIqe0cjAlu/aIvdlsz3lE2zSSENdr2Zgb7/Xjskp+dfqTdPClpI3NcPTxrnNsG91NT3VHPbBSOk6f4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715351730; c=relaxed/simple; bh=P92kk6BhCHW3muExoIcLcwA5qcNfUfMADu6b2AJa6JA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pTKzGDayMhWbFnCBawa1FzvdBOCXVZtazIrIQV5SuCVYn/QHOZA+/RYJikkvVDls40S2Em1u3hKsGR+xrCmYIuby5VaykuBtXds7q9wXiau3h5AWoYE27NR427rdMbQ7/KZxZK4TEYUQRYyCg1o0rP2gmDup3QI8rZxySkLdZZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=ROHqB4m2; arc=none smtp.client-ip=209.85.218.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="ROHqB4m2" Received: by mail-ej1-f45.google.com with SMTP id a640c23a62f3a-a599c55055dso549027066b.0 for ; Fri, 10 May 2024 07:35:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1715351727; x=1715956527; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fJE6iq5KMzfXhNp8cO0cJHNPNYoqLhn2RR6V0vH5QBM=; b=ROHqB4m2bwmUAfyqROd6dRtM6BST+qJEOTL/Voj49JLC+hzHMfFPxNQPLN8KCzJCbp +iSdYwX6IRridt4tSm7D3gkea4E9Rm+wFX8VbCvEZs4+ucEePY0NdM3LZd5wx0yJcUUP wonQgTFaz9pLp/dca/DM46ymG/wlOzu0jNupxPMUHVnfiJ2LsP2AfcRNFPSfUVmPs4Jg mXTtA+1cvPm3aXNG88VTB7Vx6d/fO5JjG1QJuwmoOq5flpZXOdhtVBGkvGmEkU4gj4Ec 2pHAFkWbvXSjQDE0eRQwwIA357Nt+VCgRL1dNdYbm0n0vs/MjL4EASrI43DDkyPZdHQp xZTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715351727; x=1715956527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fJE6iq5KMzfXhNp8cO0cJHNPNYoqLhn2RR6V0vH5QBM=; b=Yh/rosIkA6/7Zi2e/1io0tZGujJXFCOVlnA/5QbAeCJsnTEoLHt1byGGuVAaF1pWly k3WR29tu1GfS8hNFBaKtJ6gt5qEl4MxQn1U5HRf5FjuqvWgkS5DFn5crkOMDKGbjTmQ/ DkyteurhrfF452//dFTRW/ncndW1i3wbaPrVWOgXxY6FMjPI/V14MMb+wVpLx6yw7ow7 cB8yfdq78HuvDD9Spp3LMOdfdPJsRapldJ1rDaE2xHt2v/240LbM5QRvLewQoVTM8Mb9 4gc7v5emicXdk0cekS3yrEpLGb7pHvMrV4c8Gvu1503hc+u7Nmvw9g+VmndZpjw33uvT 7Iuw== X-Forwarded-Encrypted: i=1; AJvYcCWbd7SIOk/VL6WaStV592S09BYRPcj+zPZ/aHJJGCBhdBIT2dhvUeM4RoppN4YF4EvuxnCpre8WJ7tLMOWopG4fAc7tGI7HAJ4uyDEn X-Gm-Message-State: AOJu0YzQH3LtRYUPpU3GzitXDAm4c9DXU3gJ9NoFXxH/yTny1uZhVnAc CeUX2KcFlbpiqsEx4lGJsQW7yjELYv0KBWatZb4JFGRal4tlYbl7x4KsI5s+oAA= X-Google-Smtp-Source: AGHT+IGYZyhWDzVYf6DmjGdC71tudm6uLp4GK1JX9oFjlfQU0KYYH9PsgUrcikFgCQeJEwb7baoaaQ== X-Received: by 2002:a50:baeb:0:b0:56e:2ebc:5c4 with SMTP id 4fb4d7f45d1cf-5734d5ceae0mr2015999a12.20.1715351727022; Fri, 10 May 2024 07:35:27 -0700 (PDT) Received: from localhost (host-95-235-217-160.retail.telecomitalia.it. [95.235.217.160]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733bea6a36sm1882673a12.12.2024.05.10.07.35.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:35:26 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Eric Anholt , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v2 2/4] dt-bindings: mmc: Add support for BCM2712 SD host controller Date: Fri, 10 May 2024 16:35:28 +0200 Message-ID: <1f0c4fa62d6849753e2138cce5498693cfc3a230.1715332922.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 has an SDHCI capable host interface similar to the one found in other STB chipsets. Add the relevant compatible string and relative example. Signed-off-by: Andrea della Porta --- .../bindings/mmc/brcm,sdhci-brcmstb.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml = b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index cbd3d6c6c77f..404b75fa7adb 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -13,6 +13,10 @@ maintainers: properties: compatible: oneOf: + - items: + - enum: + - brcm,bcm2712-sdhci + - const: brcm,sdhci-brcmstb - items: - enum: - brcm,bcm7216-sdhci @@ -114,3 +118,22 @@ examples: clocks =3D <&scmi_clk 245>; clock-names =3D "sw_sdio"; }; + + - | + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + mmc@1000fff000 { + compatible =3D "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg =3D <0x10 0x00fff000 0x0 0x260>, + <0x10 0x00fff400 0x0 0x200>; + reg-names =3D "host", "cfg"; + mmc-ddr-3_3v; + interrupts =3D ; + clocks =3D <&clk_emmc2>; + clock-names =3D "sw_sdio"; + }; + }; --=20 2.35.3 From nobody Mon Feb 9 17:56:53 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6C5917089A for ; Fri, 10 May 2024 14:35:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715351732; cv=none; b=pXLWklhWzqiFCSnSHOPLo1VOt3fUm8LM1Ihb7ZWnl+s5Xl0LRBKRda/f+hKO9SJBSVOW3kkfqOtYhG75Vf2mV1wuZdhfs0zDre+qjkZOqjEjEj1i6pTZCOoSAmlTgyMCteqzWhPyLykfN/vktQvvftgAeB4as6lo4Y6AHxYgo6o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715351732; c=relaxed/simple; bh=E7NUkbQ1yYPYk13T3ngej5HA0PiOQTLH4ED/QrY2NS0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PoD4k4Q1jeU67Tuf79I+SQpdedRfFULl6PhhPrAPIbjYTZtXCleucKKVE1Wikmq/R/mIvdnEMe/dmuBq2/MrriMUex3M7t1dRxcqi091n2jb1ho3cC+aztFZm9uRWBxD3ZaMTV36ic6JrSQuEqA4bVHC/i7teYCQPaRBHrx7nZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b=GdEhHa1c; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=suse.com header.i=@suse.com header.b="GdEhHa1c" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-a59a8f0d941so512793866b.2 for ; Fri, 10 May 2024 07:35:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=google; t=1715351728; x=1715956528; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XSzJbe+WTx3YozI8N8SsrWCbxRZkF3THuwWmguwkPbs=; b=GdEhHa1cv6nrOXV8JYxxp53rDF6H/yktwVp2/QCqoPaI2enKBovbKGoUpkeq8QtKyM nqBa1UNy8Ga0t5Ff2C60HZHT3RAJ+EJj+MdLawe0sx56R+5K6VQXwnGRz4wrhQiSSo5k jQkU9aWiQh5gkXby4nq0Pgwu5O3/y6Ij6ilaVSLm7RlR1ADNOqCP3Ytqv2BTPkO8gqpD 6b9q/p5UtBRFmAp6irxWs8MceByrfqJ1hrws5/gXeCFKW0TXrL5ybC/eConPDvK/Q5iD V429b9CUNljPT/8QPJkX+YM1MYeIghVvAKeNCHWoA1NiZLJzXYRQIFHvz4mHMCPzsJlx zOQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1715351728; x=1715956528; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XSzJbe+WTx3YozI8N8SsrWCbxRZkF3THuwWmguwkPbs=; b=oy82ZNEYe9opu2lQ6QGE4VRZkdrY9lg7MvunsXoigasEvX8LJy3vOSBneFy61qhQB9 9y79ZKaDlLU+t2+XAv5m2sPryE2/M/Y+9wgB8DU66Xt5AW9Li0VxPlokRH4DjV3gqZx+ 64x4VhmqfEitKX+sd3gX0ig8oj7C1rtWDC5TKxoq8MvP8YslZ8J86ZSPBP5MgHmWUrTz VvSpRkaaLl01Y9W2UT46WzekevodQqdJCKiXm8Fd7qPSImF/uIElXdi3tzx9mDumvfdH hbB6N6iNA9U/sm9VHLlulMIRFsYV+Jq0zRnNgkK3n2yXPFpeuT3N5dWUGuKBRVQDMm0n cfiw== X-Forwarded-Encrypted: i=1; AJvYcCUNgvjLw305vvG8ccZql/bhVsU4YxbPtuVJ1bz5cBEFAaAUXUTXdbncB4suTzx7Em+okkzvX36qlKCCYTv8BSxJpgjKpzyNvIVHsU0p X-Gm-Message-State: AOJu0YwFdQkfXMduRiqAmfzFQoAer3aGDM1uBzwWVcZ6k/6z2CKps+dt 15uWCIQ0I1RQ+m8z5OsrGJkz8UAYYhSWef2h5BdHxRMV57tmLDaDCAfbtAnSfWk= X-Google-Smtp-Source: AGHT+IHvNWn+a/E+B1THbrDUUwvq+JSMNDMNjIXDVlIPLuJo/eF+Pd3MYBa8HUbGY5Yt7plZIaokhg== X-Received: by 2002:a50:d710:0:b0:572:1589:eb98 with SMTP id 4fb4d7f45d1cf-5734d5b9098mr2123594a12.12.1715351727997; Fri, 10 May 2024 07:35:27 -0700 (PDT) Received: from localhost (host-95-235-217-160.retail.telecomitalia.it. [95.235.217.160]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5733bea65e2sm1878884a12.19.2024.05.10.07.35.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:35:27 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Eric Anholt , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v2 3/4] mmc: sdhci-brcmstb: Add BCM2712 support Date: Fri, 10 May 2024 16:35:29 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG register block present on other STB chips. Add support for BCM2712 SD capabilities of this chipset. The silicon is SD Express capable but this driver port does not currently include that feature yet. Based on downstream driver by raspberry foundation maintained kernel. Signed-off-by: Andrea della Porta --- drivers/mmc/host/sdhci-brcmstb.c | 81 ++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 9053526fa212..13a1017d53c5 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -30,6 +30,24 @@ =20 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 =20 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) + +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) + +#define MMC_CAP_HSE_MASK (MMC_CAP2_HS200_1_8V_SDR | \ + MMC_CAP2_HS200_1_2V_SDR | \ + MMC_CAP2_HS400_1_8V | \ + MMC_CAP2_HS400_1_2V) + +#define MMC_CAP_UHS_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; @@ -38,6 +56,7 @@ struct sdhci_brcmstb_priv { }; =20 struct brcmstb_match_priv { + void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; const unsigned int flags; @@ -139,6 +158,17 @@ static void sdhci_brcmstb_set_clock(struct sdhci_host = *host, unsigned int clock) sdhci_enable_clk(host, clk); } =20 +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char= mode, + unsigned short vdd) +{ + struct mmc_host *mmc =3D host->mmc; + + if (!IS_ERR(mmc->supply.vmmc)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + + sdhci_set_power_noreg(host, mode, vdd); +} + static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { @@ -168,6 +198,40 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdh= ci_host *host, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } =20 +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *brcmstb_priv =3D sdhci_pltfm_priv(pltfm_host); + u32 hsemmc_mask =3D MMC_CAP_HSE_MASK; + u32 uhs_mask =3D MMC_CAP_UHS_MASK; + u32 reg, base_clk_mhz; + + /* + * If we support a speed that requires tuning, + * then select the delay line PHY as the clock source. + */ + if ((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask)) { + reg =3D readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + reg &=3D ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; + reg |=3D SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + } + + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg =3D readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + reg &=3D ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |=3D SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + } + + /* Guesstimate the timer frequency (controller base clock) */ + base_clk_mhz =3D max_t(u32, clk_get_rate(pltfm_host->clk) / (1000 * 1000)= , 1); + reg =3D SDIO_CFG_CQ_CAPABILITY_FMUL | base_clk_mhz; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CQ_CAPABILITY); +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -200,6 +264,14 @@ static struct sdhci_ops sdhci_brcmstb_ops =3D { .set_uhs_signaling =3D sdhci_set_uhs_signaling, }; =20 +static struct sdhci_ops sdhci_brcmstb_ops_2712 =3D { + .set_clock =3D sdhci_set_clock, + .set_power =3D sdhci_brcmstb_set_power, + .set_bus_width =3D sdhci_set_bus_width, + .reset =3D sdhci_reset, + .set_uhs_signaling =3D sdhci_set_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 =3D { .set_clock =3D sdhci_brcmstb_set_clock, .set_bus_width =3D sdhci_set_bus_width, @@ -214,6 +286,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 =3D { .set_uhs_signaling =3D sdhci_brcmstb_set_uhs_signaling, }; =20 +static const struct brcmstb_match_priv match_priv_2712 =3D { + .cfginit =3D sdhci_brcmstb_cfginit_2712, + .ops =3D &sdhci_brcmstb_ops_2712, +}; + static struct brcmstb_match_priv match_priv_7425 =3D { .flags =3D BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -238,6 +315,7 @@ static struct brcmstb_match_priv match_priv_74165b0 =3D= { }; =20 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] =3D { + { .compatible =3D "brcm,bcm2712-sdhci", .data =3D &match_priv_2712 }, { .compatible =3D "brcm,bcm7425-sdhci", .data =3D &match_priv_7425 }, { .compatible =3D "brcm,bcm7445-sdhci", .data =3D &match_priv_7445 }, { .compatible =3D "brcm,bcm7216-sdhci", .data =3D &match_priv_7216 }, @@ -370,6 +448,9 @@ static int sdhci_brcmstb_probe(struct platform_device *= pdev) (host->mmc->caps2 & MMC_CAP2_HS400_ES)) host->mmc_host_ops.hs400_enhanced_strobe =3D match_priv->hs400es; =20 + if (match_priv->cfginit) + match_priv->cfginit(host); + /* * Supply the existing CAPS, but clear the UHS modes. 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[95.235.217.160]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a5a179c822fsm189865966b.138.2024.05.10.07.35.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 May 2024 07:35:28 -0700 (PDT) From: Andrea della Porta To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Ray Jui , Scott Branden , Broadcom internal kernel review list , Ulf Hansson , Adrian Hunter , Kamal Dasu , Al Cooper , Eric Anholt , Stefan Wahren , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Cc: Andrea della Porta Subject: [PATCH v2 4/4] arm64: dts: broadcom: Add support for BCM2712 Date: Fri, 10 May 2024 16:35:30 +0200 Message-ID: <59a3015c3a6f2f0b70a38c030274a163773e7757.1715332922.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The BCM2712 SoC family can be found on Raspberry Pi 5. Add minimal SoC and board (Rpi5 specific) dts file to be able to boot from SD card and use console on debug UART. Signed-off-by: Andrea della Porta --- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 62 ++++ arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 302 ++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712.dtsi diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/br= oadcom/Makefile index 8b4591ddd27c..92565e9781ad 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -6,6 +6,7 @@ DTC_FLAGS :=3D -@ dtb-$(CONFIG_ARCH_BCM2835) +=3D bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ + bcm2712-rpi-5-b.dtb \ bcm2837-rpi-3-a-plus.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/= boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 index 000000000000..b5921437e09f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include +#include "bcm2712.dtsi" + +/ { + compatible =3D "raspberrypi,5-model-b", "brcm,bcm2712"; + model =3D "Raspberry Pi 5"; + + aliases { + serial10 =3D &uart0; + }; + + chosen: chosen { + stdout-path =3D "serial10:115200n8"; + }; + + /* Will be filled by the bootloader */ + memory@0 { + device_type =3D "memory"; + reg =3D <0 0 0x28000000>; + }; + + sd_io_1v8_reg: sd-io-1v8-reg { + compatible =3D "regulator-gpio"; + regulator-name =3D "vdd-sd-io"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-settling-time-us =3D <5000>; + gpios =3D <&gio_aon 3 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x1>, + <3300000 0x0>; + }; + + sd_vcc_reg: sd-vcc-reg { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-sd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&gio_aon 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* The system UART */ +&uart0 { + status =3D "okay"; +}; + +/* SDIO1 is used to drive the SD card */ +&sdio1 { + vqmmc-supply =3D <&sd_io_1v8_reg>; + vmmc-supply =3D <&sd_vcc_reg>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-ddr50; + sd-uhs-sdr104; +}; diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dt= s/broadcom/bcm2712.dtsi new file mode 100644 index 000000000000..398df13148bd --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0 +#include + +/ { + compatible =3D "brcm,bcm2712"; + + #address-cells =3D <2>; + #size-cells =3D <1>; + + interrupt-parent =3D <&gicv2>; + + axi: axi { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + sdio1: mmc@1000fff000 { + compatible =3D "brcm,bcm2712-sdhci", + "brcm,sdhci-brcmstb"; + reg =3D <0x10 0x00fff000 0x260>, + <0x10 0x00fff400 0x200>; + reg-names =3D "host", "cfg"; + interrupts =3D ; + clocks =3D <&clk_emmc2>; + clock-names =3D "sw_sdio"; + mmc-ddr-3_3v; + }; + + gicv2: interrupt-controller@107fff9000 { + interrupt-controller; + #interrupt-cells =3D <3>; + compatible =3D "arm,gic-400"; + reg =3D <0x10 0x7fff9000 0x1000>, + <0x10 0x7fffa000 0x2000>, + <0x10 0x7fffc000 0x2000>, + <0x10 0x7fffe000 0x2000>; + interrupts =3D ; + }; + }; + + clocks { + /* The oscillator is the root of the clock tree. */ + clk_osc: clk-osc { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "osc"; + clock-frequency =3D <54000000>; + }; + + clk_vpu: clk-vpu { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <750000000>; + clock-output-names =3D "vpu-clock"; + }; + + clk_uart: clk-uart { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <9216000>; + clock-output-names =3D "uart-clock"; + }; + + clk_emmc2: clk-emmc2 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <200000000>; + clock-output-names =3D "emmc2-clock"; + }; + }; + + cpus: cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* Source for d/i cache-line-size, cache-sets, cache-size + * https://developer.arm.com/documentation/100798/0401 + * /L1-memory-system/About-the-L1-memory-system?lang=3Den + */ + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x000>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l0>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x100>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l1>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x200>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l2>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a76"; + reg =3D <0x300>; + enable-method =3D "psci"; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <256>; // 64KiB(size)/64(line-size)=3D1024ways/4-way s= et + next-level-cache =3D <&l2_cache_l3>; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100798/0401 + * /L2-memory-system/About-the-L2-memory-system?lang=3Den + * and for cache-size: + * https://www.raspberrypi.com/documentation/computers + * /processors.html#bcm2712 + */ + l2_cache_l0: l2-cache-l0 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible =3D "cache"; + cache-size =3D <0x80000>; + cache-line-size =3D <128>; + cache-sets =3D <1024>; // 512KiB(size)/64(line-size)=3D8192ways/8-way s= et + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + /* Source for cache-line-size and cache-sets: + * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=3Den + * Source for cache-size: + * https://www.raspberrypi.com/documentation/computers/processors.html#b= cm2712 + */ + l3_cache: l3-cache { + compatible =3D "cache"; + cache-size =3D <0x200000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; // 2MiB(size)/64(line-size)=3D32768ways/16-way s= et + cache-level =3D <3>; + cache-unified; + }; + }; + + psci { + method =3D "smc"; + compatible =3D "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + cpu_on =3D <0xc4000003>; + cpu_suspend =3D <0xc4000001>; + cpu_off =3D <0x84000002>; + }; + + rmem: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <1>; + ranges; + + atf@0 { + reg =3D <0x0 0x0 0x80000>; + no-map; + }; + + cma: linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x4000000>; /* 64MB */ + reusable; + linux,cma-default; + alloc-ranges =3D <0x0 0x00000000 0x40000000>; + }; + }; + + soc: soc@107c000000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x7c000000 0x10 0x7c000000 0x04000000>; + /* Emulate a contiguous 30-bit address range for DMA */ + dma-ranges =3D <0xc0000000 0x00 0x00000000 0x40000000>, + <0x7c000000 0x10 0x7c000000 0x04000000>; + + system_timer: timer@7c003000 { + compatible =3D "brcm,bcm2835-system-timer"; + reg =3D <0x7c003000 0x1000>; + interrupts =3D , + , + , + ; + clock-frequency =3D <1000000>; + }; + + mailbox: mailbox@7c013880 { + compatible =3D "brcm,bcm2835-mbox"; + reg =3D <0x7c013880 0x40>; + interrupts =3D ; + #mbox-cells =3D <0>; + }; + + local_intc: local-intc@7cd00000 { + compatible =3D "brcm,bcm2836-l1-intc"; + reg =3D <0x7cd00000 0x100>; + }; + + uart0: serial@7d001000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x7d001000 0x200>; + interrupts =3D ; + clocks =3D <&clk_uart>, <&clk_vpu>; + clock-names =3D "uartclk", "apb_pclk"; + arm,primecell-periphid =3D <0x00241011>; + status =3D "disabled"; + }; + + interrupt-controller@7d517000 { + compatible =3D "brcm,bcm7271-l2-intc"; + reg =3D <0x7d517000 0x10>; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + status =3D "disabled"; + }; + + gio_aon: gpio@7d517c00 { + compatible =3D "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; + reg =3D <0x7d517c00 0x40>; + gpio-controller; + #gpio-cells =3D <2>; + // Don't use GIO_AON as an interrupt controller because it will + // clash with the firmware monitoring the PMIC interrupt via the VPU. + brcm,gpio-bank-widths =3D <17 6>; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + /* This only applies to the ARMv7 stub */ + arm,cpu-registers-not-fw-configured; + }; +}; --=20 2.35.3