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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2024 20:17:23.6320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8056d35b-8511-4eca-e254-08dc6564b7ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A105.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4117 Content-Type: text/plain; charset="utf-8" In an effort to support MBM and MBA tests for AMD, renaming for variable and functions to generic names. For Intel, the memory controller is called Integrated Memory Controllers (IMC). For AMD, it is called Unified Memory Controller (UMC). No functional change. Signed-off-by: Babu Moger --- tools/testing/selftests/resctrl/resctrl_val.c | 59 ++++++++++--------- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index 5a49f07a6c85..a30cfcff605f 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -60,7 +60,7 @@ struct imc_counter_config { }; =20 static char mbm_total_path[1024]; -static int imcs; +static int mcs; static struct imc_counter_config imc_counters_config[MAX_IMCS][2]; =20 void membw_initialize_perf_event_attr(int i, int j) @@ -211,15 +211,16 @@ static int read_from_imc_dir(char *imc_dir, int count) } =20 /* - * A system can have 'n' number of iMC (Integrated Memory Controller) - * counters, get that 'n'. For each iMC counter get it's type and config. + * A system can have 'n' number of iMC (Integrated Memory Controller for + * Intel) counters, get that 'n'. In case of AMD it is called UMC (Unified + * Memory Controller). For each iMC/UMC counter get it's type and config. * Also, each counter has two configs, one for read and the other for writ= e. * A config again has two parts, event and umask. * Enumerate all these details into an array of structures. * * Return: >=3D 0 on success. < 0 on failure. */ -static int num_of_imcs(void) +static int num_of_mem_controllers(void) { char imc_dir[512], *temp; unsigned int count =3D 0; @@ -275,25 +276,25 @@ static int num_of_imcs(void) return count; } =20 -static int initialize_mem_bw_imc(void) +static int initialize_mem_bw_mc(void) { - int imc, j; + int mc, j; =20 - imcs =3D num_of_imcs(); - if (imcs <=3D 0) - return imcs; + mcs =3D num_of_mem_controllers(); + if (mcs <=3D 0) + return mcs; =20 /* Initialize perf_event_attr structures for all iMC's */ - for (imc =3D 0; imc < imcs; imc++) { + for (mc =3D 0; mc < mcs; mc++) { for (j =3D 0; j < 2; j++) - membw_initialize_perf_event_attr(imc, j); + membw_initialize_perf_event_attr(mc, j); } =20 return 0; } =20 /* - * get_mem_bw_imc: Memory band width as reported by iMC counters + * get_mem_bw_mc: Memory band width as reported by iMC counters * @cpu_no: CPU number that the benchmark PID is binded to * @bw_report: Bandwidth report type (reads, writes) * @@ -302,40 +303,40 @@ static int initialize_mem_bw_imc(void) * * Return: =3D 0 on success. < 0 on failure. */ -static int get_mem_bw_imc(int cpu_no, char *bw_report, float *bw_imc) +static int get_mem_bw_mc(int cpu_no, char *bw_report, float *bw_imc) { float reads, writes, of_mul_read, of_mul_write; - int imc, j, ret; + int mc, j, ret; =20 /* Start all iMC counters to log values (both read and write) */ reads =3D 0, writes =3D 0, of_mul_read =3D 1, of_mul_write =3D 1; - for (imc =3D 0; imc < imcs; imc++) { + for (mc =3D 0; mc < mcs; mc++) { for (j =3D 0; j < 2; j++) { - ret =3D open_perf_event(imc, cpu_no, j); + ret =3D open_perf_event(mc, cpu_no, j); if (ret) return -1; } for (j =3D 0; j < 2; j++) - membw_ioctl_perf_event_ioc_reset_enable(imc, j); + membw_ioctl_perf_event_ioc_reset_enable(mc, j); } =20 sleep(1); =20 /* Stop counters after a second to get results (both read and write) */ - for (imc =3D 0; imc < imcs; imc++) { + for (mc =3D 0; mc < mcs; mc++) { for (j =3D 0; j < 2; j++) - membw_ioctl_perf_event_ioc_disable(imc, j); + membw_ioctl_perf_event_ioc_disable(mc, j); } =20 /* * Get results which are stored in struct type imc_counter_config * Take over flow into consideration before calculating total b/w */ - for (imc =3D 0; imc < imcs; imc++) { + for (mc =3D 0; mc < mcs; mc++) { struct imc_counter_config *r =3D - &imc_counters_config[imc][READ]; + &imc_counters_config[mc][READ]; struct imc_counter_config *w =3D - &imc_counters_config[imc][WRITE]; + &imc_counters_config[mc][WRITE]; =20 if (read(r->fd, &r->return_value, sizeof(struct membw_read_format)) =3D=3D -1) { @@ -368,9 +369,9 @@ static int get_mem_bw_imc(int cpu_no, char *bw_report, = float *bw_imc) writes +=3D w->return_value.value * of_mul_write * SCALE; } =20 - for (imc =3D 0; imc < imcs; imc++) { - close(imc_counters_config[imc][READ].fd); - close(imc_counters_config[imc][WRITE].fd); + for (mc =3D 0; mc < mcs; mc++) { + close(imc_counters_config[mc][READ].fd); + close(imc_counters_config[mc][WRITE].fd); } =20 if (strcmp(bw_report, "reads") =3D=3D 0) { @@ -598,7 +599,7 @@ static int measure_vals(const struct user_params *upara= ms, unsigned long *bw_resc_start) { unsigned long bw_resc, bw_resc_end; - float bw_imc; + float bw_mc; int ret; =20 /* @@ -608,7 +609,7 @@ static int measure_vals(const struct user_params *upara= ms, * Compare the two values to validate resctrl value. * It takes 1sec to measure the data. */ - ret =3D get_mem_bw_imc(uparams->cpu, param->bw_report, &bw_imc); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2024 20:17:30.5941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4542e6ab-a6a3-4536-391d-08dc6564bc15 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5645 Content-Type: text/plain; charset="utf-8" Detect the vendor and pass the sysfs name for the vendor for searching the controller information. Signed-off-by: Babu Moger --- tools/testing/selftests/resctrl/resctrl_val.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index a30cfcff605f..e3b09128ec3d 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -224,14 +224,24 @@ static int num_of_mem_controllers(void) { char imc_dir[512], *temp; unsigned int count =3D 0; + int ret, vendor, size; struct dirent *ep; - int ret; + char *sysfs_name; DIR *dp; =20 + vendor =3D get_vendor(); + if (vendor =3D=3D ARCH_INTEL) { + sysfs_name =3D UNCORE_IMC; + size =3D sizeof(UNCORE_IMC); + } else { + perror("Unsupported Vendor!\n"); + return -1; + } + dp =3D opendir(DYN_PMU_PATH); if (dp) { while ((ep =3D readdir(dp))) { - temp =3D strstr(ep->d_name, UNCORE_IMC); + temp =3D strstr(ep->d_name, sysfs_name); if (!temp) continue; =20 @@ -242,7 +252,7 @@ static int num_of_mem_controllers(void) * well and hence the last underscore character in * uncore_imc'_' need not be counted. */ - temp =3D temp + sizeof(UNCORE_IMC); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2024 20:17:37.6401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e890d961-75b3-4ba8-5a3d-08dc6564c048 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A102.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7160 Content-Type: text/plain; charset="utf-8" Add support to read UMC (Unified Memory Controller) perf events to compare the numbers with QoS monitor for AMD. Signed-off-by: Babu Moger --- tools/testing/selftests/resctrl/resctrl_val.c | 67 ++++++++++++++++--- 1 file changed, 59 insertions(+), 8 deletions(-) diff --git a/tools/testing/selftests/resctrl/resctrl_val.c b/tools/testing/= selftests/resctrl/resctrl_val.c index e3b09128ec3d..d90d3196d7b5 100644 --- a/tools/testing/selftests/resctrl/resctrl_val.c +++ b/tools/testing/selftests/resctrl/resctrl_val.c @@ -11,6 +11,7 @@ #include "resctrl.h" =20 #define UNCORE_IMC "uncore_imc" +#define AMD_UMC "amd_umc" #define READ_FILE_NAME "events/cas_count_read" #define WRITE_FILE_NAME "events/cas_count_write" #define DYN_PMU_PATH "/sys/bus/event_source/devices" @@ -146,6 +147,47 @@ static int open_perf_event(int i, int cpu_no, int j) return 0; } =20 +/* Get type and config (read and write) of an UMC counter */ +static int read_from_umc_dir(char *umc_dir, int count) +{ + char umc_counter_type[PATH_MAX]; + FILE *fp; + + /* Get type of iMC counter */ + sprintf(umc_counter_type, "%s%s", umc_dir, "type"); + fp =3D fopen(umc_counter_type, "r"); + if (!fp) { + ksft_perror("Failed to open imc counter type file"); + return -1; + } + + if (fscanf(fp, "%u", &imc_counters_config[count][READ].type) <=3D 0) { + ksft_perror("Could not get imc type"); + fclose(fp); + return -1; + } + + fclose(fp); + + imc_counters_config[count][WRITE].type =3D + imc_counters_config[count][READ].type; + + /* + * Setup the event and umasks for UMC events + * Number of CAS commands sent for reads: + * EventCode =3D 0x0a, umask =3D 0x1 + * Number of CAS commands sent for writes: + * EventCode =3D 0x0a, umask =3D 0x2 + */ + imc_counters_config[count][READ].event =3D 0xa; + imc_counters_config[count][READ].umask =3D 0x1; + + imc_counters_config[count][WRITE].event =3D 0xa; + imc_counters_config[count][WRITE].umask =3D 0x2; + + return 0; +} + /* Get type and config (read and write) of an iMC counter */ static int read_from_imc_dir(char *imc_dir, int count) { @@ -233,6 +275,9 @@ static int num_of_mem_controllers(void) if (vendor =3D=3D ARCH_INTEL) { sysfs_name =3D UNCORE_IMC; size =3D sizeof(UNCORE_IMC); + } else if (vendor =3D=3D ARCH_AMD) { + sysfs_name =3D AMD_UMC; + size =3D sizeof(AMD_UMC); } else { perror("Unsupported Vendor!\n"); return -1; @@ -246,11 +291,12 @@ static int num_of_mem_controllers(void) continue; =20 /* - * imc counters are named as "uncore_imc_", hence - * increment the pointer to point to . Note that - * sizeof(UNCORE_IMC) would count for null character as - * well and hence the last underscore character in - * uncore_imc'_' need not be counted. + * Intel imc counters are named as "uncore_imc_", + * hence increment the pointer to point to . + * Note that sizeof(UNCORE_IMC) would count for null + * character as well and hence the last underscore + * character in uncore_imc'_' need not be counted. + * For AMD, it will be amd_umc_. */ temp =3D temp + size; =20 @@ -262,7 +308,11 @@ static int num_of_mem_controllers(void) if (temp[0] >=3D '0' && temp[0] <=3D '9') { sprintf(imc_dir, "%s/%s/", DYN_PMU_PATH, ep->d_name); - ret =3D read_from_imc_dir(imc_dir, count); + if (vendor =3D=3D ARCH_INTEL) + ret =3D read_from_imc_dir(imc_dir, count); + else + ret =3D read_from_umc_dir(imc_dir, count); + if (ret) { closedir(dp); =20 @@ -273,8 +323,9 @@ static int num_of_mem_controllers(void) } closedir(dp); if (count =3D=3D 0) { - ksft_print_msg("Unable to find iMC counters\n"); - + ksft_print_msg("Unable to find iMC/UMC counters\n"); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Apr 2024 20:17:44.5377 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 378762d9-7e9f-4607-d8f1-08dc6564c464 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A108.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7121 Content-Type: text/plain; charset="utf-8" Enable MBA/MBM tests if UMC (Unified Memory Controller) support is available on the system. Tests will be skipped otherwise. Update noncont_cat_run_test to check for vendor. AMD supports non contiguous CBM masks but does not report it via CPUID. Signed-off-by: Babu Moger --- tools/testing/selftests/resctrl/cat_test.c | 2 +- tools/testing/selftests/resctrl/mba_test.c | 1 - tools/testing/selftests/resctrl/mbm_test.c | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/sel= ftests/resctrl/cat_test.c index 4cb991be8e31..b682eaf65bfd 100644 --- a/tools/testing/selftests/resctrl/cat_test.c +++ b/tools/testing/selftests/resctrl/cat_test.c @@ -314,7 +314,7 @@ static int noncont_cat_run_test(const struct resctrl_te= st *test, else return -EINVAL; =20 - if (sparse_masks !=3D ((ecx >> 3) & 1)) { + if ((get_vendor() =3D=3D ARCH_INTEL) && sparse_masks !=3D ((ecx >> 3) & 1= )) { ksft_print_msg("CPUID output doesn't match 'sparse_masks' file content!\= n"); return 1; } diff --git a/tools/testing/selftests/resctrl/mba_test.c b/tools/testing/sel= ftests/resctrl/mba_test.c index 7946e32e85c8..353054724fa7 100644 --- a/tools/testing/selftests/resctrl/mba_test.c +++ b/tools/testing/selftests/resctrl/mba_test.c @@ -177,7 +177,6 @@ static bool mba_feature_check(const struct resctrl_test= *test) struct resctrl_test mba_test =3D { .name =3D "MBA", .resource =3D "MB", - .vendor_specific =3D ARCH_INTEL, .feature_check =3D mba_feature_check, .run_test =3D mba_run_test, }; diff --git a/tools/testing/selftests/resctrl/mbm_test.c b/tools/testing/sel= ftests/resctrl/mbm_test.c index d67ffa3ec63a..f2223315b5b8 100644 --- a/tools/testing/selftests/resctrl/mbm_test.c +++ b/tools/testing/selftests/resctrl/mbm_test.c @@ -147,7 +147,6 @@ static bool mbm_feature_check(const struct resctrl_test= *test) struct resctrl_test mbm_test =3D { .name =3D "MBM", .resource =3D "MB", - .vendor_specific =3D ARCH_INTEL, .feature_check =3D mbm_feature_check, .run_test =3D mbm_run_test, }; --=20 2.34.1