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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 08:41:18.9024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a33af9b-a197-4a9c-2bab-08dc63712568 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4111 Content-Type: text/plain; charset="utf-8" There are some other drivers also need to use the MSR_K7_HWCR_CPB_DIS_BIT for CPB control bit, so it makes sense to move the definition to a common header file to allow other driver to use it. No intentional functional impact. Suggested-by: Gautham Ranjal Shenoy Signed-off-by: Perry Yuan Acked-by: Rafael J. Wysocki Acked-by: Huang Rui --- arch/x86/include/asm/msr-index.h | 2 ++ drivers/cpufreq/acpi-cpufreq.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index e72c2b872957..8738a7b3917d 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -782,6 +782,8 @@ #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 +#define MSR_K7_HWCR_CPB_DIS_BIT 25 +#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) =20 /* K6 MSRs */ #define MSR_K6_WHCR 0xc0000082 diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c index 37f1cdf46d29..2fc82831bddd 100644 --- a/drivers/cpufreq/acpi-cpufreq.c +++ b/drivers/cpufreq/acpi-cpufreq.c @@ -50,8 +50,6 @@ enum { #define AMD_MSR_RANGE (0x7) #define HYGON_MSR_RANGE (0x7) =20 -#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) - struct acpi_cpufreq_data { unsigned int resume; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 08:41:22.4189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f346ccd3-6b52-4ea1-206b-08dc63712783 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DE.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4077 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Add one global `global_params` to represent CPU Performance Boost(cpb) state for cpu frequency scaling, both active and passive modes all can support CPU cores frequency boosting control which is based on the BIOS setting, while BIOS turn on the "Core Performance Boost", it will allow OS control each core highest perf limitation from OS side. The active, guided and passive modes of the amd-pstate driver can support frequency boost control when the "Core Performance Boost" (CPB) feature is enabled in the BIOS. When enabled in BIOS, the user has an option at runtime to allow/disallow the cores from operating in the boost frequency range. Add an amd_pstate_global_params object to record whether CPB is enabled in BIOS, and if it has been activated by the user Reported-by: Artem S. Tashkinov" Cc: Oleksandr Natalenko Closes: https://bugzilla.kernel.org/show_bug.cgi?id=3D217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 39 +++++++++++++++++++++++++++--------- include/linux/amd-pstate.h | 13 ++++++++++++ 2 files changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 83a29b257794..3d86cd7c9073 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -68,6 +68,8 @@ static int cppc_state =3D AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore =3D true; static struct quirk_entry *quirks; +struct amd_pstate_global_params amd_pstate_global_params; +EXPORT_SYMBOL_GPL(amd_pstate_global_params); =20 /* * AMD Energy Preference Performance (EPP) @@ -665,18 +667,27 @@ static int amd_pstate_set_boost(struct cpufreq_policy= *policy, int state) return 0; } =20 -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - u32 highest_perf, nominal_perf; + u64 boost_val; + int ret; =20 - highest_perf =3D READ_ONCE(cpudata->highest_perf); - nominal_perf =3D READ_ONCE(cpudata->nominal_perf); + ret =3D rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); + return ret; + } =20 - if (highest_perf <=3D nominal_perf) - return; + amd_pstate_global_params.cpb_supported =3D !(boost_val & MSR_K7_HWCR_CPB_= DIS); + + if (amd_pstate_global_params.cpb_supported) { + cpudata->boost_supported =3D true; + current_pstate_driver->boost_enabled =3D true; + } =20 - cpudata->boost_supported =3D true; - current_pstate_driver->boost_enabled =3D true; + amd_pstate_global_params.cpb_boost =3D amd_pstate_global_params.cpb_suppo= rted; + + return ret; } =20 static void amd_perf_ctl_reset(unsigned int cpu) @@ -900,6 +911,11 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *= policy) =20 amd_pstate_init_prefcore(cpudata); =20 + /* initialize cpu cores boot state */ + ret =3D amd_pstate_boost_init(cpudata); + if (ret) + goto free_cpudata1; + ret =3D amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -956,7 +972,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *p= olicy) =20 policy->driver_data =3D cpudata; =20 - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf =3D amd_pstate_adjust_perf; =20 @@ -1363,6 +1378,11 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_po= licy *policy) =20 amd_pstate_init_prefcore(cpudata); =20 + /* initialize cpu cores boot state */ + ret =3D amd_pstate_boost_init(cpudata); + if (ret) + goto free_cpudata1; + ret =3D amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1417,7 +1437,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_pol= icy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); =20 return 0; =20 diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 6b832153a126..c5e41de65f70 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -134,4 +134,17 @@ struct quirk_entry { u32 lowest_freq; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 08:41:26.3018 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b96feac0-a9b5-4458-9b33-08dc637129d3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8562 Content-Type: text/plain; charset="utf-8" From: Perry Yuan With this new sysfs entry `cpb_boost`created, user can change CPU boost state dynamically under `active`, `guided` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changing. 0): check current boost state cat /sys/devices/system/cpu/amd_pstate/cpb_boost 1): disable CPU boost sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" 2): enable CPU boost sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 99 ++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3d86cd7c9073..49eeb38fcf20 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1291,6 +1291,103 @@ static ssize_t prefcore_show(struct device *dev, return sysfs_emit(buf, "%s\n", str_enabled_disabled(amd_pstate_prefcore)); } =20 +static int amd_cpu_boost_update(struct amd_cpudata *cpudata, u32 on) +{ + struct cpufreq_policy *policy =3D cpufreq_cpu_acquire(cpudata->cpu); + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf, nominal_freq, max_freq; + int ret; + + if (!policy) + return -ENODATA; + + highest_perf =3D READ_ONCE(cpudata->highest_perf); + nominal_perf =3D READ_ONCE(cpudata->nominal_perf); + nominal_freq =3D READ_ONCE(cpudata->nominal_freq); + max_freq =3D READ_ONCE(cpudata->max_freq); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value =3D READ_ONCE(cpudata->cppc_req_cached); + + value &=3D ~GENMASK_ULL(7, 0); + value |=3D on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + + } else { + perf_ctrls.max_perf =3D on ? highest_perf : nominal_perf; + ret =3D cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq =3D max_freq; + else + policy->cpuinfo.max_freq =3D nominal_freq; + + policy->max =3D policy->cpuinfo.max_freq; + + if (cppc_state =3D=3D AMD_PSTATE_PASSIVE) { + ret =3D freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + } + + cpufreq_cpu_release(policy); + + return ret; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", amd_pstate_global_params.cpb_boost); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute= *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu; + + mutex_lock(&amd_pstate_driver_lock); + if (!amd_pstate_global_params.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + ret =3D kstrtobool(buf, &new_state); + if (ret) + return -EINVAL; + + amd_pstate_global_params.cpb_boost =3D !!new_state; + + for_each_present_cpu(cpu) { + + struct cpufreq_policy *policy =3D cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata =3D policy->driver_data; + + if (!cpudata) { + pr_err("cpudata is NULL\n"); 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Tue, 23 Apr 2024 03:41:26 -0500 From: Perry Yuan To: , , , , , , CC: , , , , , Subject: [PATCH v7 4/6] cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off Date: Tue, 23 Apr 2024 16:40:57 +0800 Message-ID: <3548a1e1056d9d08286da8ca1c68da23c6672ee3.1713861200.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DB:EE_|BL3PR12MB6570:EE_ X-MS-Office365-Filtering-Correlation-Id: 51bd85e5-33ed-402a-1fb8-08dc63712be0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?yr+Z/N/kaUYWLRRumcdLxahOR+02CPw3lHHYiDbuLl14eFmuRdEWW3If1cR/?= =?us-ascii?Q?dI+H9ejefE4XIGxl4BfD5QLFujc139MlEH5eqgKFCX0g1P94zjZo0uUhp+My?= =?us-ascii?Q?3hHpnuTydkr8i1age4hvt/1n5hrTjpDAa0NZVRLf30uu5RuyJ6zhW+ZhqADs?= =?us-ascii?Q?ACgcym9ZiyJVx6jn3uli0KTH3mmec2R+gtvbzCKIDlzIZPXXQTlsqDwgfgzv?= =?us-ascii?Q?lD2BEuRDH02kfPpiJfd8SZYV+bc0cCQBqcy7GV7DhACSgwubdxpYPQaS/A/v?= =?us-ascii?Q?S5ZJ4H3q2xNoc0AZmnXUh2bk4KhJGEDJfqiPwhyHiwJIT4AL6UoHyUPiUD2F?= =?us-ascii?Q?j7s6fLu+fTXlBdVSqoUhpUr5Vzd4/pW2xnwqvNqnGslUs1GWOjbMgaK8RxJM?= =?us-ascii?Q?fiOB9LXLHnhNLBViQr4YaQZyGgNQUuVRcEXe+Hgm7ddVf1bsT1tOI9+kuk3p?= =?us-ascii?Q?Ncd66XwFBS7XrGkT+fp/jY8J16xSnBdB3S5kcjeJTx2qXPSI03LD1yHWpp8A?= =?us-ascii?Q?jywD/t5r/s4OMh6Oxnpi+e/pMkNhxXvC4Z+o5pd6J/BzMbNAzBBgViCTCSCL?= =?us-ascii?Q?8AxkXYY4tFYHVgncieRSeRs79zz7mwuY0w5hX/dVeuwYgQ09ugv3T5/brHcx?= =?us-ascii?Q?snGagVw46SJuyy/2IiBxIifBjNW8y3w0hFrPyoCxTNS9ePThRcKb6AuZHyea?= =?us-ascii?Q?zxEsCkJcgJ0gBkDPviV30+wMj3xolDvs0FHB5FEEw6qrZQsPsUY1pUyBYp93?= =?us-ascii?Q?2sL4w+rGoYjXv2ri+6lwkRhBPxnNNXbmauh+sB7YfdKCqEzDYsTW37ePL9iK?= =?us-ascii?Q?ZXYfiGHpMkPgIDBt8tEeLqpSGCgvC7pNah/M7VVwUjxZatU5SuOAuqzYaInB?= =?us-ascii?Q?HNzm2SCVzH6TbLY98/qFjWsFI5+WrotZZ5ZTi8wsTaaxswGe+t7U36GToVV0?= =?us-ascii?Q?7uH4AIo46zpz56e1KsQOJVgaG5Tfpth+9SCRBhEvZYa/Iqe134kiTXRSuDZh?= =?us-ascii?Q?szc4aK53/8Ieluo1ADg40W2jeNODITHvpOJzT7Dbncc5NtCggPI5+s2XI+gu?= =?us-ascii?Q?6VHob/LNBXBJtlwg6mNl5PgpaZ2m+o9kdiq/8sFBTo3byCDOyQX83XfandHW?= =?us-ascii?Q?tSa42Zv/Aoy1Cve/eQdTElzLxb3w0NWAxvOQK1hBgL5yZVfMlFL3zNIV0BY2?= =?us-ascii?Q?f8KCyNdsQecrjLWkaeldmxYVObJ1AQ2fN4Y4bHxpOAy/l2blClc4wkhCKn1V?= =?us-ascii?Q?HILtK2kKeYu45xO0gZKiu0B9mm0ylPNHl6Hckt8LDQK4bMDxHWOVu3nOr7ph?= =?us-ascii?Q?7207hGjA4DNIQUC7sLE4qFaAPNoP78uKdNhdwpCQxqlMM9U0p40MVsP7Ert2?= =?us-ascii?Q?tUyt1gkKdRx21X/RR34Mpr7ZlNXV?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 08:41:29.7549 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51bd85e5-33ed-402a-1fb8-08dc63712be0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6570 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Select the min perf to fix the highest perf value while update pstate CPPC request MSR register, here we need to limit the max perf value when CPU boost is disabled in case of that highest perf value in the MSR will be reset to original highest perf value which cause the BOOST control failed. Signed-off-by: Perry Yuan Acked-by: Huang Rui --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 49eeb38fcf20..22e5b84dbe28 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -476,6 +476,7 @@ static void amd_pstate_update(struct amd_cpudata *cpuda= ta, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) { u64 prev =3D READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf =3D READ_ONCE(cpudata->nominal_perf); u64 value =3D prev; =20 min_perf =3D clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, @@ -495,6 +496,10 @@ static void amd_pstate_update(struct amd_cpudata *cpud= ata, u32 min_perf, value &=3D ~AMD_CPPC_DES_PERF(~0L); value |=3D AMD_CPPC_DES_PERF(des_perf); =20 + /* limit the max perf when core performance boost feature is disabled */ + if (!amd_pstate_global_params.cpb_boost) + max_perf =3D min_t(unsigned long, nominal_perf, max_perf); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 08:41:33.4267 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f7d1ea91-ac32-4698-ca03-08dc63712e12 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DB.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6365 Content-Type: text/plain; charset="utf-8" From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P= -state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/ad= min-guide/pm/amd-pstate.rst index 1e0d101b020a..82fbd01da658 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -440,6 +440,17 @@ control its functionality at the system level. They a= re located in the This attribute is read-only to check the state of preferred core s= et by the kernel parameter. =20 +``cpb_boost`` + Specifies whether core performance boost is requested to be enable= d or disabled + If core performance boost is disabled while a core is in a boosted= P-state, the + core automatically transitions to the highest performance non-boos= ted P-state. + AMD Core Performance Boost(CPB) is controlled by this new attribut= e file which + allow user to change all cores frequency boosting state. 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Tue, 23 Apr 2024 08:41:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF000099DC.mail.protection.outlook.com (10.167.17.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7519.19 via Frontend Transport; Tue, 23 Apr 2024 08:41:36 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 23 Apr 2024 03:41:32 -0500 From: Perry Yuan To: , , , , , , CC: , , , , , Subject: [PATCH v7 6/6] cpufreq: amd-pstate-ut: support new cpb boost control interface Date: Tue, 23 Apr 2024 16:40:59 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DC:EE_|SN7PR12MB7451:EE_ X-MS-Office365-Filtering-Correlation-Id: e2958de3-5bae-4203-e5db-08dc63712ff5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2024 08:41:36.6085 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2958de3-5bae-4203-e5db-08dc63712ff5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DC.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7451 Content-Type: text/plain; charset="utf-8" As the new CPB boost control is enabled, pstate unit test needs to remove legacy `boost_supported` check and start to use new CPB boost control interface `amd_pstate_global_params.cpb_boost`. Signed-off-by: Perry Yuan Acked-by: Huang Rui --- drivers/cpufreq/amd-pstate-ut.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cpufreq/amd-pstate-ut.c b/drivers/cpufreq/amd-pstate-u= t.c index f04ae67dda37..b3601b0e6dd3 100644 --- a/drivers/cpufreq/amd-pstate-ut.c +++ b/drivers/cpufreq/amd-pstate-ut.c @@ -226,7 +226,7 @@ static void amd_pstate_ut_check_freq(u32 index) goto skip_test; } =20 - if (cpudata->boost_supported) { + if (amd_pstate_global_params.cpb_boost) { if ((policy->max =3D=3D cpudata->max_freq) || (policy->max =3D=3D cpudata->nominal_freq)) amd_pstate_ut_cases[index].result =3D AMD_PSTATE_UT_RESULT_PASS; --=20 2.34.1