From nobody Tue May 21 16:17:10 2024 Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F0FA44C94; Wed, 17 Apr 2024 20:32:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713385924; cv=none; b=O7fhlXnIvFUoVJsugOzMOxAw2j+6QyPm/enWpyOzPO6Yg633ur/1zSFtq6ZD2D6XFj+i1weeQy/fFZJLTvgpu0Dx5W5+wKjrytHRoAm5B+gQGjP/kPCuxgpZQt6XUmoIKiJtoP7DvbAKZBdrFhfTvEaHoaW0F2f7ttgJEK1mXlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713385924; c=relaxed/simple; bh=yJdXC/Q3Xr0EL7UYdwsyh7gdRvydjr3J5vNqgkjgxnU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jk2p2EnJ6zWCThlNmN0J+0ojhFRHJIsNEpmBhftvol5rmUU5r/B/FRxfkhVNtgqJQqFTArBL8cAn+785PXCZWLYwkpfrD+VM8oj0UKL810dW2W8cOBYK1od8cOuqILJN+GNHaquEROxHq8lpoUJS/cl6heV2NMY0ZaB6qMspCMo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io; spf=pass smtp.mailfrom=finest.io; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b=MyLlPdJd; arc=none smtp.client-ip=74.208.4.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=finest.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=finest.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=finest.io header.i=parker@finest.io header.b="MyLlPdJd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=finest.io; s=s1-ionos; t=1713385914; x=1713990714; i=parker@finest.io; bh=8DVZiB5rBLaO78Y9u12D3SplbPcKBaSsMHCST2QVFuw=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:Message-ID:In-Reply-To: References:MIME-Version:Content-Transfer-Encoding:cc: content-transfer-encoding:content-type:date:from:message-id: mime-version:reply-to:subject:to; b=MyLlPdJdmZPEQzTkWQ4NCIXVXhZAtHIxN9X5ntx6h3aZgfQGf5o2ln17J5oxubqc DLH9TrscN4o7nN0t8vGq0zqHA/5tT92h2f7iyliHXlNh2hKN0/o577fcBVTumPwZU E7Jx5F4Ls915MQBmcg+a1aEADe/akbuGf+4bobAXj59P2qYLjuyNvzWjquGueGoMI BkhcGBApx4GjdPc18tVJ4TRuaDisTc12fmetdNrKOIMlGpbDXUiqsE0CzTiOPPQCY TCX6pI0U+v9iwlGJWjJW30Jie4jgtXnVIdGrN/T6GZb8l+IeV2DaJxZWhGrR9sj/a qNz929ZcOPOkDsUJEg== X-UI-Sender-Class: 55c96926-9e95-11ee-ae09-1f7a4046a0f6 Received: from finest.io ([98.159.241.229]) by mrelay.perfora.net (mreueus004 [74.208.5.2]) with ESMTPSA (Nemesis) id 1MBVVT-1rsUq5124t-00CwVn; Wed, 17 Apr 2024 22:31:54 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v4 1/7] serial: exar: remove old Connect Tech setup Date: Wed, 17 Apr 2024 16:31:23 -0400 Message-ID: <06a04b6c683ca20c50646cc0836be869c2dacd87.1713382717.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:2kIeL5o789fbeAlzaygoEOoFLPT2MfcgRCrP8EJ+m6PJmvEBqKY zVpcpiFUeN30e15WClQbIkHzFwm+UpFZxKNkXGjaACl54e40JzGslnscRSNR/uRKwFHQRBs qkDo+sKprMZws6lr3Kq6rNWff7TRbxnAPi6/9tjCjSU9MuGjjjm/fFDIgMdpqvac0zGp2+X 8Rtdy0Mui41IGFhJ/7z9A== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:Yu7mW78t6mA=;1+wiX4ZdaFrem6Q5HZc/8J/EXXo tIklVqD0xoMJXSxx1eWM4R5vojnxwEoEDFiQSZak/tJePgUAv4u3howzxHkqEmARt/1xkTACC bNG2pSE6aY/LqMmGeVZlNqG/CsaULsDi8Mx/ncz1cvydMG5lZt8ADvIo6yKz/BGTkUjgL6k0a 3HUA99P8G7nwueXBKGnrUboGcuFW6iD+Lm291PWdiUi8dY4dY01Ii8m7U4LJcFZ3YEKMFKXue O8/edle2oHnnNLkcbIlpYy9lo/+eZ8UUFqcCFoDB4hx+2hXHnejsoOsjka3oTwIfMA/n/WFJw TFE0GYONBO02CRb75a0ulTnD/FWIsuCnGMbvEfqCKwqT6Ru6Paklz6ndbD48OWYSMZQJseI5l lBpFkAeYUor+/qXC3QPZjJoBZO6vS3VFOmVaOoLMHXPIGcN5jbIJ9/Qet0q08EweFnJbIe+Tw lIOWSgpHdxSo3MyA2+SLEsX00DmBqsd0jHPcSFhWstnvwM7SB8Vtq+jtd7iRG1Acl9iv7tFnG aymPo4t/SYVvM1/6QQuPCvj9RjhuNTTfOmnruya5DJSHrQlR0IIIpBe8l3E5NfroaymEvastJ MtyYH46g3vlMGj25EKP7qlnSeDTKj35JWN8ipoqscn2UhW5AQ2axu7iWVVsuAHVzt4R3TSxa2 mE5pTY7rfMr67gJG4ynpvgmh7JMgTtfs++5KoYHCN3vJfiVxgwfDfEwN2pQYC2PXUhU22MOLJ 8L4OWp/9oRGneeBLEiOrCTrdLaqjWOkiQrE/DIoMms3oXcKXh36R0g= Content-Type: text/plain; charset="utf-8" From: Parker Newman Preparatory patch removing existing Connect Tech setup code and CONNECT_DEVICE macro. Subsequent patches in this series will add in new UART family specific setup code and new device definition macros to allow for supporting CTI serial cards with Exar PCI IDs and CTI PCI IDs. Signed-off-by: Parker Newman --- Changes in v3: - Split code removals to own patch drivers/tty/serial/8250/8250_exar.c | 37 ----------------------------- 1 file changed, 37 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 604e5a292d4e..04ce5e8ddb24 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -358,17 +358,6 @@ pci_fastcom335_setup(struct exar8250 *priv, struct pci= _dev *pcidev, return 0; } -static int -pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, - struct uart_8250_port *port, int idx) -{ - unsigned int offset =3D idx * 0x200; - unsigned int baud =3D 1843200; - - port->port.uartclk =3D baud * 16; - return default_setup(priv, pcidev, idx, offset, port); -} - static int pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, struct uart_8250_port *port, int idx) @@ -849,10 +838,6 @@ static const struct exar8250_board pbn_fastcom335_8 = =3D { .setup =3D pci_fastcom335_setup, }; -static const struct exar8250_board pbn_connect =3D { - .setup =3D pci_connect_tech_setup, -}; - static const struct exar8250_board pbn_exar_ibm_saturn =3D { .num_ports =3D 1, .setup =3D pci_xr17c154_setup, @@ -897,15 +882,6 @@ static const struct exar8250_board pbn_exar_XR17V8358 = =3D { .exit =3D pci_xr17v35x_exit, }; -#define CONNECT_DEVICE(devid, sdevid, bd) { \ - PCI_DEVICE_SUB( \ - PCI_VENDOR_ID_EXAR, \ - PCI_DEVICE_ID_EXAR_##devid, \ - PCI_SUBVENDOR_ID_CONNECT_TECH, \ - PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ - (kernel_ulong_t)&bd \ - } - #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } #define IBM_DEVICE(devid, sdevid, bd) { \ @@ -935,19 +911,6 @@ static const struct pci_device_id exar_pci_tbl[] =3D { EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), - CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), - IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), /* USRobotics USR298x-OEM PCI Modems */ -- 2.43.2 From nobody Tue May 21 16:17:10 2024 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9E183D967; 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Wed, 17 Apr 2024 22:31:54 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v4 2/7] serial: exar: added a exar_get_nr_ports function Date: Wed, 17 Apr 2024 16:31:24 -0400 Message-ID: <33f2bf66bc334573c10cf670a299ecef0b7264bc.1713382717.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:lmxjJVTt5Rxry9+yxUIQhHvHMuCXBS86zV+ew9oOXQmeZeK6tof Dt1whiHtZZ6rMhpcuLVF7YL5rn0i+mbVkefwzyV+A/gtdj8gxTY4o5ABsg720axXQG/ZzES PL8cvcXFuz/7S6jg4aY6OobTFnARSKXiUNYplOIMmoeAywqdAMgLDiTEAlRxutO5P3/gKoE VANiRnIkckaen/Ija5TTw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:g4f2b9UA+MY=;7N1TVxiFRc05BDan4sTTMmiIbCt kElQvHp5BQ+bKwrp8hMyq1L29KrbLAmKq1lyp0VlDesaTYsGAzBSqUIFIJPrRg7tXL7qh9pIY 0kXWBLen69BwKuo8Vw+lP5DSfGKa9//+vNePUHVMyixaUKB24gfPrzFrcdOXIyxxooxL+IgmI JbEztJPY4EL5KnV6secdH+2vByFbwXK2kCzqm2fq6f/kwOqWZHPX9uD1NKj0L94VxSO4B/eLO k8fyOLCCuiPcfAuH2rkl46GvGIYBvKMIsr1eX7VmzpusvzeKA6JsugKIQNUTXtQw0BTy9HmHn EHVJejVnXnq0QFFJAQtPDw2MHiiFMBTwta6s6XaIuqoBc+UauOQkHUII1324LUvOGdatQDKxZ fKZBRhL9s+x56tljmtEBSEEecoa5QRqdMszjfSxo6W/hUGJufsvhDy7aTq5dxrJCeTGL6CPgB skCYsWs1m4NWL5YT1N8tfWorViRRlMbbN2nh6WneWBblQ3ZYATue45fjgpvpwmYVHx6WRbMsF GHBFC+rgwN/JH9XMjhhMQZMOuwrfHA/5TiWMhTqIBQ2dhhqV1ZnUVAEGsbK5WiAfuZwjaXQZ2 2wvWaiSyowQxhFf0HZaxqrnx4mHG5PzrO7mx1Pa5p2o9TXJrguRtKxs2U2TYJgdH/pkQ5dsEC U7ZJMJgcTK7bN3EZzmyI/mMaAEFotGM6GB7aAjR9J5muAsquJdFE/U206uhUZjevK4XElD8eT ecda+uaZR7rh0tgAUz+qmonwYjKblhloi5pqFDWrJ1GMfnUccounF0= Content-Type: text/plain; charset="utf-8" From: Parker Newman Moved code for getting number of ports from exar_pci_probe() to a separate exar_get_nr_ports() function. CTI specific code will be added in another patch in this series. Signed-off-by: Parker Newman Reviewed-by: Ilpo J=C3=A4rvinen --- Changes in v3: - Only moved existing code in this patch, will add CTI code in subsequent patch drivers/tty/serial/8250/8250_exar.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 04ce5e8ddb24..72385c7d2eda 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -704,6 +704,21 @@ static irqreturn_t exar_misc_handler(int irq, void *da= ta) return IRQ_HANDLED; } +static unsigned int exar_get_nr_ports(struct exar8250_board *board, + struct pci_dev *pcidev) +{ + unsigned int nr_ports =3D 0; + + if (pcidev->vendor =3D=3D PCI_VENDOR_ID_ACCESSIO) + nr_ports =3D BIT(((pcidev->device & 0x38) >> 3) - 1); + else if (board->num_ports) + nr_ports =3D board->num_ports; + else + nr_ports =3D pcidev->device & 0x0f; + + return nr_ports; +} + static int exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) { @@ -723,12 +738,12 @@ exar_pci_probe(struct pci_dev *pcidev, const struct p= ci_device_id *ent) maxnr =3D pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 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charset="utf-8" From: Parker Newman Add an optional "board_init()" function pointer to struct exar8250_board which is called once during probe prior to setting up the ports. It will be used in subsequent patches of this series. Signed-off-by: Parker Newman Reviewed-by: Ilpo J=C3=A4rvinen --- Changes in v3: - Renamed board_setup to board_init. - Changed pci_err to dev_err_probe - Added note above about checkpatch fixes Changes in v4: - Removed checkpatch fixes, they will be in their own patch at the end - Added pcidev to board_init() args to avoid needing to add to priv drivers/tty/serial/8250/8250_exar.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 72385c7d2eda..f14f73d250bb 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -177,12 +177,14 @@ struct exar8250_platform { * struct exar8250_board - board information * @num_ports: number of serial ports * @reg_shift: describes UART register mapping in PCI memory - * @setup: quirk run at ->probe() stage + * @board_init: quirk run once at ->probe() stage before setting up ports + * @setup: quirk run at ->probe() stage for each port * @exit: quirk run at ->remove() stage */ struct exar8250_board { unsigned int num_ports; unsigned int reg_shift; + int (*board_init)(struct exar8250 *priv, struct pci_dev *pcidev); int (*setup)(struct exar8250 *, struct pci_dev *, struct uart_8250_port *, int); void (*exit)(struct pci_dev *pcidev); @@ -773,6 +775,15 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pc= i_device_id *ent) if (rc) return rc; + if (board->board_init) { + rc =3D board->board_init(priv, pcidev); + if (rc) { + dev_err_probe(&pcidev->dev, rc, + "failed to init serial board\n"); + return rc; + } + } + for (i =3D 0; i < nr_ports && i < maxnr; i++) { rc =3D board->setup(priv, pcidev, &uart, i); if (rc) { -- 2.43.2 From nobody Tue May 21 16:17:10 2024 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B5E244C8B; Wed, 17 Apr 2024 20:32:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.197 ARC-Seal: i=1; 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Wed, 17 Apr 2024 22:31:55 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v4 4/7] serial: exar: moved generic_rs485 further up in 8250_exar.c Date: Wed, 17 Apr 2024 16:31:26 -0400 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:+hpOLbZKCVK1NoaArMhv+73t32rBcfbUsYZPyRUPiiIU0hqKy83 q076np94c4pmFMV4vh+U7HZ8W1WiNTnQj+F+Z1923DNH4QOtgp29V3WLT0I95rMkHLtfv30 9yr0DkzEJkosiQ8kJU0vUlAGD1xP6IjOHKz0B3RPahuryIxNMRcuyepJqEeUCECGg/xyaiH nmEFvAWCQo7lxDDheAb9w== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:Mx0TjLfV/CQ=;vIIrygbyWdnlaJ/s4Jea8H0fTKU D7oKZEIK/ztumR/B/4iuMy7z6AyB3olY8J2SwyAl0vmaB3kWdh7bKbR7V2tcjWzvJyn09VAfQ e794Wl5u6tXEPYjWE9SxbJF/oXRseeFKGSSNIByZtsC4wMJytPrANgIYNOuDDPJPtVrdp1BLv REO7XYvEVgHoIgA+B9SfZjuOScCPSyw6FmiM1C6hFaLPs+idfQpN5JxkmQughzNi5P1J29QIr z+R6N6IrsV4qJushuIx0OO61iIlCuFRwxCh4jiiCMHT9MX+v3CvGewB9x2mWl5QHwVwYkp/26 em9EBl//JMs2pBMFzDQCbguVbt8gTsL4zpNZL3JVbrsVvxMDXN+GSu0ujIrFXEz/RVeivYiEc ZsKCaefTFLVS+8QrX0TNTNWP9wNL4v42DTiRy2Ep0+j4GoooxbJJZZ5tGoVY3DQfSAPlRZvxg +RJ8cXG4sB/X8Y+EXFV1K6G2ubn6pfTyKfIyMJfclo3llyN3QOb2+QRATsmB8mrQPszubMRQm mq+r56zqOE02UTC9Vc7Hbj11BN9s4DgKzANW2b1Qcr47fgdStRMlSu/3ZTu02V8M3ZLpLlyeE 2zeflT0ruzarQKCeQ+2Br78GB4mizdAAcjJ1bC0ediK3WsMZetqgNorU5EfokGOKw3iC9YmPL m6ZzR53Lw5K3vYaW93IcrlzWGekYpaJwNSR667CUBGiv/Ta2OkaEx/QXr5isBD0hWK8BQtpkI gr1y39CSlQ3webvt5BQFd3NfpBjef4xImIbu4GtX9l430GnUBY3aYc= Content-Type: text/plain; charset="utf-8" From: Parker Newman Preparatory patch moving generic_rs485_config and generic_rs485_supported higher in the file to allow for CTI setup functions to use them. Signed-off-by: Parker Newman Reviewed-by: Ilpo J=C3=A4rvinen --- Changes in v3: - split into separate preparatory patch drivers/tty/serial/8250/8250_exar.c | 50 ++++++++++++++--------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index f14f73d250bb..e68029a59122 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -197,6 +197,31 @@ struct exar8250 { int line[]; }; +static int generic_rs485_config(struct uart_port *port, struct ktermios *t= ermios, + struct serial_rs485 *rs485) +{ + bool is_rs485 =3D !!(rs485->flags & SER_RS485_ENABLED); + u8 __iomem *p =3D port->membase; + u8 value; + + value =3D readb(p + UART_EXAR_FCTR); + if (is_rs485) + value |=3D UART_FCTR_EXAR_485; + else + value &=3D ~UART_FCTR_EXAR_485; + + writeb(value, p + UART_EXAR_FCTR); + + if (is_rs485) + writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); + + return 0; +} + +static const struct serial_rs485 generic_rs485_supported =3D { + .flags =3D SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, +}; + static void exar_pm(struct uart_port *port, unsigned int state, unsigned i= nt old) { /* @@ -459,27 +484,6 @@ static void xr17v35x_unregister_gpio(struct uart_8250_= port *port) port->port.private_data =3D NULL; } -static int generic_rs485_config(struct uart_port *port, struct ktermios *t= ermios, - struct serial_rs485 *rs485) -{ - bool is_rs485 =3D !!(rs485->flags & SER_RS485_ENABLED); - u8 __iomem *p =3D port->membase; - u8 value; - - value =3D readb(p + UART_EXAR_FCTR); - if (is_rs485) - value |=3D UART_FCTR_EXAR_485; - else - value &=3D ~UART_FCTR_EXAR_485; - - writeb(value, p + UART_EXAR_FCTR); - - if (is_rs485) - writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); - - return 0; -} - static int sealevel_rs485_config(struct uart_port *port, struct ktermios *= termios, struct serial_rs485 *rs485) { @@ -518,10 +522,6 @@ static int sealevel_rs485_config(struct uart_port *por= t, struct ktermios *termio return 0; } -static const struct serial_rs485 generic_rs485_supported =3D { - .flags =3D SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, -}; - static const struct exar8250_platform exar8250_default_platform =3D { .register_gpio =3D xr17v35x_register_gpio, .unregister_gpio =3D xr17v35x_unregister_gpio, -- 2.43.2 From nobody Tue May 21 16:17:10 2024 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3B85651AB; Wed, 17 Apr 2024 20:32:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713385932; cv=none; b=tSUZbBMfXmUbRtQ0C+mQl/NAJovbiWckSXbEd8U89hjeY/mg9WdVsKV/cgTg6sUHSaZElkTY1765G5nvzkgzV8dN7oFaeCzN/r4va+8qqrGbAARIMzPysMyEeM5DEW/QJOe/dkJkQkW3LaBJL3dJ/smsfrWbLE1S5pe705heO9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713385932; c=relaxed/simple; bh=jBrmZuc+hQi/FGE2D/xlvk+OLFJTmVNAlYBeQ3oBbaw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" From: Parker Newman Add code for getting number of ports of CTI cards to exar_get_nr_ports(). Signed-off-by: Parker Newman --- Changes in v3: - moved to separate patch - added spaces to single line comments drivers/tty/serial/8250/8250_exar.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index e68029a59122..197f45e306ff 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -711,12 +711,28 @@ static unsigned int exar_get_nr_ports(struct exar8250= _board *board, { unsigned int nr_ports =3D 0; - if (pcidev->vendor =3D=3D PCI_VENDOR_ID_ACCESSIO) + if (pcidev->vendor =3D=3D PCI_VENDOR_ID_ACCESSIO) { nr_ports =3D BIT(((pcidev->device & 0x38) >> 3) - 1); - else if (board->num_ports) + } else if (board->num_ports > 0) { + // Check if board struct overrides number of ports nr_ports =3D board->num_ports; - else + } else if (pcidev->vendor =3D=3D PCI_VENDOR_ID_EXAR) { + // Exar encodes # ports in last nibble of PCI Device ID ex. 0358 nr_ports =3D pcidev->device & 0x0f; + } else if (pcidev->vendor =3D=3D PCI_VENDOR_ID_CONNECT_TECH) { + // Handle CTI FPGA cards + switch (pcidev->device) { + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X: + nr_ports =3D 12; + break; + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16: + nr_ports =3D 16; + break; + default: + break; + } + } return nr_ports; } -- 2.43.2 From nobody Tue May 21 16:17:10 2024 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF80A64CCC; Wed, 17 Apr 2024 20:32:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713385930; cv=none; b=iTgFT08RB1MXhKvaI97fzoL3KJd5M+iym2o8Cn8ctpELWldotOZptjErgEslcN7XcKHcRLYdm8RnL+k9kMhL8PYK/nzX9me9a2pSSqhCycA4o+Io4jGdBir47ARRGg4WPYZ+eU4rTk9Ar2p30DMfZEKx8rXtHjy8ePy1tBBhEBI= ARC-Message-Signature: i=1; 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charset="utf-8" From: Parker Newman This is a large patch but is only additions. All changes and removals are made in previous patches in this series. - Add CTI board_init and port setup functions for each UART type - Add CTI_EXAR_DEVICE() and CTI_PCI_DEVICE() macros - Add support for reading a word from the Exar EEPROM. - Add support for configuring and setting a single MPIO - Add various helper functions for CTI boards. - Add osc_freq to struct exar8250 Signed-off-by: Parker Newman --- Changes in v3: - Moved all base driver changes and refactoring to preparatory patches - Switched any user space types to kernel types - Switched all uses of pci_xxx print functions to dev_xxx - Added struct device pointer in struct exar8250 to simplify above - Switched osc_freq and port_flag parsing to use GENMASK() and FIELD_GET()/FIELD_PREP() - Renamed board_setup function pointer to board_init - Removed some unneeded checks for priv being NULL - Added various convenience functions instead of relying on bools ex: exar_mpio_set_low()/exar_mpio_set_high() instead of exar_mpio_set() - Renamed some variables and defines for clarity - Numerous minor formatting fixes Changes in v4: - Removed pcidev and dev from struct exar8250 - Removed some debug prints - Removed some unneeded checks if PCI vendor was Exar - Changed several functions to take pcidev as arg to avoid adding to priv - Removed _exar_mpio_config(), only needed exar_mpio_config_output() - Removed _cti_set_tristate() and _cti_set_plx_int_enable, same as above drivers/tty/serial/8250/8250_exar.c | 846 ++++++++++++++++++++++++++++ 1 file changed, 846 insertions(+) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 197f45e306ff..6985aabe13cc 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -128,6 +129,19 @@ #define UART_EXAR_DLD 0x02 /* Divisor Fractional */ #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ +/* EEPROM registers */ +#define UART_EXAR_REGB 0x8e +#define UART_EXAR_REGB_EECK BIT(4) +#define UART_EXAR_REGB_EECS BIT(5) +#define UART_EXAR_REGB_EEDI BIT(6) +#define UART_EXAR_REGB_EEDO BIT(7) +#define UART_EXAR_REGB_EE_ADDR_SIZE 6 +#define UART_EXAR_REGB_EE_DATA_SIZE 16 + +#define UART_EXAR_XR17C15X_PORT_OFFSET 0x200 +#define UART_EXAR_XR17V25X_PORT_OFFSET 0x200 +#define UART_EXAR_XR17V35X_PORT_OFFSET 0x400 + /* * IOT2040 MPIO wiring semantics: * @@ -163,6 +177,52 @@ #define IOT2040_UARTS_ENABLE 0x03 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ +/* CTI EEPROM offsets */ +#define CTI_EE_OFF_XR17C15X_OSC_FREQ 0x04 /* 2 words */ +#define CTI_EE_OFF_XR17V25X_OSC_FREQ 0x08 /* 2 words */ +#define CTI_EE_OFF_XR17C15X_PART_NUM 0x0A /* 4 words */ +#define CTI_EE_OFF_XR17V25X_PART_NUM 0x0E /* 4 words */ +#define CTI_EE_OFF_XR17C15X_SERIAL_NUM 0x0E /* 1 word */ +#define CTI_EE_OFF_XR17V25X_SERIAL_NUM 0x12 /* 1 word */ +#define CTI_EE_OFF_XR17V35X_SERIAL_NUM 0x11 /* 2 word */ +#define CTI_EE_OFF_XR17V35X_BRD_FLAGS 0x13 /* 1 word */ +#define CTI_EE_OFF_XR17V35X_PORT_FLAGS 0x14 /* 1 word */ + +#define CTI_EE_MASK_PORT_FLAGS_TYPE GENMASK(7, 0) +#define CTI_EE_MASK_OSC_FREQ_LOWER GENMASK(15, 0) +#define CTI_EE_MASK_OSC_FREQ_UPPER GENMASK(31, 16) + +#define CTI_FPGA_RS485_IO_REG 0x2008 +#define CTI_FPGA_CFG_INT_EN_REG 0x48 +#define CTI_FPGA_CFG_INT_EN_EXT_BIT BIT(15) /* External int enable bit */ + +#define CTI_DEFAULT_PCI_OSC_FREQ 29491200 +#define CTI_DEFAULT_PCIE_OSC_FREQ 125000000 +#define CTI_DEFAULT_FPGA_OSC_FREQ 33333333 + +/* + * CTI Serial port line types. These match the values stored in the first + * nibble of the CTI EEPROM port_flags word. + */ +enum cti_port_type { + CTI_PORT_TYPE_NONE =3D 0, + CTI_PORT_TYPE_RS232, // RS232 ONLY + CTI_PORT_TYPE_RS422_485, // RS422/RS485 ONLY + CTI_PORT_TYPE_RS232_422_485_HW, // RS232/422/485 HW ONLY Switchable + CTI_PORT_TYPE_RS232_422_485_SW, // RS232/422/485 SW ONLY Switchable + CTI_PORT_TYPE_RS232_422_485_4B, // RS232/422/485 HW/SW (4bit ex. BCG004) + CTI_PORT_TYPE_RS232_422_485_2B, // RS232/422/485 HW/SW (2bit ex. BBG008) + CTI_PORT_TYPE_MAX, +}; + +#define CTI_PORT_TYPE_VALID(_port_type) \ + (((_port_type) > CTI_PORT_TYPE_NONE) && \ + ((_port_type) < CTI_PORT_TYPE_MAX)) + +#define CTI_PORT_TYPE_RS485(_port_type) \ + (((_port_type) > CTI_PORT_TYPE_RS232) && \ + ((_port_type) < CTI_PORT_TYPE_MAX)) + struct exar8250; struct exar8250_platform { @@ -192,11 +252,201 @@ struct exar8250_board { struct exar8250 { unsigned int nr; + unsigned int osc_freq; struct exar8250_board *board; void __iomem *virt; int line[]; }; +static inline void exar_write_reg(struct exar8250 *priv, + unsigned int reg, u8 value) +{ + writeb(value, priv->virt + reg); +} + +static inline u8 exar_read_reg(struct exar8250 *priv, unsigned int reg) +{ + return readb(priv->virt + reg); +} + +static inline void exar_ee_select(struct exar8250 *priv) +{ + // Set chip select pin high to enable EEPROM reads/writes + exar_write_reg(priv, UART_EXAR_REGB, UART_EXAR_REGB_EECS); + // Min ~500ns delay needed between CS assert and EEPROM access + udelay(1); +} + +static inline void exar_ee_deselect(struct exar8250 *priv) +{ + exar_write_reg(priv, UART_EXAR_REGB, 0x00); +} + +static inline void exar_ee_write_bit(struct exar8250 *priv, int bit) +{ + u8 value =3D UART_EXAR_REGB_EECS; + + if (bit) + value |=3D UART_EXAR_REGB_EEDI; + + // Clock out the bit on the EEPROM interface + exar_write_reg(priv, UART_EXAR_REGB, value); + // 2us delay =3D ~500khz clock speed + udelay(2); + + value |=3D UART_EXAR_REGB_EECK; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); +} + +static inline u8 exar_ee_read_bit(struct exar8250 *priv) +{ + u8 regb; + u8 value =3D UART_EXAR_REGB_EECS; + + // Clock in the bit on the EEPROM interface + exar_write_reg(priv, UART_EXAR_REGB, value); + // 2us delay =3D ~500khz clock speed + udelay(2); + + value |=3D UART_EXAR_REGB_EECK; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); + + regb =3D exar_read_reg(priv, UART_EXAR_REGB); + + return (regb & UART_EXAR_REGB_EEDO ? 1 : 0); +} + +/** + * exar_ee_read() - Read a word from the EEPROM + * @priv: Device's private structure + * @ee_addr: Offset of EEPROM to read word from + * + * Read a single 16bit word from an Exar UART's EEPROM. + * + * Return: EEPROM word + */ +static u16 exar_ee_read(struct exar8250 *priv, u8 ee_addr) +{ + int i; + u16 data =3D 0; + + exar_ee_select(priv); + + // Send read command (opcode 110) + exar_ee_write_bit(priv, 1); + exar_ee_write_bit(priv, 1); + exar_ee_write_bit(priv, 0); + + // Send address to read from + for (i =3D 1 << (UART_EXAR_REGB_EE_ADDR_SIZE - 1); i; i >>=3D 1) + exar_ee_write_bit(priv, (ee_addr & i)); + + // Read data 1 bit at a time + for (i =3D 0; i <=3D UART_EXAR_REGB_EE_DATA_SIZE; i++) { + data <<=3D 1; + data |=3D exar_ee_read_bit(priv); + } + + exar_ee_deselect(priv); + + return data; +} + +/** + * exar_mpio_config_output() - Configure an Exar MPIO as an output + * @priv: Device's private structure + * @mpio_num: MPIO number/offset to configure + * + * Configure a single MPIO as an output and disable tristate. It is reccom= ended + * to set the level with exar_mpio_set_high()/exar_mpio_set_low() prior to + * calling this function to ensure default MPIO pin state. + * + * Return: 0 on success, negative error code on failure + */ +static int exar_mpio_config_output(struct exar8250 *priv, + unsigned int mpio_num) +{ + unsigned int mpio_offset; + u8 sel_reg; // MPIO Select register (input/output) + u8 tri_reg; // MPIO Tristate register + u8 value; + + if (mpio_num < 8) { + sel_reg =3D UART_EXAR_MPIOSEL_7_0; + tri_reg =3D UART_EXAR_MPIO3T_7_0; + mpio_offset =3D mpio_num; + } else if (mpio_num >=3D 8 && mpio_num < 16) { + sel_reg =3D UART_EXAR_MPIOSEL_15_8; + tri_reg =3D UART_EXAR_MPIO3T_15_8; + mpio_offset =3D mpio_num - 8; + } else { + return -EINVAL; + } + + // Disable MPIO pin tri-state + value =3D exar_read_reg(priv, tri_reg); + value &=3D ~BIT(mpio_offset); + exar_write_reg(priv, tri_reg, value); + + value =3D exar_read_reg(priv, sel_reg); + value &=3D ~BIT(mpio_offset); + exar_write_reg(priv, sel_reg, value); + + return 0; +} + +/** + * _exar_mpio_set() - Set an Exar MPIO output high or low + * @priv: Device's private structure + * @mpio_num: MPIO number/offset to set + * @high: Set MPIO high if true, low if false + * + * Set a single MPIO high or low. exar_mpio_config_output() must also be c= alled + * to configure the pin as an output. + * + * Return: 0 on success, negative error code on failure + */ +static int _exar_mpio_set(struct exar8250 *priv, + unsigned int mpio_num, bool high) +{ + unsigned int mpio_offset; + u8 lvl_reg; + u8 value; + + if (mpio_num < 8) { + lvl_reg =3D UART_EXAR_MPIOLVL_7_0; + mpio_offset =3D mpio_num; + } else if (mpio_num >=3D 8 && mpio_num < 16) { + lvl_reg =3D UART_EXAR_MPIOLVL_15_8; + mpio_offset =3D mpio_num - 8; + } else { + return -EINVAL; + } + + value =3D exar_read_reg(priv, lvl_reg); + if (high) + value |=3D BIT(mpio_offset); + else + value &=3D ~BIT(mpio_offset); + exar_write_reg(priv, lvl_reg, value); + + return 0; +} + +static int exar_mpio_set_low(struct exar8250 *priv, unsigned int mpio_num) +{ + return _exar_mpio_set(priv, mpio_num, false); +} + +static int exar_mpio_set_high(struct exar8250 *priv, unsigned int mpio_num) +{ + return _exar_mpio_set(priv, mpio_num, true); +} + static int generic_rs485_config(struct uart_port *port, struct ktermios *t= ermios, struct serial_rs485 *rs485) { @@ -385,6 +635,546 @@ pci_fastcom335_setup(struct exar8250 *priv, struct pc= i_dev *pcidev, return 0; } +/** + * cti_tristate_disable() - Disable RS485 transciever tristate + * @priv: Device's private structure + * @port_num: Port number to set tristate off + * + * Most RS485 capable cards have a power on tristate jumper/switch that en= sures + * the RS422/RS485 transciever does not drive a multi-drop RS485 bus when = it is + * not the master. When this jumper is installed the user must set the RS4= 85 + * mode to Full or Half duplex to disable tristate prior to using the port. + * + * Some Exar UARTs have an auto-tristate feature while others require sett= ing + * an MPIO to disable the tristate. + * + * Return: 0 on success, negative error code on failure + */ +static int cti_tristate_disable(struct exar8250 *priv, unsigned int port_n= um) +{ + int ret; + + ret =3D exar_mpio_set_high(priv, port_num); + if (ret) + return ret; + + return exar_mpio_config_output(priv, port_num); +} + +/** + * cti_plx_int_enable() - Enable UART interrupts to PLX bridge + * @priv: Device's private structure + * + * Some older CTI cards require MPIO_0 to be set low to enable the + * interupts from the UART to the PLX PCI->PCIe bridge. + * + * Return: 0 on success, negative error code on failure + */ +static int cti_plx_int_enable(struct exar8250 *priv) +{ + int ret; + + ret =3D exar_mpio_set_low(priv, 0); + if (ret) + return ret; + + return exar_mpio_config_output(priv, 0); +} + +/** + * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM + * @priv: Device's private structure + * @eeprom_offset: Offset where the oscillator frequency is stored + * + * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequ= ency + * stored in the EEPROM. FPGA and XR17V35X based cards use the PCI/PCIe cl= ock. + * + * Return: frequency on success, negative error code on failure + */ +static int cti_read_osc_freq(struct exar8250 *priv, u8 eeprom_offset) +{ + u16 lower_word; + u16 upper_word; + int osc_freq; + + lower_word =3D exar_ee_read(priv, eeprom_offset); + // Check if EEPROM word was blank + if (lower_word =3D=3D 0xFFFF) + return -EIO; + + upper_word =3D exar_ee_read(priv, (eeprom_offset + 1)); + if (upper_word =3D=3D 0xFFFF) + return -EIO; + + osc_freq =3D FIELD_PREP(CTI_EE_MASK_OSC_FREQ_LOWER, lower_word) | + FIELD_PREP(CTI_EE_MASK_OSC_FREQ_UPPER, upper_word); + + return osc_freq; +} + +/** + * cti_get_port_type_xr17c15x_xr17v25x() - Get port type of xr17c15x/xr17v= 25x + * @priv: Device's private structure + * @port_num: Port to get type of + * + * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_xr17c15x_xr17v25x(struct exar8= 250 *priv, + struct pci_dev *pcidev, + unsigned int port_num) +{ + enum cti_port_type port_type; + + switch (pcidev->subsystem_device) { + // RS232 only cards + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS: + port_type =3D CTI_PORT_TYPE_RS232; + break; + // 1x RS232, 1x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1: + port_type =3D (port_num =3D=3D 0) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // 2x RS232, 2x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2: + port_type =3D (port_num < 2) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // 4x RS232, 4x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + port_type =3D (port_num < 4) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // RS232/RS422/RS485 HW (jumper) selectable + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + port_type =3D CTI_PORT_TYPE_RS232_422_485_HW; + break; + // RS422/RS485 HW (jumper) selectable + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port_type =3D CTI_PORT_TYPE_RS422_485; + break; + // 6x RS232, 2x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + port_type =3D (port_num < 6) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // 2x RS232, 6x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + port_type =3D (port_num < 2) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + default: + dev_err(&pcidev->dev, "unknown/unsupported device\n"); + port_type =3D CTI_PORT_TYPE_NONE; + } + + return port_type; +} + +/** + * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card + * @priv: Device's private structure + * @port_num: Port to get type of + * + * FPGA based cards port types are based on PCI IDs. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_fpga(struct exar8250 *priv, + struct pci_dev *pcidev, + unsigned int port_num) +{ + enum cti_port_type port_type; + + switch (pcidev->device) { + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16: + port_type =3D CTI_PORT_TYPE_RS232_422_485_HW; + break; + default: + dev_err(&pcidev->dev, "unknown/unsupported device\n"); + return CTI_PORT_TYPE_NONE; + } + + return port_type; +} + +/** + * cti_get_port_type_xr17v35x() - Read port type from the EEPROM + * @priv: Device's private structure + * @port_num: port offset + * + * CTI XR17V35X based cards have the port types stored in the EEPROM. + * This function reads the port type for a single port. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv, + struct pci_dev *pcidev, + unsigned int port_num) +{ + enum cti_port_type port_type; + u16 port_flags; + u8 offset; + + offset =3D CTI_EE_OFF_XR17V35X_PORT_FLAGS + port_num; + port_flags =3D exar_ee_read(priv, offset); + + port_type =3D FIELD_GET(CTI_EE_MASK_PORT_FLAGS_TYPE, port_flags); + if (!CTI_PORT_TYPE_VALID(port_type)) { + /* + * If the port type is missing the card assume it is a + * RS232/RS422/RS485 card to be safe. + * + * There is one known board (BEG013) that only has + * 3 of 4 port types written to the EEPROM so this + * acts as a work around. + */ + dev_warn(&pcidev->dev, + "failed to get port %d type from EEPROM\n", port_num); + port_type =3D CTI_PORT_TYPE_RS232_422_485_HW; + } + + return port_type; +} + +static int cti_rs485_config_mpio_tristate(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + struct exar8250 *priv =3D (struct exar8250 *)port->private_data; + int ret; + + ret =3D generic_rs485_config(port, termios, rs485); + if (ret) + return ret; + + // Disable power-on RS485 tri-state via MPIO + return cti_tristate_disable(priv, port->port_id); +} + +static int cti_port_setup_common(struct exar8250 *priv, + struct pci_dev *pcidev, + int idx, unsigned int offset, + struct uart_8250_port *port) +{ + int ret; + + if (priv->osc_freq =3D=3D 0) + return -EINVAL; + + port->port.port_id =3D idx; + port->port.uartclk =3D priv->osc_freq; + + ret =3D serial8250_pci_setup_port(pcidev, port, 0, offset, 0); + if (ret) { + dev_err(&pcidev->dev, + "failed to setup pci for port %d err: %d\n", idx, ret); + return ret; + } + + port->port.private_data =3D (void *)priv; + port->port.pm =3D exar_pm; + port->port.shutdown =3D exar_shutdown; + + return 0; +} + +static int cti_port_setup_fpga(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + + port_type =3D cti_get_port_type_fpga(priv, pcidev, idx); + + // FPGA shares port offests with XR17C15X + offset =3D idx * UART_EXAR_XR17C15X_PORT_OFFSET; + port->port.type =3D PORT_XR17D15X; + + port->port.get_divisor =3D xr17v35x_get_divisor; + port->port.set_divisor =3D xr17v35x_set_divisor; + port->port.startup =3D xr17v35x_startup; + + if (CTI_PORT_TYPE_RS485(port_type)) { + port->port.rs485_config =3D generic_rs485_config; + port->port.rs485_supported =3D generic_rs485_supported; + } + + return cti_port_setup_common(priv, pcidev, idx, offset, port); +} + +static int cti_port_setup_xr17v35x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + int ret; + + port_type =3D cti_get_port_type_xr17v35x(priv, pcidev, idx); + + offset =3D idx * UART_EXAR_XR17V35X_PORT_OFFSET; + port->port.type =3D PORT_XR17V35X; + + port->port.get_divisor =3D xr17v35x_get_divisor; + port->port.set_divisor =3D xr17v35x_set_divisor; + port->port.startup =3D xr17v35x_startup; + + switch (port_type) { + case CTI_PORT_TYPE_RS422_485: + case CTI_PORT_TYPE_RS232_422_485_HW: + port->port.rs485_config =3D cti_rs485_config_mpio_tristate; + port->port.rs485_supported =3D generic_rs485_supported; + break; + case CTI_PORT_TYPE_RS232_422_485_SW: + case CTI_PORT_TYPE_RS232_422_485_4B: + case CTI_PORT_TYPE_RS232_422_485_2B: + port->port.rs485_config =3D generic_rs485_config; + port->port.rs485_supported =3D generic_rs485_supported; + break; + default: + break; + } + + ret =3D cti_port_setup_common(priv, pcidev, idx, offset, port); + if (ret) + return ret; + + exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00); + exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD); + exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 128); + exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 128); + + return 0; +} + +static int cti_port_setup_xr17v25x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + int ret; + + port_type =3D cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx); + + offset =3D idx * UART_EXAR_XR17V25X_PORT_OFFSET; + port->port.type =3D PORT_XR17D15X; + + // XR17V25X supports fractional baudrates + port->port.get_divisor =3D xr17v35x_get_divisor; + port->port.set_divisor =3D xr17v35x_set_divisor; + port->port.startup =3D xr17v35x_startup; + + if (CTI_PORT_TYPE_RS485(port_type)) { + switch (pcidev->subsystem_device) { + // These cards support power on 485 tri-state via MPIO + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port->port.rs485_config =3D cti_rs485_config_mpio_tristate; + break; + // Otherwise auto or no power on 485 tri-state support + default: + port->port.rs485_config =3D generic_rs485_config; + break; + } + + port->port.rs485_supported =3D generic_rs485_supported; + } + + ret =3D cti_port_setup_common(priv, pcidev, idx, offset, port); + if (ret) + return ret; + + exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00); + exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD); + exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 32); + exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 32); + + return 0; +} + +static int cti_port_setup_xr17c15x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + + port_type =3D cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx); + + offset =3D idx * UART_EXAR_XR17C15X_PORT_OFFSET; + port->port.type =3D PORT_XR17D15X; + + if (CTI_PORT_TYPE_RS485(port_type)) { + switch (pcidev->subsystem_device) { + // These cards support power on 485 tri-state via MPIO + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port->port.rs485_config =3D cti_rs485_config_mpio_tristate; + break; + // Otherwise auto or no power on 485 tri-state support + default: + port->port.rs485_config =3D generic_rs485_config; + break; + } + + port->port.rs485_supported =3D generic_rs485_supported; + } + + return cti_port_setup_common(priv, pcidev, idx, offset, port); +} + +static int cti_board_init_xr17v35x(struct exar8250 *priv, + struct pci_dev *pcidev) +{ + // XR17V35X uses the PCIe clock rather than an oscillator + priv->osc_freq =3D CTI_DEFAULT_PCIE_OSC_FREQ; + + return 0; +} + +static int cti_board_init_xr17v25x(struct exar8250 *priv, + struct pci_dev *pcidev) +{ + int osc_freq; + + osc_freq =3D cti_read_osc_freq(priv, CTI_EE_OFF_XR17V25X_OSC_FREQ); + if (osc_freq < 0) { + dev_warn(&pcidev->dev, + "failed to read osc freq from EEPROM, using default\n"); + osc_freq =3D CTI_DEFAULT_PCI_OSC_FREQ; + } + + priv->osc_freq =3D osc_freq; + + /* enable interupts on cards that need the "PLX fix" */ + switch (pcidev->subsystem_device) { + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + cti_plx_int_enable(priv); + break; + default: + break; + } + + return 0; +} + +static int cti_board_init_xr17c15x(struct exar8250 *priv, + struct pci_dev *pcidev) +{ + int osc_freq; + + osc_freq =3D cti_read_osc_freq(priv, CTI_EE_OFF_XR17C15X_OSC_FREQ); + if (osc_freq <=3D 0) { + dev_warn(&pcidev->dev, + "failed to read osc freq from EEPROM, using default\n"); + osc_freq =3D CTI_DEFAULT_PCI_OSC_FREQ; + } + + priv->osc_freq =3D osc_freq; + + /* enable interrupts on cards that need the "PLX fix" */ + switch (pcidev->subsystem_device) { + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + cti_plx_int_enable(priv); + break; + default: + break; + } + + return 0; +} + +static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcid= ev) +{ + int ret; + u16 cfg_val; + + // FPGA OSC is fixed to the 33MHz PCI clock + priv->osc_freq =3D CTI_DEFAULT_FPGA_OSC_FREQ; + + // Enable external interrupts in special cfg space register + ret =3D pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val); + if (ret) + return ret; + + cfg_val |=3D CTI_FPGA_CFG_INT_EN_EXT_BIT; + ret =3D pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val); + if (ret) + return ret; + + // RS485 gate needs to be enabled; otherwise RTS/CTS will not work + exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01); + + return 0; +} + static int pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, struct uart_8250_port *port, int idx) @@ -880,6 +1670,26 @@ static const struct exar8250_board pbn_fastcom335_8 = =3D { .setup =3D pci_fastcom335_setup, }; +static const struct exar8250_board pbn_cti_xr17c15x =3D { + .board_init =3D cti_board_init_xr17c15x, + .setup =3D cti_port_setup_xr17c15x, +}; + +static const struct exar8250_board pbn_cti_xr17v25x =3D { + .board_init =3D cti_board_init_xr17v25x, + .setup =3D cti_port_setup_xr17v25x, +}; + +static const struct exar8250_board pbn_cti_xr17v35x =3D { + .board_init =3D cti_board_init_xr17v35x, + .setup =3D cti_port_setup_xr17v35x, +}; + +static const struct exar8250_board pbn_cti_fpga =3D { + .board_init =3D cti_board_init_fpga, + .setup =3D cti_port_setup_fpga, +}; + static const struct exar8250_board pbn_exar_ibm_saturn =3D { .num_ports =3D 1, .setup =3D pci_xr17c154_setup, @@ -924,6 +1734,26 @@ static const struct exar8250_board pbn_exar_XR17V8358= =3D { .exit =3D pci_xr17v35x_exit, }; +// For Connect Tech cards with Exar vendor/device PCI IDs +#define CTI_EXAR_DEVICE(devid, bd) { \ + PCI_DEVICE_SUB( \ + PCI_VENDOR_ID_EXAR, \ + PCI_DEVICE_ID_EXAR_##devid, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_ANY_ID), 0, 0, \ + (kernel_ulong_t)&bd \ + } + +// For Connect Tech cards with Connect Tech vendor/device PCI IDs (FPGA ba= sed) +#define CTI_PCI_DEVICE(devid, bd) { \ + PCI_DEVICE_SUB( \ + PCI_VENDOR_ID_CONNECT_TECH, \ + PCI_DEVICE_ID_CONNECT_TECH_PCI_##devid, \ + PCI_ANY_ID, \ + PCI_ANY_ID), 0, 0, \ + (kernel_ulong_t)&bd \ + } + #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } #define IBM_DEVICE(devid, sdevid, bd) { \ @@ -953,6 +1783,22 @@ static const struct pci_device_id exar_pci_tbl[] =3D { EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), + CTI_EXAR_DEVICE(XR17C152, pbn_cti_xr17c15x), + CTI_EXAR_DEVICE(XR17C154, pbn_cti_xr17c15x), + CTI_EXAR_DEVICE(XR17C158, pbn_cti_xr17c15x), + + CTI_EXAR_DEVICE(XR17V252, pbn_cti_xr17v25x), + CTI_EXAR_DEVICE(XR17V254, pbn_cti_xr17v25x), + CTI_EXAR_DEVICE(XR17V258, pbn_cti_xr17v25x), + + CTI_EXAR_DEVICE(XR17V352, pbn_cti_xr17v35x), + CTI_EXAR_DEVICE(XR17V354, pbn_cti_xr17v35x), + CTI_EXAR_DEVICE(XR17V358, pbn_cti_xr17v35x), + + CTI_PCI_DEVICE(XR79X_12_XIG00X, pbn_cti_fpga), + CTI_PCI_DEVICE(XR79X_12_XIG01X, pbn_cti_fpga), + CTI_PCI_DEVICE(XR79X_16, pbn_cti_fpga), + IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), /* USRobotics USR298x-OEM PCI Modems */ -- 2.43.2 From nobody Tue May 21 16:17:10 2024 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 680E844C9E; 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Wed, 17 Apr 2024 22:31:56 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v4 7/7] serial: exar: fix checkpach warnings Date: Wed, 17 Apr 2024 16:31:29 -0400 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:rmQ6lvyO9pcnLqF+oMyPzW9wbsk5Q3xtHL1O3lWF5U+UZndGBr3 7w9Xot12CLhbAYxoy0wJ+Ne6eXqebMrO+jM+iUWIoRXgT5uZpLyv+8gz40NbbvnPxTA4o4R iAqJsu1PjiH5yUqRYdZ9oM2TwN8cTOWaFAImOlDFmSCTQgBxqNDzKEeW/kEf+iG4PEeUPnE xQadyyuJUeFPXt8jd+Sjw== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:tecjjXD4p7U=;yGo4BdNr+vZQPdaOqVSoWRi35md X1J2LPXuMabQkd2cG6i0FxPUdqdkCx+bWHs5QkCszvuMIIsNzNRw0DHvrF8HqoLFAR7iTtD3g h5BqWJzac+KPcQFmU9yPpKpQqaN4XUlIVFrv3Qi5RnQ7H2D/Q6iprDoAFS8wr8xowj+V0mOjV fSy01PPWZILRWfvhJug/6Au+Cy7+2sBK7VjOxokGzTi+PNUF/iVaEkj2rpCrQ95d3u16fW0nb Kg8ah1un8PTwPmngIuQbjl6S72OjqlDmyMEf2TdQ0DqNB5cI08oTQXI9XJAuCVSDK82r7mB0d 2WPUJ+efgMZekBupb4mUoMn4hZ/KAhFvXmTsjH2ebWZsslV4cEc5JjYKncItpAzZDd2AEfISa esuRreZv4eOQ+yeu8yuMh9YGJx2tm3U8t+jwMhz6L3pDZW5mPdoeo6S5UpMxWJxQ4YQV85nYM ZsmWSm5zSRa/oaJUFOepNmnSRbWVNe9Dy+57DrFPl7hRumyRguf1Psw78M6Gcw6iQeb/Pj8dK fcl2o6iJr3/Qm7h6bUYojCJtyMsLZC1B0MTM5mYB/u8wZKGxOwvx3JBFU7vrkcOf9V60E/2sw SWeGbchB8FM5cSJg0eRlguqkJLkb74m0fD+rwm7qQPJrCHFPW/c0gJLoVDV7XxbekoPIzGTLd uzNtH6QNlv98lTxvBNUGtYAB33RV3Qhybx2kViTeyyxe7iNNGVTo6FK6M7FFwzc/XMNylcTI3 7U46a8Fxpeu9L76BidXoBMwsjWkq3EUQDQCyjmrwOTa5psM/VRuiJc= Content-Type: text/plain; charset="utf-8" From: Parker Newman -Fix several "missing identifier name" warnings from checkpatch in struct exar8250_platform and struct exar8250_board. Example: WARNING: function definition argument should also have an identifier name - Fix space before tab warning from checkpatch: WARNING: please, no space before tabs + * 0^I^I2 ^IMode bit 0$ Signed-off-by: Parker Newman --- Changes in v4: - Moved to separate patch drivers/tty/serial/8250/8250_exar.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 6985aabe13cc..5e42558cbb01 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -147,7 +147,7 @@ * * MPIO Port Function * ---- ---- -------- - * 0 2 Mode bit 0 + * 0 2 Mode bit 0 * 1 2 Mode bit 1 * 2 2 Terminate bus * 3 - @@ -229,8 +229,8 @@ struct exar8250_platform { int (*rs485_config)(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485); const struct serial_rs485 *rs485_supported; - int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); - void (*unregister_gpio)(struct uart_8250_port *); + int (*register_gpio)(struct pci_dev *pcidev, struct uart_8250_port *port); + void (*unregister_gpio)(struct uart_8250_port *port); }; /** @@ -245,8 +245,8 @@ struct exar8250_board { unsigned int num_ports; unsigned int reg_shift; int (*board_init)(struct exar8250 *priv, struct pci_dev *pcidev); - int (*setup)(struct exar8250 *, struct pci_dev *, - struct uart_8250_port *, int); + int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev, + struct uart_8250_port *port, int idx); void (*exit)(struct pci_dev *pcidev); }; -- 2.43.2