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Wed, 17 Apr 2024 00:30:31 -0700 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v1 1/3] Documentation/ABI: Add document for Mellanox PMC driver Date: Wed, 17 Apr 2024 03:30:16 -0400 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DA:EE_|CY5PR12MB6322:EE_ X-MS-Office365-Filtering-Correlation-Id: 21f133db-73d8-4d09-0467-08dc5eb04c52 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /xw1ONsnoNxcb5GBU2GUD4bfHCju+g/MKWZQ4anm9CzPNshc9eKWjHp/So6l4kvAxznXD1llnpejW7UEmcFAvK4zXoDZW8Qk6RSz4o7djmwJoguj75jyIpno5J6I4p7rMQT6nXI2m8G5Q/OSmN+6ovUbZIXFCwd5XxM4CmeUDcU1FVFumkENJSSdbVu0FRaHu9Ti3H1VmJUDmV5CMs7QX4EzTzOTrJuo1D8XSQpdTrpXmY4xB0Kp7+yijLPxcXwjHs0mHmQto+jA859reaL2/pJtUnOLhJ+TAVe/fIRenQF3CdsxXr3PpOsIM8caeJaMj30XJPySnVFOJ78ku5uQv7SgFB3JtvKgDWaZ7WSgBd2r+zPvLlnovetaKwZtcNVwGTKdhOhufsn83gvYmLsWLY3R2+HYJl4VdnI7IA1gJDlOCsJizdp3WPwBqmK7HRGy8PYVOz+YhoCt52f+JZt0VeUBJyIhnZz2FiCv7wmVqr6I5IU7ezP30trWY12oyxs7Tbn5+PYba6O1sOTTzCP6RbKSh02ZFLe3a7oyYY5iKumTzlT0BMue+KER7lRE1tCI1aLA18Nmv1MEAuuAubHCueD0XuG1CxmuEMvj0thbWTI5WAUqiNVdrEKiuDAW5h4ShLuv7Tg25mgtCHsV7VO+JNx8jfZ0P3mPCZycxCIZi+ozUBUi3gG+gWTdkvdpbueXlwxttLHtBmHzeAFqL5TP5mR2866Z1FdOlKhyPxbDZp7xoill5HGQUdVX1BEXAj5k X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(82310400014)(376005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2024 07:30:46.6060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21f133db-73d8-4d09-0467-08dc5eb04c52 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DA.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6322 Content-Type: text/plain; charset="utf-8" The sysfs interface is created for programming and monitoring the performance counters in various HW blocks of Mellanox BlueField-1, BlueField-2 and BlueField-3. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson --- .../ABI/testing/sysfs-platform-mellanox-pmc | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-mellanox-pmc diff --git a/Documentation/ABI/testing/sysfs-platform-mellanox-pmc b/Docume= ntation/ABI/testing/sysfs-platform-mellanox-pmc new file mode 100644 index 000000000000..47094024dbeb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-mellanox-pmc @@ -0,0 +1,49 @@ +HID Driver Description +MLNXBFD0 mlxbf-pmc Performance counters (BlueField-1) +MLNXBFD1 mlxbf-pmc Performance counters (BlueField-2) +MLNXBFD2 mlxbf-pmc Performance counters (BlueField-3) + +What: /sys/bus/platform/devices//hwmon/hwmonX//event_list +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + List of events supported by the counters in the specific block. + It is used to extract the event number or ID associated with + each event. + +What: /sys/bus/platform/devices//hwmon/hwmonX//event +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Event monitored by corresponding counter. This is used to + program or read back the event that should be or is currently + being monitored by counter. + +What: /sys/bus/platform/devices//hwmon/hwmonX//counter +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Counter value of the event being monitored. This is used to + read the counter value of the event which was programmed using + event. This is also used to clear or reset the counter value. + +What: /sys/bus/platform/devices//hwmon/hwmonX//enable +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Start or stop counters. This is used to start the counters + for monitoring the programmed events and also to stop the + counters after the desired duration. + +What: /sys/bus/platform/devices//hwmon/hwmonX// +Date: Dec 2020 +KernelVersion: 5.10 +Contact: "Shravan Kumar Ramani " +Description: + Value of register. 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Wed, 17 Apr 2024 00:30:33 -0700 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v1 2/3] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count Date: Wed, 17 Apr 2024 03:30:17 -0400 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343C:EE_|IA1PR12MB6211:EE_ X-MS-Office365-Filtering-Correlation-Id: 95f178ef-c55c-4229-fcba-08dc5eb04efa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WIDnOVb3BeIjrkrf/AJMp2ZbuR35eT9ZjHkMaGshPW8Tz+eiw8JNOr+O61ybrGhkc0Rc/GvfffTUveFx3ctOWc3yEMHSccLCUY+3kgRsvmKZhcRnDW8D6HS9TDG8REPI6E+s9zuVZ3ofa74G2i8Qcak8b+1A6c0SR0OTQopivHppWhaI/kNVGyY/3F7mV2I/RgnlmIQ27ucL2d8GXTPrIfLSl0hi8L6/iot/iIdpCX7+NdKR5LeQvIIltRAaBc6dXT19TUGVYFk67bKKHGAZCcapAPFQGhqt/MI2mNyAIwGJkfX9F/iJybgKxmO5nIxBI/cLOyYlHIQcqHUhjA0nnmEqZ60PyxyMX94XguQmhhnoCYpX38zlTbUArSvd1C8d0PHRkahtx2zNdbEUwKmlr2mMopZMdfG9lqW6FAby6v3XN+OenXJ7otNi/hRev82ooZAxMVqro0f1sJUueEZqUwMY06mujnm3rEQxDllipXCgH6FSs9paJ0O8itX9a4bgZqDtQO+f19frF43495NXYnNornAdR9hKLAKfyMEpze+aNaM7UbFhoPFsfVCVeR/+632q2IFFqcuTx4sK+I7QwI5aYryujSGWDFUN7YFL55qVlWTuvvAfKKzqk/CzEdRZwsabds7R2GCoEFgwhWn7VMRsb9fOy1Urs8mKnwfjcxRvuQsDCXPp6Z7i448bPMZsONHd5mZ7+V1chleMCWFTaoGKR+f5B1BhROrUkT87N5U/PkFWDsIKc/7w6K+08iZb X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(376005)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2024 07:30:51.0688 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95f178ef-c55c-4229-fcba-08dc5eb04efa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6211 Content-Type: text/plain; charset="utf-8" Add support for programming any counter to monitor the cycle count. Since counting of cycles using 32-bit ocunters would result in frequent wraparounds, add the ability to combine 2 adjacent 32-bit counters to form 1 64-bit counter. Both these features are supported by BlueField-3 PMC hardware, hence the required bit-fields are exposed by the driver via sysfs to allow the user to configure as needed. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 134 ++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mella= nox/mlxbf-pmc.c index 4ed9c7fd2b62..635ecc3b3845 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -88,6 +88,8 @@ #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_RE= G0_SZ) #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30) #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28) +#define MLXBF_PMC_CRSPACE_PERFMON_UOC GENMASK(15, 0) +#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMO= N_CTL(n) + 0x4) #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n= ) + 0xc) =20 /** @@ -114,6 +116,8 @@ struct mlxbf_pmc_attribute { * @attr_event: Attributes for "event" sysfs files * @attr_event_list: Attributes for "event_list" sysfs files * @attr_enable: Attributes for "enable" sysfs files + * @attr_use_odd_counter: Attributes for "use_odd_counter" sysfs files + * @attr_count_clock: Attributes for "count_clock" sysfs files * @block_attr: All attributes needed for the block * @block_attr_grp: Attribute group for the block */ @@ -126,6 +130,8 @@ struct mlxbf_pmc_block_info { struct mlxbf_pmc_attribute *attr_event; struct mlxbf_pmc_attribute attr_event_list; struct mlxbf_pmc_attribute attr_enable; + struct mlxbf_pmc_attribute attr_use_odd_counter; + struct mlxbf_pmc_attribute attr_count_clock; struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS]; struct attribute_group block_attr_grp; }; @@ -1763,6 +1769,103 @@ static ssize_t mlxbf_pmc_enable_store(struct device= *dev, return count; } =20 +/* Show function for "use_odd_counter" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_use_odd_counter_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_use_odd_counter =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 value, reg; + + blk_num =3D attr_use_odd_counter->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + value =3D FIELD_GET(MLXBF_PMC_CRSPACE_PERFMON_UOC, reg); + + return sysfs_emit(buf, "%u\n", value); +} + +/* Store function for "use_odd_counter" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_use_odd_counter_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_use_odd_counter =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 uoc, reg; + int err; + + blk_num =3D attr_use_odd_counter->nr; + + err =3D kstrtouint(buf, 0, &uoc); + if (err < 0) + return err; + + err =3D mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + ®); + if (err) + return -EINVAL; + + reg &=3D ~MLXBF_PMC_CRSPACE_PERFMON_UOC; + reg |=3D FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_UOC, uoc); + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + +/* Show function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_count_clock =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + + blk_num =3D attr_count_clock->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", reg); +} + +/* Store function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_count_clock =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + int err; + + blk_num =3D attr_count_clock->nr; + + err =3D kstrtouint(buf, 0, ®); + if (err < 0) + return err; + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + /* Populate attributes for blocks with counters to monitor performance */ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned in= t blk_num) { @@ -1799,6 +1902,37 @@ static int mlxbf_pmc_init_perftype_counter(struct de= vice *dev, unsigned int blk_ attr =3D NULL; } =20 + if (pmc->block[blk_num].type =3D=3D MLXBF_PMC_TYPE_CRSPACE) { + /* + * Couple adjacent odd and even 32-bit counters to form 64-bit counters + * using "use_odd_counter" sysfs which has one bit per even counter. + */ + attr =3D &pmc->block[blk_num].attr_use_odd_counter; + attr->dev_attr.attr.mode =3D 0644; + attr->dev_attr.show =3D mlxbf_pmc_use_odd_counter_show; + attr->dev_attr.store =3D mlxbf_pmc_use_odd_counter_store; + attr->nr =3D blk_num; + attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, + "use_odd_counter"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] =3D &attr->dev_attr.attr; + attr =3D NULL; + + /* Program crspace counters to count clock cycles using "count_clock" sy= sfs */ + attr =3D &pmc->block[blk_num].attr_count_clock; + attr->dev_attr.attr.mode =3D 0644; + attr->dev_attr.show =3D mlxbf_pmc_count_clock_show; + attr->dev_attr.store =3D mlxbf_pmc_count_clock_store; + attr->nr =3D blk_num; + attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, + "count_clock"); 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Wed, 17 Apr 2024 00:30:36 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Wed, 17 Apr 2024 00:30:36 -0700 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Wed, 17 Apr 2024 00:30:35 -0700 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v1 3/3] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block Date: Wed, 17 Apr 2024 03:30:18 -0400 Message-ID: <433fac1cffd9128a10eb2eff85b11ff671c9962f.1713334019.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|IA1PR12MB8190:EE_ X-MS-Office365-Filtering-Correlation-Id: d10587c7-e00c-4726-a5b3-08dc5eb04ded X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Apr 2024 07:30:49.3036 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d10587c7-e00c-4726-a5b3-08dc5eb04ded X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8190 Content-Type: text/plain; charset="utf-8" The HW clock_measure counter info is passed to the driver from ACPI. Create a new sub-directory for clock_measure events and provide read access to the user. Writes are blocked since the fields are RO. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mella= nox/mlxbf-pmc.c index 635ecc3b3845..1212a96fb3eb 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -865,6 +865,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_mis= s_events[] =3D { {75, "HISTOGRAM_HISTOGRAM_BIN9"}, }; =20 +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] =3D { + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, +}; + static struct mlxbf_pmc_context *pmc; =20 /* UUID used to probe ATF service. */ @@ -1038,6 +1069,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event= _list(const char *blk, size } else if (strstr(blk, "llt")) { events =3D mlxbf_pmc_llt_events; size =3D ARRAY_SIZE(mlxbf_pmc_llt_events); + } else if (strstr(blk, "clock_measure")) { + events =3D mlxbf_pmc_clock_events; + size =3D ARRAY_SIZE(mlxbf_pmc_clock_events); } else { events =3D NULL; size =3D 0; @@ -1472,14 +1506,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_nu= m, u32 cnt_num, bool is_l3, u /* Method to read a register */ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *resul= t) { - u32 ecc_out; + u32 reg; =20 - if (strstr(pmc->block_name[blk_num], "ecc")) { + if ((strstr(pmc->block_name[blk_num], "ecc")) || + (strstr(pmc->block_name[blk_num], "clock_measure"))) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, - &ecc_out)) + ®)) return -EFAULT; =20 - *result =3D ecc_out; + *result =3D reg; return 0; } =20 @@ -1493,6 +1528,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u= 32 offset, u64 *result) /* Method to write to a register */ static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { + if (strstr(pmc->block_name[blk_num], "clock_measure")) + return -EINVAL; + if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, MLXBF_PMC_WRITE_REG_32, data); --=20 2.30.1