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Tue, 16 Apr 2024 14:56:36 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v3 1/8] serial: exar: adding missing CTI and Exar PCI ids Date: Tue, 16 Apr 2024 08:55:28 -0400 Message-ID: <7c3d8e795a864dd9b0a00353b722060dc27c4e09.1713270624.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:/xHh/AkH89Z8uGkzl5PbTvHd7qBh0BgC800ou4B0KmtKs6cDYjz HbOFWxvfzTXW9n7JjOTkKQXMzE/QhwqP6fmXRvSBRFsTD0tTNRtbfKzDIVK3nhpURdGeDD4 JfH1FYENDaGag5mrE4JwuNjnLIwjI2qyawEyh3cT21j1dk1xZWcuAgUdNLrP2loO/XXkaXJ ti71253uQEFfSAkbmGCeQ== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:q/udNzQOnbI=;shTdRZPHhz1v4L9TEhcRavEEyX3 HhiWhZav0LU1ooDIfslUgonWfaxmqsrSHFBT5ya4t7mlS/GrQbDy95FyVOj8ciS4BZtnW1HQI TLc+ndgCMLDarGf66tVa0rQUYf2+Q9dNsGp1o3rE/nIQIUu5jV8P3xx1OQyorfSEf3dwP7CDn kj5bpygksnKyqf1Yq/eU0m9hwG44chATqzPV11xln+KFZyaZFtLw3QQdZu2sygjKy7YaHF8Yj IlUoXwPwVTjGFjGUGVYRyNqIRiv533CCjwi4a35dbxQD6dmBTiNsKqHdcDQjvh5TK4nE8Zn1g eiZp/ytmzQFfuTTuvFMj9OPUf/Dqz/s/971Ho4ybjmz60WwnIukxgyzYGZj3uFGlH9DMFMaLj ZtrqrQFFN9CASjdoGiS8W4ev59qK8vsiWQISrFdFtJas0P5qxg0Et2JHiqW4wcbrU1mxkHHWk nH1rSLSTcD+AHU0Tedw+9x5Lhq+5AsDuxtwQlZFmyBzLH+P3a7woGHCQexHwE8Exur1tUEraz +CRQ7pqRO4+0xYKv9d9NO8z9M9LszxyRtfRCb4q5WVmD/8RrSDACmKk64T7ocuIOZ2pIbNKdw yJAaosb70AqjYB46Fs7vS9ed/LG5Gly1+enPdnTbAiwhwRr7p7PGeYW0Cxa3/3PkzouM9BPg7 MloAoeaY8l96PRZw5cnOkSQWHiddgIejbVnSV2tLvnGWXqfpYhNSOktE4/zU0vL9wAx2396wZ LVX9eVdddMwhwXwtAmb02wWZ8UvlzqD55jrfBUefLJiJJCSCDctEyE= Content-Type: text/plain; charset="utf-8" From: Parker Newman - Added Connect Tech and Exar IDs not already in pci_ids.h Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 42 +++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 0440df7de1ed..4d1e07343d0b 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -46,8 +46,50 @@ #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 +#define PCI_VENDOR_ID_CONNECT_TECH 0x12c4 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO 0x0340 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A 0x0341 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B 0x0342 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS 0x0350 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A 0x0351 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B 0x0352 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS 0x0353 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A 0x0354 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B 0x0355 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO 0x0360 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A 0x0361 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B 0x0362 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP 0x0370 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232 0x0371 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485 0x0372 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP 0x0373 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP 0x0374 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP 0x0375 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS 0x0376 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT 0x0380 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT 0x0381 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO 0x0382 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO 0x0392 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP 0x03A0 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232 0x03A1 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485 0x03A2 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS 0x03A3 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XEG001 0x0602 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_BASE 0x1000 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_2 0x1002 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_4 0x1004 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_8 0x1008 +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_12 0x100C +#define PCI_SUBDEVICE_ID_CONNECT_TECH_PCIE_XR35X_16 0x1010 +#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X 0x110c +#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X 0x110d +#define PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16 0x1110 + #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 +#define PCI_DEVICE_ID_EXAR_XR17V252 0x0252 +#define PCI_DEVICE_ID_EXAR_XR17V254 0x0254 +#define PCI_DEVICE_ID_EXAR_XR17V258 0x0258 #define PCI_SUBDEVICE_ID_USR_2980 0x0128 #define PCI_SUBDEVICE_ID_USR_2981 0x0129 -- 2.43.2 From nobody Wed Feb 11 03:51:31 2026 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF77628E6; 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Tue, 16 Apr 2024 14:56:36 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v3 2/8] serial: exar: remove old Connect Tech setup Date: Tue, 16 Apr 2024 08:55:29 -0400 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:tUm/cSDLboyH1ISWswfOkWKv27rJSe9V8B/rZvcDNSuobuuQYpd lvvyW3yEbQRVS7uA2VfbI1RR4cQ+WF4G3p4THBjga0M9GlaeKZk90iqlT4N2f6EZnVoRbDk minojfnFEP8flDehuE/1Gvm1Oz+r+A5G7XgoD9YGPrESP989cLZdPVLquhEYYGplc0+fS/0 m39kdFlVtbotjlx6nuX6Q== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:obspGj4EhAw=;JJTplzmRPYtAgS6qB35fBIkvE// BeTnDT8OFK8HkAKi6Xs6BUdWEbOdKyWq1kk7jykPmoDP/RK3BRnme4qKLD8CdKkczYAy1baux 8NX+vbZAtaXqQVahvntl3VuBfLcgRCYg3UBVgXyKChlYBVQFBEugpj2Gb8aGVgoR1cmY2AKsG jviVEJjlwM2ZJ/kAPwU6QLwppG4A75B0IPexF+DZzonk0ZrfUi0hSsa+9h/odJo8Q225qiiqQ nEoZnOmLRsooeOnUko/ErZ5ahgVhzsQtREGm75zkxX6ZAM3VEjSRhb9sr6hG0QePhktWVzo2/ we2Y2rE2trC1u/BsX68spkDAlgUZGUlTqmQM7StQhLnoPxFU9ouQMEjT2DLFlidIP2LCtsAUP 9aad47PU6m0yGl9f7L7ZA4IlcPDzbd6UQkjtK/m+Go0xj/OV8eEqmnWnSaEqit7gnlfg13cx5 J4xZyDb5n4sPJDvDUve9hiWej/uIhNl+Ze21baK2/bh84PFXH3g/TsidlXssSNZz8jFMoqEpu HFKioHHmNIQwoe4SqcVGJDT53LNdaSnGIPwWf1o30cEfmRz0d1aeFz36oATqsWrL0Pyo1snIK h7w/wfyGZQmDKsdelNA8wCMzBiN+evBPYNgDA7DRijenOvm96HSSdIWEYdfISF0lJUOt5Klp6 3DTS5XPoraUTfJsJlvAhbrnN5RgDXX0RvP79fBmIPfy7mqS9lm9e1MHINJZ/g+Ifu0D/eeACL nDIi0pYXsKQ1O+ZhaQKDEm+OsIeW6Gyf0CRB7b2NKUyC5BL/o+qGc4= Content-Type: text/plain; charset="utf-8" From: Parker Newman Preparatory patch removing existing Connect Tech setup code and CONNECT_DEVICE macro. Changes in v3: - Split code removals to own patch Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 37 ----------------------------- 1 file changed, 37 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 4d1e07343d0b..3565b880f512 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -357,17 +357,6 @@ pci_fastcom335_setup(struct exar8250 *priv, struct pci= _dev *pcidev, return 0; } -static int -pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, - struct uart_8250_port *port, int idx) -{ - unsigned int offset =3D idx * 0x200; - unsigned int baud =3D 1843200; - - port->port.uartclk =3D baud * 16; - return default_setup(priv, pcidev, idx, offset, port); -} - static int pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, struct uart_8250_port *port, int idx) @@ -848,10 +837,6 @@ static const struct exar8250_board pbn_fastcom335_8 = =3D { .setup =3D pci_fastcom335_setup, }; -static const struct exar8250_board pbn_connect =3D { - .setup =3D pci_connect_tech_setup, -}; - static const struct exar8250_board pbn_exar_ibm_saturn =3D { .num_ports =3D 1, .setup =3D pci_xr17c154_setup, @@ -896,15 +881,6 @@ static const struct exar8250_board pbn_exar_XR17V8358 = =3D { .exit =3D pci_xr17v35x_exit, }; -#define CONNECT_DEVICE(devid, sdevid, bd) { \ - PCI_DEVICE_SUB( \ - PCI_VENDOR_ID_EXAR, \ - PCI_DEVICE_ID_EXAR_##devid, \ - PCI_SUBVENDOR_ID_CONNECT_TECH, \ - PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ - (kernel_ulong_t)&bd \ - } - #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } #define IBM_DEVICE(devid, sdevid, bd) { \ @@ -934,19 +910,6 @@ static const struct pci_device_id exar_pci_tbl[] =3D { EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), - CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), - CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), - CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), - CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), - IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), /* USRobotics USR298x-OEM PCI Modems */ -- 2.43.2 From nobody Wed Feb 11 03:51:31 2026 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B7C312BF34; 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Tue, 16 Apr 2024 14:56:36 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v3 3/8] serial: exar: added a exar_get_nr_ports function Date: Tue, 16 Apr 2024 08:55:30 -0400 Message-ID: <56bda5690e76a297bdec6768ea1f5d11c32e5eed.1713270624.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:uCv4vkQ33eN02KL/ElIF9H4MqZXklXDLUNpgf/pe4WOXXYWzAy+ 4SoeRHdj6agPH08sp5szYCC8/qiYLVO3hWHSdxQIgkyBYYfP4rcKnFzGuMNTXmNvWXGrvQz XpYrn7Pxl3OQTcY5slnizBMcDFBht2oWZH9EHiRqgtnov2ta4tnVCCaokE/xE73pbHnrob3 FSsg3rDz97sRvlLy9VGgg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:Xf9sIUOeSHE=;/edaBReefVY65VfKAskOva2NsFn EyAg+JEWGlSJzmtHT9gBvne1ukFw6a8mQ+LJPVvcJ3N2rb2HfK7eaoO0zyJ68q0LkugBxSv4P OQn8ue60inu9O9mnoENNeq8GEx+DI0UNrsMmJ8cIMit7Yq7weoAXahzD4eg9h7NA6NJ6kwOtI RY7Dhe3Tbmzr5O6CBvwcEb/4QrvNhh1GP+G0gYlmC+U7uNDr18k1BTYVj9eCW07vRhhhmunba f8DQnSTuoocz1iVj6r8HEeEITXDgVC7qmfeOJpnpIMgjhqx5wVOzzewVc9XdMdgt3aPI4P+nh yQUshury6VtJYOm4eaee/s5Ee/a3Lvw3WWf7BBKT1vx4/X2hVcOnBJhzicT4vEbcPxZKCsoY7 Y58hNrUiuydgblq1gHsfFZzt+ODH9MQ7AJYlt+KRcOoRfrE7jRqH6GI70rUSO/pv3ZoQOyYaU T5rEHfm61nRC0fZNYVcDDD8UsGdx8dEUaypdsrhNfskt5MBL91FN2HWJ2LAPNd4slGMGUxZbP 7TIsQ5ch1+2n0oRxligJhbvFWzVJW0ghkcD2Ej9EHhdA2nmPHhX+LKQQMPJ3BjPZ8ctBdDyEJ XRdmpyZi7WcuAHc3itTzMqtDw/VHX+0ge2SRh2eSxYRzZpRP2W9mk2mQCR76weqSK8QAd4mkj 0DiOBqFC0x+hfcNdurHOEMpMLn3lR02LJxPZz7ALVUSzA/lk/ol36sv/dOu5vqRc16HmrHfRT cHy6g8LLG0Ubg9cEK6Ppm9+kikVPvc307r57yeZ2fKFvdBJzkn+Wtc= Content-Type: text/plain; charset="utf-8" From: Parker Newman Moved code for getting number of ports from exar_pci_probe() to a separate exar_get_nr_ports() function. Chnages in v3: - Only moved existing code in this patch, will add CTI code in subsequent patch Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 3565b880f512..388dd60ad23a 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -703,6 +703,21 @@ static irqreturn_t exar_misc_handler(int irq, void *da= ta) return IRQ_HANDLED; } +static unsigned int exar_get_nr_ports(struct exar8250_board *board, + struct pci_dev *pcidev) +{ + unsigned int nr_ports =3D 0; + + if (pcidev->vendor =3D=3D PCI_VENDOR_ID_ACCESSIO) + nr_ports =3D BIT(((pcidev->device & 0x38) >> 3) - 1); + else if (board->num_ports) + nr_ports =3D board->num_ports; + else + nr_ports =3D pcidev->device & 0x0f; + + return nr_ports; +} + static int exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) { @@ -722,12 +737,12 @@ exar_pci_probe(struct pci_dev *pcidev, const struct p= ci_device_id *ent) maxnr =3D pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 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charset="utf-8" From: Parker Newman - Add an optional "board_init()" function pointer to struct exar8250_board which is called once during probe prior to setting up the ports. - Fix several "missing identifier name" warnings from checkpatch in struct exar8250_platform and struct exar8250_board: WARNING: function definition argument should also have an identifier name - Fix warning from checkpatch: WARNING: please, no space before tabs + * 0^I^I2 ^IMode bit 0$ Changes in v3: - Renamed board_setup to board_init. - Changed pci_err to dev_err_probe - Added note above about checkpatch fixes Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 388dd60ad23a..cf7900bd2974 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -133,7 +133,7 @@ * * MPIO Port Function * ---- ---- -------- - * 0 2 Mode bit 0 + * 0 2 Mode bit 0 * 1 2 Mode bit 1 * 2 2 Terminate bus * 3 - @@ -169,22 +169,24 @@ struct exar8250_platform { int (*rs485_config)(struct uart_port *port, struct ktermios *termios, struct serial_rs485 *rs485); const struct serial_rs485 *rs485_supported; - int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); - void (*unregister_gpio)(struct uart_8250_port *); + int (*register_gpio)(struct pci_dev *pcidev, struct uart_8250_port *port); + void (*unregister_gpio)(struct uart_8250_port *port); }; /** * struct exar8250_board - board information * @num_ports: number of serial ports * @reg_shift: describes UART register mapping in PCI memory - * @setup: quirk run at ->probe() stage + * @board_init: quirk run once at ->probe() stage before setting up ports + * @setup: quirk run at ->probe() stage for each port * @exit: quirk run at ->remove() stage */ struct exar8250_board { unsigned int num_ports; unsigned int reg_shift; - int (*setup)(struct exar8250 *, struct pci_dev *, - struct uart_8250_port *, int); + int (*board_init)(struct exar8250 *priv); + int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev, + struct uart_8250_port *port, int idx); void (*exit)(struct pci_dev *pcidev); }; @@ -772,6 +774,15 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pc= i_device_id *ent) if (rc) return rc; + if (board->board_init) { + rc =3D board->board_init(priv); + if (rc) { + dev_err_probe(&pcidev->dev, rc, + "failed to init serial board\n"); + return rc; + } + } + for (i =3D 0; i < nr_ports && i < maxnr; i++) { rc =3D board->setup(priv, pcidev, &uart, i); if (rc) { -- 2.43.2 From nobody Wed Feb 11 03:51:31 2026 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B60D212BF15; Tue, 16 Apr 2024 12:56:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713272217; cv=none; b=PvCEHE55no3KhZo1CaZOBoID4/36D9g5SxY3ktU3/3tK5cDgqLZFcTuSQzvxdvVD5o+wqSJFjJoCF3OSYjKnw8C39W3SbBA4CwPDfodEItS2fDAa/anvJSA+ni8cLQu4EMHK7TTAJncGpLwbZOzZBK/weVSHb01NHD8w4KmdIfk= ARC-Message-Signature: i=1; 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charset="utf-8" From: Parker Newman Preparatory patch moving generic_rs485_config and generic_rs485_supported higher in the file to allow for CTI setup functions to use it. Changes in v3: - split into separate preparatory patch Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 50 ++++++++++++++--------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index cf7900bd2974..7e47a4145c7b 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -197,6 +197,31 @@ struct exar8250 { int line[]; }; +static int generic_rs485_config(struct uart_port *port, struct ktermios *t= ermios, + struct serial_rs485 *rs485) +{ + bool is_rs485 =3D !!(rs485->flags & SER_RS485_ENABLED); + u8 __iomem *p =3D port->membase; + u8 value; + + value =3D readb(p + UART_EXAR_FCTR); + if (is_rs485) + value |=3D UART_FCTR_EXAR_485; + else + value &=3D ~UART_FCTR_EXAR_485; + + writeb(value, p + UART_EXAR_FCTR); + + if (is_rs485) + writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); + + return 0; +} + +static const struct serial_rs485 generic_rs485_supported =3D { + .flags =3D SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, +}; + static void exar_pm(struct uart_port *port, unsigned int state, unsigned i= nt old) { /* @@ -458,27 +483,6 @@ static void xr17v35x_unregister_gpio(struct uart_8250_= port *port) port->port.private_data =3D NULL; } -static int generic_rs485_config(struct uart_port *port, struct ktermios *t= ermios, - struct serial_rs485 *rs485) -{ - bool is_rs485 =3D !!(rs485->flags & SER_RS485_ENABLED); - u8 __iomem *p =3D port->membase; - u8 value; - - value =3D readb(p + UART_EXAR_FCTR); - if (is_rs485) - value |=3D UART_FCTR_EXAR_485; - else - value &=3D ~UART_FCTR_EXAR_485; - - writeb(value, p + UART_EXAR_FCTR); - - if (is_rs485) - writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); - - return 0; -} - static int sealevel_rs485_config(struct uart_port *port, struct ktermios *= termios, struct serial_rs485 *rs485) { @@ -517,10 +521,6 @@ static int sealevel_rs485_config(struct uart_port *por= t, struct ktermios *termio return 0; } -static const struct serial_rs485 generic_rs485_supported =3D { - .flags =3D SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, -}; - static const struct exar8250_platform exar8250_default_platform =3D { .register_gpio =3D xr17v35x_register_gpio, .unregister_gpio =3D xr17v35x_unregister_gpio, -- 2.43.2 From nobody Wed Feb 11 03:51:31 2026 Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3EF712BE8C; Tue, 16 Apr 2024 12:56:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713272215; cv=none; b=Gw/zlyq4EfdnFFEEOqSwW9sMjItTHXtqFS1RWr1MSG3TWe0qg3Rwko84gOAGnXHhup1Niizf+dlog2ijqvnhTdWp87Xop7Rod0sZ1SjfKGi7P6nflsG3N4W5yg3P5ldEvnwWwD0yrkDuj+j3cF717fG6OQtK3tfNdfbnlznoV/8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713272215; c=relaxed/simple; bh=NQhqySD6CGl5aYpely4K4CDmCz7g+Tp64db5QcIZwkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" From: Parker Newman Add code for getting number of ports of CTI cards to exar_get_nr_ports() Changes in v3: - moved to separate patch - added spaces to single line comments Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 7e47a4145c7b..ada01c6394a3 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -710,12 +710,28 @@ static unsigned int exar_get_nr_ports(struct exar8250= _board *board, { unsigned int nr_ports =3D 0; - if (pcidev->vendor =3D=3D PCI_VENDOR_ID_ACCESSIO) + if (pcidev->vendor =3D=3D PCI_VENDOR_ID_ACCESSIO) { nr_ports =3D BIT(((pcidev->device & 0x38) >> 3) - 1); - else if (board->num_ports) + } else if (board->num_ports > 0) { + // Check if board struct overrides number of ports nr_ports =3D board->num_ports; - else + } else if (pcidev->vendor =3D=3D PCI_VENDOR_ID_EXAR) { + // Exar encodes # ports in last nibble of PCI Device ID ex. 0358 nr_ports =3D pcidev->device & 0x0f; + } else if (pcidev->vendor =3D=3D PCI_VENDOR_ID_CONNECT_TECH) { + // Handle CTI FPGA cards + switch (pcidev->device) { + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X: + nr_ports =3D 12; + break; + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16: + nr_ports =3D 16; + break; + default: + break; + } + } return nr_ports; } -- 2.43.2 From nobody Wed Feb 11 03:51:31 2026 Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB55812C481; Tue, 16 Apr 2024 12:56:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.208.4.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713272219; cv=none; b=kKhKfhMjq2ijTt9vqRGMf9OO9klrmvT12HPCBB1lUawpSArWrnvr2hogAhSnvkObNjNL7UcQwCMTPprAGFeKN8wnOMYlROFahMithIMIUA++ZyqmFv1rr2b9O5vlIObUuXLkjPUeyQY7Z1CusWgt9769fMXLHinZTTA+g9DiH9M= ARC-Message-Signature: i=1; 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charset="utf-8" From: Parker Newman This is a large patch but is only additions. All changes and removals are made in previous patches in this series. - Add CTI board_init and port setup functions for each UART type - Add CTI_EXAR_DEVICE() and CTI_PCI_DEVICE() macros - Add support for reading a word from the Exar EEPROM. - Add support for configuring and setting a single MPIO - Add various helper functions for CTI boards. - Add osc_freq, pcidev, dev to struct exar8250 Changes in v3: - Moved all base driver changes and refactoring to preparatory patches - Switched any user space types to kernel types - Switched all uses of pci_xxx print functions to dev_xxx - Added struct device pointer in struct exar8250 to simplify above - Switched osc_freq and port_flag parsing to use GENMASK() and FIELD_GET()/FIELD_PREP() - Renamed board_setup function pointer to board_init - Removed some unneeded checks for priv being NULL - Added various convenience functions instead of relying on bools ex: exar_mpio_set_low()/exar_mpio_set_high() instead of exar_mpio_set() - Renamed some variables and defines for clarity - Numerous minor formatting fixes Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 899 ++++++++++++++++++++++++++++ 1 file changed, 899 insertions(+) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index ada01c6394a3..501b9f3e9c89 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include #include @@ -128,6 +130,19 @@ #define UART_EXAR_DLD 0x02 /* Divisor Fractional */ #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ +/* EEPROM registers */ +#define UART_EXAR_REGB 0x8e +#define UART_EXAR_REGB_EECK BIT(4) +#define UART_EXAR_REGB_EECS BIT(5) +#define UART_EXAR_REGB_EEDI BIT(6) +#define UART_EXAR_REGB_EEDO BIT(7) +#define UART_EXAR_REGB_EE_ADDR_SIZE 6 +#define UART_EXAR_REGB_EE_DATA_SIZE 16 + +#define UART_EXAR_XR17C15X_PORT_OFFSET 0x200 +#define UART_EXAR_XR17V25X_PORT_OFFSET 0x200 +#define UART_EXAR_XR17V35X_PORT_OFFSET 0x400 + /* * IOT2040 MPIO wiring semantics: * @@ -163,6 +178,52 @@ #define IOT2040_UARTS_ENABLE 0x03 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ +/* CTI EEPROM offsets */ +#define CTI_EE_OFF_XR17C15X_OSC_FREQ 0x04 /* 2 words */ +#define CTI_EE_OFF_XR17V25X_OSC_FREQ 0x08 /* 2 words */ +#define CTI_EE_OFF_XR17C15X_PART_NUM 0x0A /* 4 words */ +#define CTI_EE_OFF_XR17V25X_PART_NUM 0x0E /* 4 words */ +#define CTI_EE_OFF_XR17C15X_SERIAL_NUM 0x0E /* 1 word */ +#define CTI_EE_OFF_XR17V25X_SERIAL_NUM 0x12 /* 1 word */ +#define CTI_EE_OFF_XR17V35X_SERIAL_NUM 0x11 /* 2 word */ +#define CTI_EE_OFF_XR17V35X_BRD_FLAGS 0x13 /* 1 word */ +#define CTI_EE_OFF_XR17V35X_PORT_FLAGS 0x14 /* 1 word */ + +#define CTI_EE_MASK_PORT_FLAGS_TYPE GENMASK(7, 0) +#define CTI_EE_MASK_OSC_FREQ_LOWER GENMASK(15, 0) +#define CTI_EE_MASK_OSC_FREQ_UPPER GENMASK(31, 16) + +#define CTI_FPGA_RS485_IO_REG 0x2008 +#define CTI_FPGA_CFG_INT_EN_REG 0x48 +#define CTI_FPGA_CFG_INT_EN_EXT_BIT BIT(15) /* External int enable bit */ + +#define CTI_DEFAULT_PCI_OSC_FREQ 29491200 +#define CTI_DEFAULT_PCIE_OSC_FREQ 125000000 +#define CTI_DEFAULT_FPGA_OSC_FREQ 33333333 + +/* + * CTI Serial port line types. These match the values stored in the first + * nibble of the CTI EEPROM port_flags word. + */ +enum cti_port_type { + CTI_PORT_TYPE_NONE =3D 0, + CTI_PORT_TYPE_RS232, // RS232 ONLY + CTI_PORT_TYPE_RS422_485, // RS422/RS485 ONLY + CTI_PORT_TYPE_RS232_422_485_HW, // RS232/422/485 HW ONLY Switchable + CTI_PORT_TYPE_RS232_422_485_SW, // RS232/422/485 SW ONLY Switchable + CTI_PORT_TYPE_RS232_422_485_4B, // RS232/422/485 HW/SW (4bit ex. BCG004) + CTI_PORT_TYPE_RS232_422_485_2B, // RS232/422/485 HW/SW (2bit ex. BBG008) + CTI_PORT_TYPE_MAX, +}; + +#define CTI_PORT_TYPE_VALID(_port_type) \ + (((_port_type) > CTI_PORT_TYPE_NONE) && \ + ((_port_type) < CTI_PORT_TYPE_MAX)) + +#define CTI_PORT_TYPE_RS485(_port_type) \ + (((_port_type) > CTI_PORT_TYPE_RS232) && \ + ((_port_type) < CTI_PORT_TYPE_MAX)) + struct exar8250; struct exar8250_platform { @@ -192,11 +253,214 @@ struct exar8250_board { struct exar8250 { unsigned int nr; + unsigned int osc_freq; + struct pci_dev *pcidev; + struct device *dev; struct exar8250_board *board; void __iomem *virt; int line[]; }; +static inline void exar_write_reg(struct exar8250 *priv, + unsigned int reg, u8 value) +{ + writeb(value, priv->virt + reg); +} + +static inline u8 exar_read_reg(struct exar8250 *priv, unsigned int reg) +{ + return readb(priv->virt + reg); +} + +static inline void exar_ee_select(struct exar8250 *priv) +{ + // Set chip select pin high to enable EEPROM reads/writes + exar_write_reg(priv, UART_EXAR_REGB, UART_EXAR_REGB_EECS); + // Min ~500ns delay needed between CS assert and EEPROM access + udelay(1); +} + +static inline void exar_ee_deselect(struct exar8250 *priv) +{ + exar_write_reg(priv, UART_EXAR_REGB, 0x00); +} + +static inline void exar_ee_write_bit(struct exar8250 *priv, int bit) +{ + u8 value =3D UART_EXAR_REGB_EECS; + + if (bit) + value |=3D UART_EXAR_REGB_EEDI; + + // Clock out the bit on the EEPROM interface + exar_write_reg(priv, UART_EXAR_REGB, value); + // 2us delay =3D ~500khz clock speed + udelay(2); + + value |=3D UART_EXAR_REGB_EECK; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); +} + +static inline u8 exar_ee_read_bit(struct exar8250 *priv) +{ + u8 regb; + u8 value =3D UART_EXAR_REGB_EECS; + + // Clock in the bit on the EEPROM interface + exar_write_reg(priv, UART_EXAR_REGB, value); + // 2us delay =3D ~500khz clock speed + udelay(2); + + value |=3D UART_EXAR_REGB_EECK; + + exar_write_reg(priv, UART_EXAR_REGB, value); + udelay(2); + + regb =3D exar_read_reg(priv, UART_EXAR_REGB); + + return (regb & UART_EXAR_REGB_EEDO ? 1 : 0); +} + +/** + * exar_ee_read() - Read a word from the EEPROM + * @priv: Device's private structure + * @ee_addr: Offset of EEPROM to read word from + * + * Read a single 16bit word from an Exar UART's EEPROM. + * + * Return: EEPROM word + */ +static u16 exar_ee_read(struct exar8250 *priv, u8 ee_addr) +{ + int i; + u16 data =3D 0; + + exar_ee_select(priv); + + // Send read command (opcode 110) + exar_ee_write_bit(priv, 1); + exar_ee_write_bit(priv, 1); + exar_ee_write_bit(priv, 0); + + // Send address to read from + for (i =3D 1 << (UART_EXAR_REGB_EE_ADDR_SIZE - 1); i; i >>=3D 1) + exar_ee_write_bit(priv, (ee_addr & i)); + + // Read data 1 bit at a time + for (i =3D 0; i <=3D UART_EXAR_REGB_EE_DATA_SIZE; i++) { + data <<=3D 1; + data |=3D exar_ee_read_bit(priv); + } + + exar_ee_deselect(priv); + + return data; +} + +/** + * _exar_mpio_config() - Configure an Exar MPIO as input or output + * @priv: Device's private structure + * @mpio_num: MPIO number/offset to configure + * @output: Configure as output if true, inout if false + * + * Configure a single MPIO as an input or output and disable tristate. + * If configuring as output it is reccomended to set value with + * exar_mpio_set_high()/exar_mpio_set_low() prior to calling this function= to + * ensure default MPIO pin state. + * + * Return: 0 on success, negative error code on failure + */ +static int _exar_mpio_config(struct exar8250 *priv, + unsigned int mpio_num, bool output) +{ + unsigned int mpio_offset; + u8 sel_reg; // MPIO Select register (input/output) + u8 tri_reg; // MPIO Tristate register + u8 value; + + if (mpio_num < 8) { + sel_reg =3D UART_EXAR_MPIOSEL_7_0; + tri_reg =3D UART_EXAR_MPIO3T_7_0; + mpio_offset =3D mpio_num; + } else if (mpio_num >=3D 8 && mpio_num < 16) { + sel_reg =3D UART_EXAR_MPIOSEL_15_8; + tri_reg =3D UART_EXAR_MPIO3T_15_8; + mpio_offset =3D mpio_num - 8; + } else { + return -EINVAL; + } + + // Disable MPIO pin tri-state + value =3D exar_read_reg(priv, tri_reg); + value &=3D ~BIT(mpio_offset); + exar_write_reg(priv, tri_reg, value); + + value =3D exar_read_reg(priv, sel_reg); + if (output) + value &=3D ~BIT(mpio_offset); + else + value |=3D BIT(mpio_offset); + exar_write_reg(priv, sel_reg, value); + + return 0; +} + +static int exar_mpio_config_output(struct exar8250 *priv, + unsigned int mpio_num) +{ + return _exar_mpio_config(priv, mpio_num, true); +} + +/** + * _exar_mpio_set() - Set an Exar MPIO output high or low + * @priv: Device's private structure + * @mpio_num: MPIO number/offset to set + * @high: Set MPIO high if true, low if false + * + * Set a single MPIO high or low. exar_mpio_config_output() must also be c= alled + * to configure the pin as an output. + * + * Return: 0 on success, negative error code on failure + */ +static int _exar_mpio_set(struct exar8250 *priv, + unsigned int mpio_num, bool high) +{ + unsigned int mpio_offset; + u8 lvl_reg; + u8 value; + + if (mpio_num < 8) { + lvl_reg =3D UART_EXAR_MPIOLVL_7_0; + mpio_offset =3D mpio_num; + } else if (mpio_num >=3D 8 && mpio_num < 16) { + lvl_reg =3D UART_EXAR_MPIOLVL_15_8; + mpio_offset =3D mpio_num - 8; + } else { + return -EINVAL; + } + + value =3D exar_read_reg(priv, lvl_reg); + if (high) + value |=3D BIT(mpio_offset); + else + value &=3D ~BIT(mpio_offset); + exar_write_reg(priv, lvl_reg, value); + + return 0; +} + +static int exar_mpio_set_low(struct exar8250 *priv, unsigned int mpio_num) +{ + return _exar_mpio_set(priv, mpio_num, false); +} + +static int exar_mpio_set_high(struct exar8250 *priv, unsigned int mpio_num) +{ + return _exar_mpio_set(priv, mpio_num, true); +} + static int generic_rs485_config(struct uart_port *port, struct ktermios *t= ermios, struct serial_rs485 *rs485) { @@ -384,6 +648,582 @@ pci_fastcom335_setup(struct exar8250 *priv, struct pc= i_dev *pcidev, return 0; } +/** + * _cti_set_tristate() - Enable/Disable RS485 transciever tristate + * @priv: Device's private structure + * @port_num: Port number to set tristate on/off + * @enable: Enable tristate if true, disable if false + * + * Most RS485 capable cards have a power on tristate jumper/switch that en= sures + * the RS422/RS485 transciever does not drive a multi-drop RS485 bus when = it is + * not the master. When this jumper is installed the user must set the RS4= 85 + * mode to disable tristate prior to using the port. + * + * Some Exar UARTs have an auto-tristate feature while others require sett= ing + * an MPIO to disable the tristate. + * + * Return: 0 on success, negative error code on failure + */ +static int _cti_set_tristate(struct exar8250 *priv, + unsigned int port_num, bool enable) +{ + int ret =3D 0; + + if (port_num >=3D priv->nr) + return -EINVAL; + + // Only Exar based cards use MPIO, return 0 otherwise + if (priv->pcidev->vendor !=3D PCI_VENDOR_ID_EXAR) + return 0; + + dev_dbg(priv->dev, "%s tristate for port %u\n", + str_enable_disable(enable), port_num); + + if (enable) + ret =3D exar_mpio_set_low(priv, port_num); + else + ret =3D exar_mpio_set_high(priv, port_num); + if (ret) + return ret; + + // Ensure MPIO is an output + ret =3D exar_mpio_config_output(priv, port_num); + + return ret; +} + +static int cti_tristate_disable(struct exar8250 *priv, unsigned int port_n= um) +{ + return _cti_set_tristate(priv, port_num, false); +} + +/** + * _cti_set_plx_int_enable() - Enable/Disable PCI interrupts + * @priv: Device's private structure + * @enable: Enable interrupts if true, disable if false + * + * Some older CTI cards require MPIO_0 to be set low to enable the PCI + * interupts from the UART to the PLX PCI->PCIe bridge. + * + * Return: 0 on success, negative error code on failure + */ +static int _cti_set_plx_int_enable(struct exar8250 *priv, bool enable) +{ + int ret =3D 0; + + // Only Exar based cards use MPIO, return 0 otherwise + if (priv->pcidev->vendor !=3D PCI_VENDOR_ID_EXAR) + return 0; + + if (enable) + ret =3D exar_mpio_set_low(priv, 0); + else + ret =3D exar_mpio_set_high(priv, 0); + if (ret) + return ret; + + // Ensure MPIO is an output + ret =3D exar_mpio_config_output(priv, 0); + + return ret; +} + +static int cti_plx_int_enable(struct exar8250 *priv) +{ + return _cti_set_plx_int_enable(priv, true); +} + +/** + * cti_read_osc_freq() - Read the UART oscillator frequency from EEPROM + * @priv: Device's private structure + * @eeprom_offset: Offset where the oscillator frequency is stored + * + * CTI XR17x15X and XR17V25X cards have the serial boards oscillator frequ= ency + * stored in the EEPROM. FPGA and XR17V35X based cards use the PCI/PCIe cl= ock. + * + * Return: frequency on success, negative error code on failure + */ +static int cti_read_osc_freq(struct exar8250 *priv, u8 eeprom_offset) +{ + u16 lower_word; + u16 upper_word; + int osc_freq; + + lower_word =3D exar_ee_read(priv, eeprom_offset); + // Check if EEPROM word was blank + if (lower_word =3D=3D 0xFFFF) + return -EIO; + + upper_word =3D exar_ee_read(priv, (eeprom_offset + 1)); + if (upper_word =3D=3D 0xFFFF) + return -EIO; + + osc_freq =3D FIELD_PREP(CTI_EE_MASK_OSC_FREQ_LOWER, lower_word) | + FIELD_PREP(CTI_EE_MASK_OSC_FREQ_UPPER, upper_word); + + dev_dbg(priv->dev, "osc_freq from EEPROM %d\n", osc_freq); + + return osc_freq; +} + +/** + * cti_get_port_type_xr17c15x_xr17v25x() - Get port type of xr17c15x/xr17v= 25x + * @priv: Device's private structure + * @port_num: Port to get type of + * + * CTI xr17c15x and xr17v25x based cards port types are based on PCI IDs. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_xr17c15x_xr17v25x(struct exar8= 250 *priv, + unsigned int port_num) +{ + enum cti_port_type port_type; + + switch (priv->pcidev->subsystem_device) { + // RS232 only cards + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_232_NS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_232_NS: + port_type =3D CTI_PORT_TYPE_RS232; + break; + // 1x RS232, 1x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1: + port_type =3D (port_num =3D=3D 0) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // 2x RS232, 2x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2: + port_type =3D (port_num < 2) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // 4x RS232, 4x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + port_type =3D (port_num < 4) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // RS232/RS422/RS485 HW (jumper) selectable + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_SP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_SP_OPTO_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + port_type =3D CTI_PORT_TYPE_RS232_422_485_HW; + break; + // RS422/RS485 HW (jumper) selectable + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port_type =3D CTI_PORT_TYPE_RS422_485; + break; + // 6x RS232, 2x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + port_type =3D (port_num < 6) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + // 2x RS232, 6x RS422/RS485 + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + port_type =3D (port_num < 2) ? + CTI_PORT_TYPE_RS232 : CTI_PORT_TYPE_RS422_485; + break; + default: + dev_err(priv->dev, "unknown/unsupported device\n"); + port_type =3D CTI_PORT_TYPE_NONE; + } + + return port_type; +} + +/** + * cti_get_port_type_fpga() - Get the port type of a CTI FPGA card + * @priv: Device's private structure + * @port_num: Port to get type of + * + * FPGA based cards port types are based on PCI IDs. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_fpga(struct exar8250 *priv, + unsigned int port_num) +{ + enum cti_port_type port_type; + + switch (priv->pcidev->device) { + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG00X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_12_XIG01X: + case PCI_DEVICE_ID_CONNECT_TECH_PCI_XR79X_16: + port_type =3D CTI_PORT_TYPE_RS232_422_485_HW; + break; + default: + dev_err(priv->dev, "unknown/unsupported device\n"); + return CTI_PORT_TYPE_NONE; + } + + return port_type; +} + +/** + * cti_get_port_type_xr17v35x() - Read port type from the EEPROM + * @priv: Device's private structure + * @port_num: port offset + * + * CTI XR17V35X based cards have the port types stored in the EEPROM. + * This function reads the port type for a single port. + * + * Return: port type on success, CTI_PORT_TYPE_NONE on failure + */ +static enum cti_port_type cti_get_port_type_xr17v35x(struct exar8250 *priv, + unsigned int port_num) +{ + enum cti_port_type port_type; + u16 port_flags; + u8 offset; + + offset =3D CTI_EE_OFF_XR17V35X_PORT_FLAGS + port_num; + port_flags =3D exar_ee_read(priv, offset); + + port_type =3D FIELD_GET(CTI_EE_MASK_PORT_FLAGS_TYPE, port_flags); + if (!CTI_PORT_TYPE_VALID(port_type)) { + /* + * If the port type is missing the card assume it is a + * RS232/RS422/RS485 card to be safe. + * + * There is one known board (BEG013) that only has + * 3 of 4 port types written to the EEPROM so this + * acts as a work around. + */ + dev_warn(priv->dev, + "failed to get port %d type from EEPROM\n", port_num); + port_type =3D CTI_PORT_TYPE_RS232_422_485_HW; + } + + return port_type; +} + +static int cti_rs485_config_mpio_tristate(struct uart_port *port, + struct ktermios *termios, + struct serial_rs485 *rs485) +{ + struct exar8250 *priv =3D (struct exar8250 *)port->private_data; + int ret; + + ret =3D generic_rs485_config(port, termios, rs485); + if (ret) + return ret; + + // Disable power-on RS485 tri-state via MPIO + return cti_tristate_disable(priv, port->port_id); +} + +static int cti_port_setup_common(struct exar8250 *priv, + int idx, unsigned int offset, + struct uart_8250_port *port) +{ + int ret; + + if (priv->osc_freq =3D=3D 0) + return -EINVAL; + + port->port.port_id =3D idx; + port->port.uartclk =3D priv->osc_freq; + + ret =3D serial8250_pci_setup_port(priv->pcidev, port, 0, offset, 0); + if (ret) { + dev_err(priv->dev, + "failed to setup pci for port %d err: %d\n", idx, ret); + return ret; + } + + port->port.private_data =3D (void *)priv; + port->port.pm =3D exar_pm; + port->port.shutdown =3D exar_shutdown; + + return 0; +} + +static int cti_port_setup_fpga(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + + port_type =3D cti_get_port_type_fpga(priv, idx); + + // FPGA shares port offests with XR17C15X + offset =3D idx * UART_EXAR_XR17C15X_PORT_OFFSET; + port->port.type =3D PORT_XR17D15X; + + port->port.get_divisor =3D xr17v35x_get_divisor; + port->port.set_divisor =3D xr17v35x_set_divisor; + port->port.startup =3D xr17v35x_startup; + + if (CTI_PORT_TYPE_RS485(port_type)) { + port->port.rs485_config =3D generic_rs485_config; + port->port.rs485_supported =3D generic_rs485_supported; + } + + return cti_port_setup_common(priv, idx, offset, port); +} + +static int cti_port_setup_xr17v35x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + int ret; + + port_type =3D cti_get_port_type_xr17v35x(priv, idx); + + offset =3D idx * UART_EXAR_XR17V35X_PORT_OFFSET; + port->port.type =3D PORT_XR17V35X; + + port->port.get_divisor =3D xr17v35x_get_divisor; + port->port.set_divisor =3D xr17v35x_set_divisor; + port->port.startup =3D xr17v35x_startup; + + switch (port_type) { + case CTI_PORT_TYPE_RS422_485: + case CTI_PORT_TYPE_RS232_422_485_HW: + port->port.rs485_config =3D cti_rs485_config_mpio_tristate; + port->port.rs485_supported =3D generic_rs485_supported; + break; + case CTI_PORT_TYPE_RS232_422_485_SW: + case CTI_PORT_TYPE_RS232_422_485_4B: + case CTI_PORT_TYPE_RS232_422_485_2B: + port->port.rs485_config =3D generic_rs485_config; + port->port.rs485_supported =3D generic_rs485_supported; + break; + default: + break; + } + + ret =3D cti_port_setup_common(priv, idx, offset, port); + if (ret) + return ret; + + exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00); + exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD); + exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 128); + exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 128); + + return 0; +} + +static int cti_port_setup_xr17v25x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + int ret; + + port_type =3D cti_get_port_type_xr17c15x_xr17v25x(priv, idx); + + offset =3D idx * UART_EXAR_XR17V25X_PORT_OFFSET; + port->port.type =3D PORT_XR17D15X; + + // XR17V25X supports fractional baudrates + port->port.get_divisor =3D xr17v35x_get_divisor; + port->port.set_divisor =3D xr17v35x_set_divisor; + port->port.startup =3D xr17v35x_startup; + + if (CTI_PORT_TYPE_RS485(port_type)) { + switch (priv->pcidev->subsystem_device) { + // These cards support power on 485 tri-state via MPIO + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port->port.rs485_config =3D cti_rs485_config_mpio_tristate; + break; + // Otherwise auto or no power on 485 tri-state support + default: + port->port.rs485_config =3D generic_rs485_config; + break; + } + + port->port.rs485_supported =3D generic_rs485_supported; + } + + ret =3D cti_port_setup_common(priv, idx, offset, port); + if (ret) + return ret; + + exar_write_reg(priv, (offset + UART_EXAR_8XMODE), 0x00); + exar_write_reg(priv, (offset + UART_EXAR_FCTR), UART_FCTR_EXAR_TRGD); + exar_write_reg(priv, (offset + UART_EXAR_TXTRG), 32); + exar_write_reg(priv, (offset + UART_EXAR_RXTRG), 32); + + return 0; +} + +static int cti_port_setup_xr17c15x(struct exar8250 *priv, + struct pci_dev *pcidev, + struct uart_8250_port *port, + int idx) +{ + enum cti_port_type port_type; + unsigned int offset; + + port_type =3D cti_get_port_type_xr17c15x_xr17v25x(priv, idx); + + offset =3D idx * UART_EXAR_XR17C15X_PORT_OFFSET; + port->port.type =3D PORT_XR17D15X; + + if (CTI_PORT_TYPE_RS485(port_type)) { + switch (priv->pcidev->subsystem_device) { + // These cards support power on 485 tri-state via MPIO + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_SP_485: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_6_2_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_6_SP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_LEFT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XP_OPTO_RIGHT: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XP_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS_LP_485: + port->port.rs485_config =3D cti_rs485_config_mpio_tristate; + break; + // Otherwise auto or no power on 485 tri-state support + default: + port->port.rs485_config =3D generic_rs485_config; + break; + } + + port->port.rs485_supported =3D generic_rs485_supported; + } + + return cti_port_setup_common(priv, idx, offset, port); +} + +static int cti_board_init_xr17v35x(struct exar8250 *priv) +{ + // XR17V35X uses the PCIe clock rather than an oscillator + priv->osc_freq =3D CTI_DEFAULT_PCIE_OSC_FREQ; + + return 0; +} + +static int cti_board_init_xr17v25x(struct exar8250 *priv) +{ + int osc_freq; + + osc_freq =3D cti_read_osc_freq(priv, CTI_EE_OFF_XR17V25X_OSC_FREQ); + if (osc_freq < 0) { + dev_warn(priv->dev, + "failed to read osc freq from EEPROM, using default\n"); + osc_freq =3D CTI_DEFAULT_PCI_OSC_FREQ; + } + + priv->osc_freq =3D osc_freq; + + /* enable interupts on cards that need the "PLX fix" */ + switch (priv->pcidev->subsystem_device) { + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B: + cti_plx_int_enable(priv); + break; + default: + break; + } + + return 0; +} + +static int cti_board_init_xr17c15x(struct exar8250 *priv) +{ + int osc_freq; + + osc_freq =3D cti_read_osc_freq(priv, CTI_EE_OFF_XR17C15X_OSC_FREQ); + if (osc_freq <=3D 0) { + dev_warn(priv->dev, + "failed to read osc freq from EEPROM, using default\n"); + osc_freq =3D CTI_DEFAULT_PCI_OSC_FREQ; + } + + priv->osc_freq =3D osc_freq; + + /* enable interrupts on cards that need the "PLX fix" */ + switch (priv->pcidev->subsystem_device) { + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A: + case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B: + cti_plx_int_enable(priv); + break; + default: + break; + } + + return 0; +} + +static int cti_board_init_fpga(struct exar8250 *priv) +{ + int ret; + u16 cfg_val; + + // FPGA OSC is fixed to the 33MHz PCI clock + priv->osc_freq =3D CTI_DEFAULT_FPGA_OSC_FREQ; + + // Enable external interrupts in special cfg space register + ret =3D pci_read_config_word(priv->pcidev, + CTI_FPGA_CFG_INT_EN_REG, &cfg_val); + if (ret) + return ret; + + cfg_val |=3D CTI_FPGA_CFG_INT_EN_EXT_BIT; + ret =3D pci_write_config_word(priv->pcidev, + CTI_FPGA_CFG_INT_EN_REG, cfg_val); + if (ret) + return ret; + + // RS485 gate needs to be enabled; otherwise RTS/CTS will not work + exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01); + + return 0; +} + static int pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, struct uart_8250_port *port, int idx) @@ -767,6 +1607,8 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pc= i_device_id *ent) return -ENOMEM; priv->board =3D board; + priv->pcidev =3D pcidev; + priv->dev =3D &pcidev->dev; priv->virt =3D pcim_iomap(pcidev, bar, 0); if (!priv->virt) return -ENOMEM; @@ -879,6 +1721,26 @@ static const struct exar8250_board pbn_fastcom335_8 = =3D { .setup =3D pci_fastcom335_setup, }; +static const struct exar8250_board pbn_cti_xr17c15x =3D { + .board_init =3D cti_board_init_xr17c15x, + .setup =3D cti_port_setup_xr17c15x, +}; + +static const struct exar8250_board pbn_cti_xr17v25x =3D { + .board_init =3D cti_board_init_xr17v25x, + .setup =3D cti_port_setup_xr17v25x, +}; + +static const struct exar8250_board pbn_cti_xr17v35x =3D { + .board_init =3D cti_board_init_xr17v35x, + .setup =3D cti_port_setup_xr17v35x, +}; + +static const struct exar8250_board pbn_cti_fpga =3D { + .board_init =3D cti_board_init_fpga, + .setup =3D cti_port_setup_fpga, +}; + static const struct exar8250_board pbn_exar_ibm_saturn =3D { .num_ports =3D 1, .setup =3D pci_xr17c154_setup, @@ -923,6 +1785,27 @@ static const struct exar8250_board pbn_exar_XR17V8358= =3D { .exit =3D pci_xr17v35x_exit, }; +// For Connect Tech cards with Exar vendor/device PCI IDs +#define CTI_EXAR_DEVICE(devid, bd) { \ + PCI_DEVICE_SUB( \ + PCI_VENDOR_ID_EXAR, \ + PCI_DEVICE_ID_EXAR_##devid, \ + PCI_SUBVENDOR_ID_CONNECT_TECH, \ + PCI_ANY_ID), 0, 0, \ + (kernel_ulong_t)&bd \ + } + +// For Connect Tech cards with Connect Tech vendor/device PCI IDs (FPGA ba= sed) +#define CTI_PCI_DEVICE(devid, bd) { \ + PCI_DEVICE_SUB( \ + PCI_VENDOR_ID_CONNECT_TECH, \ + PCI_DEVICE_ID_CONNECT_TECH_PCI_##devid, \ + PCI_ANY_ID, \ + PCI_ANY_ID), 0, 0, \ + (kernel_ulong_t)&bd \ + } + + #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } #define IBM_DEVICE(devid, sdevid, bd) { \ @@ -952,6 +1835,22 @@ static const struct pci_device_id exar_pci_tbl[] =3D { EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), + CTI_EXAR_DEVICE(XR17C152, pbn_cti_xr17c15x), + CTI_EXAR_DEVICE(XR17C154, pbn_cti_xr17c15x), + CTI_EXAR_DEVICE(XR17C158, pbn_cti_xr17c15x), + + CTI_EXAR_DEVICE(XR17V252, pbn_cti_xr17v25x), + CTI_EXAR_DEVICE(XR17V254, pbn_cti_xr17v25x), + CTI_EXAR_DEVICE(XR17V258, pbn_cti_xr17v25x), + + CTI_EXAR_DEVICE(XR17V352, pbn_cti_xr17v35x), + CTI_EXAR_DEVICE(XR17V354, pbn_cti_xr17v35x), + CTI_EXAR_DEVICE(XR17V358, pbn_cti_xr17v35x), + + CTI_PCI_DEVICE(XR79X_12_XIG00X, pbn_cti_fpga), + CTI_PCI_DEVICE(XR79X_12_XIG01X, pbn_cti_fpga), + CTI_PCI_DEVICE(XR79X_16, pbn_cti_fpga), + IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), /* USRobotics USR298x-OEM PCI Modems */ -- 2.43.2 From nobody Wed Feb 11 03:51:31 2026 Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B301E12C7FA; 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Tue, 16 Apr 2024 14:56:38 +0200 From: Parker Newman To: Greg Kroah-Hartman , Jiri Slaby , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Parker Newman Subject: [PATCH v3 8/8] serial: exar: fix: fix crash during shutdown if setup fails Date: Tue, 16 Apr 2024 08:55:35 -0400 Message-ID: <1a21fffe403d7181e0404db1ed92140c306f97b7.1713270624.git.pnewman@connecttech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:Aix2Gfbz3WAlz2Z+lR82+NyyweP0ySGfxPJud5y3h/eaUD+TfCK tNX9oGSruoLdOu9OVjQ9Uo+0rMlWuAnj6QsQuf3NDwyJeJenh9G0YNuqjDrvxGC9To3Prd5 jnZUmHyyBgT1l7zjRXaSm1ujrg3CmsH+J0VneP9UY/0irnodH4Aa//OhmPjPqbOQZeA8qvd qvFGMX5q3L8Sz2gc/pDIg== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:R9jOjENT1WY=;ejdCrwwafJxLraDIM3YWdGe5Gf8 TGgftdLfb0YEcoJYUk0MjEIP5PuK3s748EFwOTKaLY+Pq67vKwXlBwwF6Qr2vRrcq7L3SIdyI ysVumb/Co+kA88d4EnuG+4x/6O0tWghnHZXILOYGY+grItIiuXDDBue+YGPsojqQe/vQFCu5j AnM5ofSPS1mRszGgXFvhgtEyU56eKQwL/kQPAumflvQARki2PgJ4EtskR9xbqSQuv0Lv64oH1 4BHQXvS8+9kES+adbpXhgmg8qJx0KNTUNBRlc2QE3qzfSZqa67dmyl9sG1+75pkPjusK5YWqO dbNGBATZ2m8olWBCF3w/91oDCqfQZ5sASj4VQ+iFfbEMhI9UE5bX+ve05LagaY3wxSKdQD57K 85LMfFDKXgdBsYuNP3iCqh0/eKX7k8Ut8ntFm/p+/9WiPYFFbN41dn+hjOFfmhhCK+KAaBpLC EnvcA5GERyQum/2sHmHkh2gkjT+K4S7xvi9KNWBmRztfGF4+MFs929LvBWT/MZ1c29emR83Ao RZSvao8gY2jnbrYQvmBdmHxzFDr0qHlmjqS9mOZTXXjDpb1+S+bUJdhSFTpIzFsWz0Ak0iQdR Csqskd5/909oaQ3kbEe042qJU62/boQ1w7xDTaMMdUARd0u1l2ktaUbvJtXIjCHJLGpYZC/4Q OV4ZW0lBaNndXjHuKj0L55EB0NoyqPeg+rN9YX4gufMj9w9ko44hKulEjeQX/xzkmNgQVOt0V eiF47/CMa5tfT5XvMX9PeNVTtTPxP1P+frurlBoSXwIT7gPCDQTyvg= Content-Type: text/plain; charset="utf-8" From: Parker Newman If a port fails to register with serial8250_register_8250_port() the kernel can crash when shutting down or module removal. This is because "priv->line[i]" will be set to a negative error code and in the exar_pci_remove() function serial8250_unregister_port() is called without checking if the "priv->line[i]" value is valid. Signed-off-by: Parker Newman --- drivers/tty/serial/8250/8250_exar.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/= 8250_exar.c index 501b9f3e9c89..f5a395ed69d1 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -1671,7 +1671,8 @@ static void exar_pci_remove(struct pci_dev *pcidev) unsigned int i; for (i =3D 0; i < priv->nr; i++) - serial8250_unregister_port(priv->line[i]); + if (priv->line[i] >=3D 0) + serial8250_unregister_port(priv->line[i]); /* Ensure that every init quirk is properly torn down */ if (priv->board->exit) -- 2.43.2