From nobody Mon Feb 9 04:30:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F96D2BAE7 for ; Sun, 7 Apr 2024 12:45:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493918; cv=none; b=Yzw6CCr5RbXtuwNQEWcA1GU/SKkBT+GZEMty30iQx5L1Zfe4HR3V4TRN5HItUY42wfUmKN284aI8LL1mCk5w7xFjv4mr5D0Z7a+foFXD5Xi0hftx7KSdgdsLN1GTb2lUmbpixD1x3lhwRoPgZtf4Szj7ltyqpMxj/R8W89BxSD4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493918; c=relaxed/simple; bh=ZkR1EiJggDNyuzKlUoPpjBGIiqt0tELn3Ew37L5rYo8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lFuMBWEjecvJv8krpbceXaCdhyxpr19CaUBimN8M/BQi6+tH2m9J1YkIMD3n0erSOyT0tyy3QWnZwcGgfNPS/UI1s322jZLOZ4U0S0wNdDtpBjcxt0nHrZ8icoNSZ3dyUFz71olujaabZDuaOkLgV98nsx/fn3vHGB6Awdo2/Rs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=etDGvSEY; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="etDGvSEY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712493917; x=1744029917; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZkR1EiJggDNyuzKlUoPpjBGIiqt0tELn3Ew37L5rYo8=; b=etDGvSEY1DK4MTbqnRoom5fC5dF6dQRs0rpP1oEc38ra5fcYBi3FPgjm H6I55r6c7gZqIXzF5PB/AtFcWd4RX0KvoEz4UX3khNAY9E9VDc3Z2sTnX /iPFmy7seBhpR8rXHmzGSjLkpDtM5NGG0YxPQ0fYKiCXkn0vxqmgOLSrZ Gle+GSSUoaUQK2IXj3+s/2vkCWXfR7RoOI/UACyZWzVxn4he5L6Ok5iXY KFnVtQMQloPy+oYE5VoCaTsu5lWnG5kmqypJsarNTmzOvHxYRw9d4uXrk B8AueEXw38NIpJ6yhpYPwwyF5NBNsZ8ca3k+OSX0aFCEXtLXseds969E4 Q==; X-CSE-ConnectionGUID: nyIgkqk5RBKDrv8U8555kg== X-CSE-MsgGUID: H5DHvaSZSACOuKfdylu0ZQ== X-IronPort-AV: E=McAfee;i="6600,9927,11036"; a="11564050" X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="11564050" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:17 -0700 X-CSE-ConnectionGUID: RwtkdjYzQo2uNlUaD9AIuw== X-CSE-MsgGUID: xQXHZH8kQg6htPdnXZPDqw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="20185642" Received: from mirtanji-mobl.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.251.14.88]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:13 -0700 From: Kai Huang To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, dave.hansen@intel.com, bp@alien8.de, kirill.shutemov@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, luto@kernel.org, peterz@infradead.org, rick.p.edgecombe@intel.com, thomas.lendacky@amd.com, ashish.kalra@amd.com, chao.gao@intel.com, bhe@redhat.com, nik.borisov@suse.com, pbonzini@redhat.com, seanjc@google.com Subject: [PATCH v3 1/5] x86/kexec: do unconditional WBINVD for bare-metal in stop_this_cpu() Date: Mon, 8 Apr 2024 00:44:54 +1200 Message-ID: <33b985a8f4346f4bcf0944eaf37193a906b11af3.1712493366.git.kai.huang@intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TL;DR: Change to do unconditional WBINVD in stop_this_cpu() for bare metal to cover kexec support for both AMD SME and Intel TDX, despite there _was_ some issue preventing from doing so but now has it got fixed. Long version: Both SME and TDX can leave caches in incoherent state due to memory encryption. During kexec, the caches must be flushed before jumping to the second kernel to avoid silent memory corruption to the second kernel. Currently, for SME the kernel only does WBINVD in stop_this_cpu() when the kernel determines the hardware supports SME. To support TDX, one option is to extend that specific check to cover both SME and TDX. However, instead of sprinkling around vendor-specific checks, it's better to just do unconditional WBINVD. Kexec() is a slow path, and it is acceptable to have an additional WBINVD in order to have simple and easy to maintain code. But only do WBINVD for bare-metal because TDX guests and SEV-ES/SEV-SNP guests will get unexpected (and yet unnecessary) #VE and may not be able to handle (e.g., TDX guest panics when it gets #VE due to WBINVD). Note: Historically, there _was_ an issue preventing doing unconditional WBINVD but that has been fixed. When SME kexec() support was initially added in commit bba4ed011a52: ("x86/mm, kexec: Allow kexec to be used with SME") WBINVD was done unconditionally. However since then some issues were reported that different Intel systems would hang or reset due to that commit. To try to fix, a later commit f23d74f6c66c: ("x86/mm: Rework wbinvd, hlt operation in stop_this_cpu()") then changed to only do WBINVD when hardware supports SME. While this commit made the reported issues go away, it didn't pinpoint the root cause. Also, it didn't handle a corner case[*] correctly, which resulted in the reveal of the root cause and the final fix by commit 1f5e7eb7868e: ("x86/smp: Make stop_other_cpus() more robust") See [1][2] for more information. Further testing of doing unconditional WBINVD based on the above fix on the problematic machines (that issues were originally reported) confirmed the issues couldn't be reproduced. See [3][4] for more information. Therefore, it is safe to do unconditional WBINVD now. [*] The commit didn't check whether the CPUID leaf is available or not. Making unsupported CPUID leaf on Intel returns garbage resulting in unintended WBINVD which caused some issue (followed by the analysis and the reveal of the final root cause). The corner case was independently fixed by commit 9b040453d444: ("x86/smp: Dont access non-existing CPUID leaf") [1]: https://lore.kernel.org/lkml/CALu+AoQKmeixJdkO07t7BtttN7v3RM4_aBKi642b= Q3fTBbSAVg@mail.gmail.com/T/#m300f3f9790850b5daa20a71abcc200ae8d94a12a [2]: https://lore.kernel.org/lkml/CALu+AoQKmeixJdkO07t7BtttN7v3RM4_aBKi642b= Q3fTBbSAVg@mail.gmail.com/T/#ma7263a7765483db0dabdeef62a1110940e634846 [3]: https://lore.kernel.org/lkml/CALu+AoQKmeixJdkO07t7BtttN7v3RM4_aBKi642b= Q3fTBbSAVg@mail.gmail.com/T/#mc043191f2ff860d649c8466775dc61ac1e0ae320 [4]: https://lore.kernel.org/lkml/CALu+AoQKmeixJdkO07t7BtttN7v3RM4_aBKi642b= Q3fTBbSAVg@mail.gmail.com/T/#md23f1a8f6afcc59fa2b0ac1967f18e418e24347c Signed-off-by: Kai Huang Suggested-by: Borislav Petkov Cc: Tom Lendacky Cc: Dave Young --- v2 -> v3: - Change to only do WBINVD for bare metal --- arch/x86/kernel/process.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index b8441147eb5e..5ba8a9c1e47a 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -813,18 +813,16 @@ void __noreturn stop_this_cpu(void *dummy) mcheck_cpu_clear(c); =20 /* - * Use wbinvd on processors that support SME. This provides support - * for performing a successful kexec when going from SME inactive - * to SME active (or vice-versa). The cache must be cleared so that - * if there are entries with the same physical address, both with and - * without the encryption bit, they don't race each other when flushed - * and potentially end up with the wrong entry being committed to - * memory. + * The kernel could leave caches in incoherent state on SME/TDX + * capable platforms. Flush cache to avoid silent memory + * corruption for these platforms. * - * Test the CPUID bit directly because the machine might've cleared - * X86_FEATURE_SME due to cmdline options. + * stop_this_cpu() is not a fast path, just do unconditional + * WBINVD for simplicity. But only do WBINVD for bare-metal + * as TDX guests and SEV-ES/SEV-SNP guests will get unexpected + * (and unnecessary) #VE and may unable to handle. */ - if (c->extended_cpuid_level >=3D 0x8000001f && (cpuid_eax(0x8000001f) & B= IT(0))) + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) native_wbinvd(); =20 /* --=20 2.43.2 From nobody Mon Feb 9 04:30:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E892C6BA for ; Sun, 7 Apr 2024 12:45:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493922; cv=none; b=dpBFW9hk2la2E/V45NPHkM9PZrS3P9NJM9ivOitOYcXjQyBT0/Pxr+prJPNixYIZYBcremzoIuEOszBK43fUXwsPMH7nkSLpXhWQWwRzonwOtK5ojKSR8V78bJ4flOmvV9Ookx1suaI6BS4zuRvLwIrE3jQVZNGamojzGS6EuWA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493922; c=relaxed/simple; bh=V9JifYapbpBofohz95Yw5R+vy9sccP6hFMfQiefdsIE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=np6zm6AiN3Ee2Ug80qzPqoZQ1AV+sf3Hjmo7LJQgfVshL24OGCXvArj2S3xfRk+gmjKS67+FI4vRp4GkF//G+vdXkkyZQS3iluK0v3zKU5Bsca8Djis6men6jqdnrB/Tdgp8yDmOeIsrBEM927AgAqKHjMsRSEXUjqwn+IzoOu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=eJNZJcQc; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="eJNZJcQc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712493922; x=1744029922; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V9JifYapbpBofohz95Yw5R+vy9sccP6hFMfQiefdsIE=; b=eJNZJcQcsXJcjTAhGbDFaBBZOl+CMnU8GGh7NWSfhsledhhCACaX03xE ivXtC3yzor85LsKRngTaA/XSpxagrFPs0Iu0pDnrAerY3I6f7ElD8GpXr hz70sCmFm9UCVtC1qMc6zTlji/oFcupzh09XbKHqeAv8Rr0LzFvglfTDi lMVpYpGqJhdEE6EcTZoChFBus1ag/UHwUdBjgY9RXthhZb74TCp6S2sFC AJrBa/SWpv7hj7SYebdIn8lHOU5wJpTzCOR9kxiHCVO3Z63n9Wx3deu7/ Ot1vBvZdsWLSmcyLP7DJVmZEO9e8xUOYpMpSDVBs6DlTVnVWjO4fvWBm1 g==; X-CSE-ConnectionGUID: dT4N7HDSS2uah2jQS3N9Jg== X-CSE-MsgGUID: hKAdgr+TTHqsaFDoebCx6w== X-IronPort-AV: E=McAfee;i="6600,9927,11036"; a="11564064" X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="11564064" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:21 -0700 X-CSE-ConnectionGUID: fQ/sMBkhS0a4+bxYj3wcTQ== X-CSE-MsgGUID: 3QdrJ/49SVK9QBfWe/t+Bg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="20185677" Received: from mirtanji-mobl.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.251.14.88]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:17 -0700 From: Kai Huang To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, dave.hansen@intel.com, bp@alien8.de, kirill.shutemov@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, luto@kernel.org, peterz@infradead.org, rick.p.edgecombe@intel.com, thomas.lendacky@amd.com, ashish.kalra@amd.com, chao.gao@intel.com, bhe@redhat.com, nik.borisov@suse.com, pbonzini@redhat.com, seanjc@google.com Subject: [PATCH v3 2/5] x86/kexec: do unconditional WBINVD for bare-metal in relocate_kernel() Date: Mon, 8 Apr 2024 00:44:55 +1200 Message-ID: <5aca124fe0ca1c97bf4a2e925b3905485bf5b255.1712493366.git.kai.huang@intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both SME and TDX can leave caches in incoherent state due to memory encryption. During kexec, the caches must be flushed before jumping to the second kernel to avoid silent memory corruption to the second kernel. During kexec, the WBINVD in stop_this_cpu() flushes caches for all remote cpus when they are being stopped. For SME, the WBINVD in relocate_kernel() flushes the cache for the last running cpu (which is executing the kexec). Similarly, to support kexec for TDX host, after stopping all remote cpus with cache flushed, the kernel needs to flush cache for the last running cpu. Use the existing WBINVD in relocate_kernel() to cover TDX host as well. However, instead of sprinkling around vendor-specific checks, just do unconditional WBINVD to cover both SME and TDX. Kexec is not a fast path so having one additional WBINVD for platforms w/o SME/TDX is acceptable. But only do WBINVD for bare-metal because TDX guests and SEV-ES/SEV-SNP guests will get unexpected (and yet unnecessary) #VE which the kernel is unable to handle at this stage. Signed-off-by: Kai Huang Cc: Tom Lendacky Cc: Dave Young Reviewed-by: Kirill A. Shutemov --- v2 -> v3: - Change to only do WBINVD for bare metal --- arch/x86/include/asm/kexec.h | 2 +- arch/x86/kernel/machine_kexec_64.c | 2 +- arch/x86/kernel/relocate_kernel_64.S | 14 +++++++++----- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/kexec.h b/arch/x86/include/asm/kexec.h index 91ca9a9ee3a2..455f8a6c66a9 100644 --- a/arch/x86/include/asm/kexec.h +++ b/arch/x86/include/asm/kexec.h @@ -128,7 +128,7 @@ relocate_kernel(unsigned long indirection_page, unsigned long page_list, unsigned long start_address, unsigned int preserve_context, - unsigned int host_mem_enc_active); + unsigned int bare_metal); #endif =20 #define ARCH_HAS_KIMAGE_ARCH diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_k= exec_64.c index b180d8e497c3..a454477b7b4c 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c @@ -358,7 +358,7 @@ void machine_kexec(struct kimage *image) (unsigned long)page_list, image->start, image->preserve_context, - cc_platform_has(CC_ATTR_HOST_MEM_ENCRYPT)); + !boot_cpu_has(X86_FEATURE_HYPERVISOR)); =20 #ifdef CONFIG_KEXEC_JUMP if (image->preserve_context) diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocat= e_kernel_64.S index 56cab1bb25f5..3e04c5e5687f 100644 --- a/arch/x86/kernel/relocate_kernel_64.S +++ b/arch/x86/kernel/relocate_kernel_64.S @@ -50,7 +50,7 @@ SYM_CODE_START_NOALIGN(relocate_kernel) * %rsi page_list * %rdx start address * %rcx preserve_context - * %r8 host_mem_enc_active + * %r8 bare_metal */ =20 /* Save the CPU context, used for jumping back */ @@ -78,7 +78,7 @@ SYM_CODE_START_NOALIGN(relocate_kernel) pushq $0 popfq =20 - /* Save SME active flag */ + /* Save the bare_metal */ movq %r8, %r12 =20 /* @@ -160,9 +160,13 @@ SYM_CODE_START_LOCAL_NOALIGN(identity_mapped) movq %r9, %cr3 =20 /* - * If SME is active, there could be old encrypted cache line - * entries that will conflict with the now unencrypted memory - * used by kexec. Flush the caches before copying the kernel. + * The kernel could leave caches in incoherent state on SME/TDX + * capable platforms. Just do unconditional WBINVD to avoid + * silent memory corruption to the new kernel for these platforms. + * + * But only do WBINVD for bare-metal because TDX guests and + * SEV-ES/SEV-SNP guests will get #VE which the kernel is unable + * to handle at this stage. */ testq %r12, %r12 jz 1f --=20 2.43.2 From nobody Mon Feb 9 04:30:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4685032189 for ; Sun, 7 Apr 2024 12:45:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493927; cv=none; b=BNQdkxLhpdZzZaILHWY7T36Eo0dU0BemfrXwpwSDZWlMySi4h3Pd2AcE3o//OXq+wOgx8gCkVf4vESk0IYPxMgfg4UuUGtjnIYgGJcaebnPaLNmdVtKoY3zb/tnM9mHpoyYaPY8KnrulJiyYsmD5QlEGS289MF3KgaNwGVw5tgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493927; c=relaxed/simple; bh=/RooyKFiqcQ8glp+buJlhJQQS25CNQDe1WudukydwNY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j66UdVYhmBvpq15bwuiG3UzSWSrSBlQFgTPD95GEXY9L1eRusK/Gc1/qt2NXDIoFzdhtlMb3bhT78lOdixD+Fq9kju45xR+9QAE6noqjmQnMzpt09ucQ8/C/KF8doN1S+VJjFjoQfRJvbNQ+k4clMVKaR7mUcwfP/VerZMfC6cY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=SZoqUz86; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="SZoqUz86" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712493926; x=1744029926; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/RooyKFiqcQ8glp+buJlhJQQS25CNQDe1WudukydwNY=; b=SZoqUz86IWLPJjV0B2zZ+0j/2gmj8w7lsdssXcdU8CNFz2HMFJk6kidE u0Tlnxz/4Axgoj5eJFM8yCo6CpEMylqDTCHQkIoJeRGWKxIK/hsYFlOOZ QtLrR/WYwug7g+vXUjbjPqTIxtCTtTZ1Mxt9w8mDrb13hIAgB4x5Go/Oa 5ZI1h0tucfL4IONr2U/+nESVffJ1h6Jv8eBjcwuxoI5QrtSR6llme+QbB 1Cw+Xu7+SXu+oJsGhzcveT8aT7oxohOpIgLlX9V0t+abKAJkjouFcFq1G nL4jFLeq5DEf44uMPLeVdu+2GkgbN4K0NMCYUiUA+Mit/lcm5PkAtzSQe Q==; X-CSE-ConnectionGUID: cECu6C4pQgakAfOACgSiGw== X-CSE-MsgGUID: FwOXgykvStefRd5NKhPASg== X-IronPort-AV: E=McAfee;i="6600,9927,11036"; a="11564077" X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="11564077" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:25 -0700 X-CSE-ConnectionGUID: 5BMvLWqOTGaHcSEeX9mS7Q== X-CSE-MsgGUID: oDXH3/jSRD+1On8nVI6COA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="20185705" Received: from mirtanji-mobl.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.251.14.88]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:21 -0700 From: Kai Huang To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, dave.hansen@intel.com, bp@alien8.de, kirill.shutemov@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, luto@kernel.org, peterz@infradead.org, rick.p.edgecombe@intel.com, thomas.lendacky@amd.com, ashish.kalra@amd.com, chao.gao@intel.com, bhe@redhat.com, nik.borisov@suse.com, pbonzini@redhat.com, seanjc@google.com Subject: [PATCH v3 3/5] x86/kexec: Reset TDX private memory on platforms with TDX erratum Date: Mon, 8 Apr 2024 00:44:56 +1200 Message-ID: X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TL;DR: On the platforms with TDX "partial write machine check" erratum, during kexec, convert TDX private memory back to normal before jumping to the second kernel to avoid the second kernel seeing potential unexpected machine check. Long version: The first few generations of TDX hardware have an erratum. A partial write to a TDX private memory cacheline will silently "poison" the line. Subsequent reads will consume the poison and generate a machine check. According to the TDX hardware spec, neither of these things should have happened. =3D=3D Background =3D=3D Virtually all kernel memory accesses operations happen in full cachelines. In practice, writing a "byte" of memory usually reads a 64 byte cacheline of memory, modifies it, then writes the whole line back. Those operations do not trigger this problem. This problem is triggered by "partial" writes where a write transaction of less than cacheline lands at the memory controller. The CPU does these via non-temporal write instructions (like MOVNTI), or through UC/WC memory mappings. The issue can also be triggered away from the CPU by devices doing partial writes via DMA. =3D=3D Problem =3D=3D A fast warm reset doesn't reset TDX private memory. Kexec() can also boot into the new kernel directly. Thus if the old kernel has left any TDX private pages on the platform with this erratum, the new kernel might get unexpected machine check. Note that w/o this erratum any kernel read/write on TDX private memory should never cause machine check, thus it's OK for the old kernel to leave TDX private pages as is. =3D=3D Solution =3D=3D In short, with this erratum, the kernel needs to explicitly convert all TDX private pages back to normal to give the new kernel a clean slate after kexec(). The BIOS is also expected to disable fast warm reset as a workaround to this erratum, thus this implementation doesn't try to reset TDX private memory for the reboot case in the kernel but depends on the BIOS to enable the workaround. Convert TDX private pages back to normal (using MOVDIR64B to clear these pages) after all remote cpus have been stopped and cache flush has been done on all cpus, when no more TDX activity can happen further. Do it in machine_kexec() to cover both normal kexec, and crash kexec. For now TDX private memory can only be PAMT pages. It would be ideal to cover all types of TDX private memory here, but there are practical problems to do so: 1) There's no existing infrastructure to track TDX private pages; 2) It's not feasible to query the TDX module about page type, because VMX, which making SEAMCALL requires, has already been disabled; 3) Even if it is feasible to query the TDX module, the result may not be accurate. E.g., the remote CPU could be stopped right before MOVDIR64B. One temporary solution is to blindly convert all memory pages, but it's problematic to do so too, because not all pages are mapped as writable in the direct mapping. It can be done by switching to the identical mapping created for kexec(), or a new page table, but the complexity looks overkill. Therefore, rather than doing something dramatic, only reset PAMT pages here. Leave resetting other TDX private pages as a future work when they become possible to exist. Signed-off-by: Kai Huang Reviewed-by: Kirill A. Shutemov --- v2 -> v3: - No change v1 -> v2: - Remove using reboot notifier to stop TDX module as it doesn't cover crash kexec. Change to use a variable with barrier instead. (Rick) - Introduce kexec_save_processor_start() to make code better, and make the comment around calling site of tdx_reset_memory() more concise. (Dave) - Mention cache for all other cpus have been flushed around native_wbinvd() in tdx_reset_memory(). (Dave) - Remove the extended alternaties discussion from the comment, but leave it in the changelog. Point out what does current code do and point out risk. (Dave) --- arch/x86/include/asm/tdx.h | 2 + arch/x86/kernel/machine_kexec_64.c | 27 ++++++++-- arch/x86/virt/vmx/tdx/tdx.c | 79 ++++++++++++++++++++++++++++++ 3 files changed, 104 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index eba178996d84..ed3ac9a8a079 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -116,11 +116,13 @@ static inline u64 sc_retry(sc_func_t func, u64 fn, int tdx_cpu_enable(void); int tdx_enable(void); const char *tdx_dump_mce_info(struct mce *m); +void tdx_reset_memory(void); #else static inline void tdx_init(void) { } static inline int tdx_cpu_enable(void) { return -ENODEV; } static inline int tdx_enable(void) { return -ENODEV; } static inline const char *tdx_dump_mce_info(struct mce *m) { return NULL; } +static inline void tdx_reset_memory(void) { } #endif /* CONFIG_INTEL_TDX_HOST */ =20 #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_k= exec_64.c index a454477b7b4c..ba5a66bf724e 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c @@ -28,6 +28,7 @@ #include #include #include +#include =20 #ifdef CONFIG_ACPI /* @@ -288,6 +289,14 @@ void machine_kexec_cleanup(struct kimage *image) free_transition_pgtable(image); } =20 +static void kexec_save_processor_start(struct kimage *image) +{ +#ifdef CONFIG_KEXEC_JUMP + if (image->preserve_context) + save_processor_state(); +#endif +} + /* * Do not allocate memory (or fail in any way) in machine_kexec(). * We are past the point of no return, committed to rebooting now. @@ -298,10 +307,20 @@ void machine_kexec(struct kimage *image) void *control_page; int save_ftrace_enabled; =20 -#ifdef CONFIG_KEXEC_JUMP - if (image->preserve_context) - save_processor_state(); -#endif + kexec_save_processor_start(image); + + /* + * Convert TDX private memory back to normal (when needed) to + * avoid the second kernel potentially seeing unexpected machine + * check. + * + * However skip this when preserve_context is on. By reaching + * here, TDX (if ever got enabled by the kernel) has survived + * from the suspend when preserve_context is on, and it can + * continue to work after jumping back from the second kernel. + */ + if (!image->preserve_context) + tdx_reset_memory(); =20 save_ftrace_enabled =3D __ftrace_enabled_save(); =20 diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 49a1c6890b55..7f5d388c5461 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -52,6 +52,8 @@ static DEFINE_MUTEX(tdx_module_lock); /* All TDX-usable memory regions. Protected by mem_hotplug_lock. */ static LIST_HEAD(tdx_memlist); =20 +static bool tdx_may_have_private_memory __read_mostly; + typedef void (*sc_err_func_t)(u64 fn, u64 err, struct tdx_module_args *arg= s); =20 static inline void seamcall_err(u64 fn, u64 err, struct tdx_module_args *a= rgs) @@ -1096,6 +1098,18 @@ static int init_tdmrs(struct tdmr_info_list *tdmr_li= st) return 0; } =20 +static void mark_may_have_private_memory(bool may) +{ + tdx_may_have_private_memory =3D may; + + /* + * Ensure update to tdx_may_have_private_memory is visible to all + * cpus. This ensures when any remote cpu reads it as true, the + * 'tdx_tdmr_list' must be stable for reading PAMTs. + */ + smp_wmb(); +} + static int init_tdx_module(void) { struct tdx_tdmr_sysinfo tdmr_sysinfo; @@ -1141,6 +1155,12 @@ static int init_tdx_module(void) if (ret) goto err_reset_pamts; =20 + /* + * Starting from this point the system is possible to have + * TDX private memory. + */ + mark_may_have_private_memory(true); + /* Initialize TDMRs to complete the TDX module initialization */ ret =3D init_tdmrs(&tdx_tdmr_list); if (ret) @@ -1172,6 +1192,7 @@ static int init_tdx_module(void) * as suggested by the TDX spec. */ tdmrs_reset_pamt_all(&tdx_tdmr_list); + mark_may_have_private_memory(false); err_free_pamts: tdmrs_free_pamt_all(&tdx_tdmr_list); err_free_tdmrs: @@ -1489,3 +1510,61 @@ void __init tdx_init(void) =20 check_tdx_erratum(); } + +void tdx_reset_memory(void) +{ + if (!boot_cpu_has(X86_FEATURE_TDX_HOST_PLATFORM)) + return; + + /* + * Converting TDX private pages back to normal must be done + * when there's no TDX activity anymore on all remote cpus. + * Verify this is only called when all remote cpus have + * been stopped. + */ + WARN_ON_ONCE(num_online_cpus() !=3D 1); + + /* + * Kernel read/write to TDX private memory doesn't cause + * machine check on hardware w/o this erratum. + */ + if (!boot_cpu_has_bug(X86_BUG_TDX_PW_MCE)) + return; + + /* + * Nothing to convert if it's not possible to have any TDX + * private pages. + */ + if (!tdx_may_have_private_memory) + return; + + /* + * Ensure the 'tdx_tdmr_list' is stable for reading PAMTs + * when tdx_may_have_private_memory reads true, paired with + * the smp_wmb() in mark_may_have_private_memory(). + */ + smp_rmb(); + + /* + * All remote cpus have been stopped, and their caches have + * been flushed in stop_this_cpu(). Now flush cache for the + * last running cpu _before_ converting TDX private pages. + */ + native_wbinvd(); + + /* + * It's ideal to cover all types of TDX private pages here, but + * currently there's no unified way to tell whether a given page + * is TDX private page or not. + * + * Just convert PAMT pages now, as currently TDX private pages + * can only be PAMT pages. + * + * TODO: + * + * This leaves all other types of TDX private pages undealt + * with. They must be handled in _some_ way when they become + * possible to exist. + */ + tdmrs_reset_pamt_all(&tdx_tdmr_list); +} --=20 2.43.2 From nobody Mon Feb 9 04:30:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3489F3612C for ; Sun, 7 Apr 2024 12:45:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493930; cv=none; b=ILNvSQuuie6Gckfc1xQ37n/VOB9FVJHcTLB35QGQpIKQ1lNomrGqTrbPDE+0BIFWMChOMetIDRa/Q60J7lIpVXM1RFLm6HSECmkcR1+eDbaCav3fJLDoKPsdYurHa6ndk537CNcS/cWijuySVW2fY5JFWp6nWjtgyjGLR4Pxh0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493930; c=relaxed/simple; bh=6CCxFfD9nmysEbLLqArr5MWTcAJT2JYjKEhYrHzQWT4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SNJIsle1LUbRoaBkA2B6tki+z+HfJwpj00b4+fdvtyd6kqbpqTlFJeLQnLf3j6kgEmGwndHrpgXZlz+Df5gCDgo5pLF1fcyfjGisRMQRvF3nU+vhOi/5i2IrJ1xePxETI3UNWkt/B54PYRnmHctHBNPfMDGEXUmw8mv1H8qXaOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YpZsYycC; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YpZsYycC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712493930; x=1744029930; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6CCxFfD9nmysEbLLqArr5MWTcAJT2JYjKEhYrHzQWT4=; b=YpZsYycCMs4FvJeHmeR3Mw9e+0BQ2NxoL9xiq5j4bAenC74ykDJNk3MU IiHgvZDdWPzDzv6euVk+uark2eznf7KloNsxq3DLKxoCb5X8U8mW8Qw53 LkL+styKwB3s77ANmbIx9TCDLteOx4cymC/eXLU0ooPL282tve+MdPU9z 3WMjI4nX/G00qqR+ItWAx9oCX4kuNc105pY5fpcg4xaT2xQwT45Cw9EeS XrzTKdHIMUlN/KK3uqsgc8Os8PnkfmVUEzkQI6pQVcN+bihIluMI8XSJO vrDUnVX4mKBGD2sZsgC0K1hCJT3zqwdO5fRhZ42gJx9zhzmkdFxOZ1W02 g==; X-CSE-ConnectionGUID: lIp8CeN5TyyocVHup49Jlw== X-CSE-MsgGUID: D1A/ghMQTlS3W2M8Wfrdow== X-IronPort-AV: E=McAfee;i="6600,9927,11036"; a="11564092" X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="11564092" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:29 -0700 X-CSE-ConnectionGUID: Hfoa1JAtRr2OaQ87X0HmXw== X-CSE-MsgGUID: s6rhqW3xQK2nHSH7TBt2bQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="20185730" Received: from mirtanji-mobl.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.251.14.88]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:25 -0700 From: Kai Huang To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, dave.hansen@intel.com, bp@alien8.de, kirill.shutemov@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, luto@kernel.org, peterz@infradead.org, rick.p.edgecombe@intel.com, thomas.lendacky@amd.com, ashish.kalra@amd.com, chao.gao@intel.com, bhe@redhat.com, nik.borisov@suse.com, pbonzini@redhat.com, seanjc@google.com Subject: [PATCH v3 4/5] x86/virt/tdx: Remove the !KEXEC_CORE dependency Date: Mon, 8 Apr 2024 00:44:57 +1200 Message-ID: <2fc6e5c300d863ba72eac8739c50507cbbfa1712.1712493366.git.kai.huang@intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now TDX host can work with kexec(). Remove the !KEXEC_CORE dependency. Signed-off-by: Kai Huang --- arch/x86/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index c62db6b853d7..bfafc8a16a07 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1967,7 +1967,6 @@ config INTEL_TDX_HOST depends on X86_X2APIC select ARCH_KEEP_MEMBLOCK depends on CONTIG_ALLOC - depends on !KEXEC_CORE depends on X86_MCE help Intel Trust Domain Extensions (TDX) protects guest VMs from malicious --=20 2.43.2 From nobody Mon Feb 9 04:30:06 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 302753309E for ; Sun, 7 Apr 2024 12:45:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493934; cv=none; b=gU1BlXOfUSHEo/uNdoSV4qhI3VD5CWrGAWMtj7QHCwx3reTzauAArizDld8TdKm2OwNNXVevA7cVd2Q+jOABzTT69URhz/mtEqYYpqUwT5GI3VFVkTjrPSZYIqDTq0vVrsNSIW1SxNI40YdBn/2md0g/TcqOT3ULoJwfNDbHAxU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712493934; c=relaxed/simple; bh=w5AQltEjcfuaA8t+xAbaDYXarkRZWOmtHIHnBJWtT88=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QHr0qwR1OgtZalAwWZVPezPrnS5KWBbEl5595C5oRkRc2Bl8wPOwm/LYilsyj2ndAKJLwiNDs/bsaUQYQh6bKB3MBPRicq406b9DHUjSWrfrPaAv728+XqxsxM38o6zzqCAkRb3fkuhRY+gl/73t2Uj6X+pcoiYH/sH/+aHT67s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JUgiEU3R; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JUgiEU3R" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712493934; x=1744029934; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w5AQltEjcfuaA8t+xAbaDYXarkRZWOmtHIHnBJWtT88=; b=JUgiEU3RkQXSxPx/c7OXEdn/MiEYFLjNdeAz7Qjxp+Q7cP2cu/vPuTFT CuQf4sRJe5CtIhxkGImQJ/0zmQMTyDX1aKTajTQOV9PuiSMJUt3JHwmXy RbKjfPcMeLw6y06Lq70SWIdOXcFPZeT2KtRBMkt/tZmK4qviAXFgyjHks heJWqnhrSXMMrSjFxTBk/Nfft6YsS1wdsJkbTdiJeuGgejY/x6d+Rxysl G4sF0KuRXOSID1rZJdufLhrbzv+UGsx428jUbSj9L/d//dPlBAmvfm9GA OsjO4BKr5yX9vVoOgA6jdWrqHKw5Utg6KbNJhn1OPbXr4MeGOcJ9bhPPE w==; X-CSE-ConnectionGUID: RJI2J3nrRy6dcDLlHZi7RQ== X-CSE-MsgGUID: 9Mxs4Do4Q5mFfczj6KzG1A== X-IronPort-AV: E=McAfee;i="6600,9927,11036"; a="11564103" X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="11564103" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:33 -0700 X-CSE-ConnectionGUID: 7757OkZGT3ijl1UFYtuNcg== X-CSE-MsgGUID: z0HSBt8LTxOfUIzCWypoBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,185,1708416000"; d="scan'208";a="20185744" Received: from mirtanji-mobl.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.251.14.88]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2024 05:45:29 -0700 From: Kai Huang To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, dave.hansen@intel.com, bp@alien8.de, kirill.shutemov@linux.intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, luto@kernel.org, peterz@infradead.org, rick.p.edgecombe@intel.com, thomas.lendacky@amd.com, ashish.kalra@amd.com, chao.gao@intel.com, bhe@redhat.com, nik.borisov@suse.com, pbonzini@redhat.com, seanjc@google.com Subject: [PATCH v3 5/5] x86/virt/tdx: Add TDX memory reset notifier to reset other private pages Date: Mon, 8 Apr 2024 00:44:58 +1200 Message-ID: <94a9d89487356547b67e2e5c08edae3bd2e68490.1712493366.git.kai.huang@intel.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TL;DR: To cover both normal kexec and crash kexec, add a TDX specific memory reset notifier to let "in-kernel TDX users" use their own way to convert TDX private pages (that they manage respectively) in tdx_reset_memory(). Long version: On the platforms with TDX "partial write machine check" erratum, during kexec, the kernel needs to convert TDX private memory back to normal before jumping to the second kernel to avoid the second kernel seeing potential machine check. For now tdx_reset_memory() only resets PAMT pages. KVM will be the first in-kernel TDX user to support running TDX guests, and by then other TDX private pages will start to exist. They need to be covered too. Currently the kernel doesn't have a unified way to tell whether a given page is TDX private page or not. One choice is to add such unified way, and there are couple of options to do it: 1) Use a bitmap, or Xarray, etc to track TDX private page for all PFNs; 2) Use a "software-only" bit in the direct-mapping PTE to mark a given page is TDX private page; 3) Use a new flag in 'struct page' to mark TDX private page; 4) ... potential other ways. Option 1) consumes additional memory. E.g., if using bitmap, the overhead is "number of total RAM pages / 8" bytes. Option 2) would cause splitting large-page mapping to 4K mapping in the direct mapping when one page is allocated as TDX private page, and cause additional TLB flush etc. It's not ideal for such use case. Option 3) apparently contradicts to the effort to reduce the use of the flags of 'struct page'. None of above is ideal. Therefore, instead of providing a unified way to tell whether a given page is TDX private page or not, leave "resetting TDX private pages" to the "in-kernel user" of TDX. This is motivated by the fact that KVM is already maintaining an Xarray to track "memory attributes (e.g., private or shared)" for each GFN for each guest. Thus KVM can use its own way to find all TDX private pages that it manages and convert them back to normal. For the normal kexec the reboot notifier could be used, but it doesn't cover the cash kexec. Add a TDX specific memory reset notifier to achieve this. The in-kernel TDX users will need to register their own notifiers to reset TDX private pages. Call these notifiers in tdx_reset_memory() right before resetting PAMT pages. KVM will be the first user of this notifier. Export the "register" and "unregister" APIs for KVM to use. Signed-off-by: Kai Huang --- arch/x86/include/asm/tdx.h | 14 ++++++++++++ arch/x86/virt/vmx/tdx/tdx.c | 45 +++++++++++++++++++++++++++---------- 2 files changed, 47 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index ed3ac9a8a079..7c2c0a0b9754 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -117,12 +117,26 @@ int tdx_cpu_enable(void); int tdx_enable(void); const char *tdx_dump_mce_info(struct mce *m); void tdx_reset_memory(void); + +struct notifier_block; + +int tdx_register_memory_reset_notifier(struct notifier_block *nb); +void tdx_unregister_memory_reset_notifier(struct notifier_block *nb); #else static inline void tdx_init(void) { } static inline int tdx_cpu_enable(void) { return -ENODEV; } static inline int tdx_enable(void) { return -ENODEV; } static inline const char *tdx_dump_mce_info(struct mce *m) { return NULL; } static inline void tdx_reset_memory(void) { } + +struct notifier_block; + +static inline int tdx_register_memory_reset_notifier(struct notifier_block= *nb) +{ + return -EOPNOTSUPP; +} +static inline void tdx_unregister_memory_reset_notifier( + struct notifier_block *nb) { } #endif /* CONFIG_INTEL_TDX_HOST */ =20 #endif /* !__ASSEMBLY__ */ diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 7f5d388c5461..af62fbffcd96 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,8 @@ static LIST_HEAD(tdx_memlist); =20 static bool tdx_may_have_private_memory __read_mostly; =20 +static BLOCKING_NOTIFIER_HEAD(tdx_memory_reset_chain); + typedef void (*sc_err_func_t)(u64 fn, u64 err, struct tdx_module_args *arg= s); =20 static inline void seamcall_err(u64 fn, u64 err, struct tdx_module_args *a= rgs) @@ -1511,6 +1514,27 @@ void __init tdx_init(void) check_tdx_erratum(); } =20 +int tdx_register_memory_reset_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&tdx_memory_reset_chain, nb); +} +EXPORT_SYMBOL_GPL(tdx_register_memory_reset_notifier); + +void tdx_unregister_memory_reset_notifier(struct notifier_block *nb) +{ + blocking_notifier_chain_unregister(&tdx_memory_reset_chain, nb); +} +EXPORT_SYMBOL_GPL(tdx_unregister_memory_reset_notifier); + +static int notify_reset_memory(void) +{ + int ret; + + ret =3D blocking_notifier_call_chain(&tdx_memory_reset_chain, 0, NULL); + + return notifier_to_errno(ret); +} + void tdx_reset_memory(void) { if (!boot_cpu_has(X86_FEATURE_TDX_HOST_PLATFORM)) @@ -1553,18 +1577,15 @@ void tdx_reset_memory(void) native_wbinvd(); =20 /* - * It's ideal to cover all types of TDX private pages here, but - * currently there's no unified way to tell whether a given page - * is TDX private page or not. - * - * Just convert PAMT pages now, as currently TDX private pages - * can only be PAMT pages. - * - * TODO: - * - * This leaves all other types of TDX private pages undealt - * with. They must be handled in _some_ way when they become - * possible to exist. + * Tell all in-kernel TDX users to reset TDX private pages + * that they manage. + */ + if (notify_reset_memory()) + pr_err("Failed to reset all TDX private pages.\n"); + + /* + * The only remaining TDX private pages are PAMT pages. + * Reset them. */ tdmrs_reset_pamt_all(&tdx_tdmr_list); } --=20 2.43.2