From nobody Fri May 17 04:59:58 2024 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2060.outbound.protection.outlook.com [40.107.93.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D41E364C1; Tue, 13 Feb 2024 11:15:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822958; cv=fail; b=OQHlH2lVExueGY9Q+QVk0fcvuLajc4QX4+qUYHh10F60YFz/jOxv9CCVhidyQTJh9zBpbEDMhnIhePYkMKJ0FTJOyS1HYhy0Y0ze7cf2Ry0lywZpcOKavH4/I2TfS6PuAIM802qL/AaS20raYIFhJMULaTT/XNY49rpkGeq69zc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822958; c=relaxed/simple; bh=OdBgv6GEJgWqm9PHWWDA1ZSXtRp4iwHLdZs+JwuMsnQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b12juSm6fFpFFmR0l9uprCbUuVJVoKsN/vdnmbfqSmvcQMiPmjTlT4IBY2r0jzDTkJOxqE01fxzjtEOq1WVertqaXFvcevu6RcwNhOheblcwysbKKW5bq42ZkB43XlOnbIsEGJ3nOm/EQnmR4ZoH76WATBxxK8Y6f48nqKA4s+A= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=WXO2Oxc/; arc=fail smtp.client-ip=40.107.93.60 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="WXO2Oxc/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dfIftdIxavzV9kSYniccolUp7Y72/qnZm3huw+xQi1t5qpp53TZwSzKPQFbIUGyPFj3pkUvvTHfCKT8rxBrF72m0gW/5S5aDsiJpuNYbgWCp014l+4Dwff4/4DuhWP9BsJ+6GVKSFGi/rOqGDm8bPW6gDBcMT29yXLbUw3zfWHuhbyFjnt+FFVj5Th3E1xepQb6K2psbj/Bvce2NMYOwLqPjpRUy3EHVAcsWAOIDLNixgsHNbLe1/+iYA0PeBLxpemRadUvawiTjpFEVXxwXx6XKFMckE3sCCEqA84QlqIeRb2xgH4A6AbDy16SRPEcviv2y4Ruh7Si8g/ObXqyKqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=fUz2Y/hF4PQixena8vBYg9SMbkpNO+TEcdDXW+HuIrM=; b=Ty8dpoxUWKwzGiDUbCC1T+2Vt3UokibxccOk+GeA4/DU+OSFxKNnjimmamSG9Ch3GL5yAVF9CBrpVqMwT21JvKH3HtfVtjxPauNVGFcFBh4dVk8Oc4gheaNjEHRAhbpHaMeNBL1nf1aKm8V7Z5u7zFy8RgGMA3GCyPx04+/++aF8Ds8bmsYDLn5SpWpvnsyjzGE+h8OTGZX2fptgLfkh+av5xu7Ru4mNrNKAYm5zJiJXblEZ48PKfDWpLC7vrA6cVwaA6plS9zzt09XmMBS0LleGMLJUQnZv74LKpyYMvf50nNs043dzNwxaQE7weclQM2q+L9ah9sbbHNW6etRCAw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=fUz2Y/hF4PQixena8vBYg9SMbkpNO+TEcdDXW+HuIrM=; b=WXO2Oxc/zbIiICwNvNGQXOR8Ll5ticohWeX3eg/eIkBkB/g1YdPPPuA+9pkgoXRfj3wTaVcLNwl7xQss9yQ/g/2ZT6QnOu2lv5zXO54hq0sSLcczTeMOjilnqbWxF74AjaM6hQo8/x3yojGqZh7V+2d5JoGHAcHnz0xchHJ/AVHIvRnnpWoZtc2FTh34SfAUDsQvjqUgnoASl2ZBE9B3j7DcAPxnOuSY3zfzvrh6CF/19WnaUez4Bo8Z4oQc1zl+peeQCmXXBb1BDMeFK/spomUzbEcBn2hKOStpj1wBw0Fz2WOVm9x3sPzUxs+W4UvpNnSJqIAE0jVp8Z+joz6QCQ== Received: from CH2PR16CA0026.namprd16.prod.outlook.com (2603:10b6:610:50::36) by MN2PR12MB4566.namprd12.prod.outlook.com (2603:10b6:208:26a::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25; Tue, 13 Feb 2024 11:15:51 +0000 Received: from CH2PEPF0000009A.namprd02.prod.outlook.com (2603:10b6:610:50:cafe::36) by CH2PR16CA0026.outlook.office365.com (2603:10b6:610:50::36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.38 via Frontend Transport; Tue, 13 Feb 2024 11:15:51 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 13 Feb 2024 11:15:50 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb 2024 03:15:38 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Feb 2024 03:15:37 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 13 Feb 2024 03:15:37 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v3 1/4] platform/mellanox: mlxbf-pmc: Replace uintN_t with kernel-style types Date: Tue, 13 Feb 2024 06:15:25 -0500 Message-ID: <39be055af3506ce6f843d11e45d71620f2a96e26.1707808180.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|MN2PR12MB4566:EE_ X-MS-Office365-Filtering-Correlation-Id: a035e7c8-e6f2-49aa-0d57-08dc2c85230a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z58thS8Fg9CN38sB5OPqULjC9kxJ+r5LyErjEXrwurScq8P9w6PsV0TJ/dprYNj+g8B1O7z+19omzjfAWDeI529IcFxPNmkVdnF5zgX1wySytYvejpNqfQf8r0nNqtrLeWhpbPxfgg8SU3gXn6oKl1xf3qS0H2DTJDHZ8Pn9NGj+4syCV9LFqyp6FgdWKr+7V1zOZ8My5MtvMEUEYiQ8VqQT9ffFUGBFGRKWITKl+TxrijGfaY5GgUHUKKWuaE/FNReaOcq9IGkGaSH68VMAmuPjspOYyhkc5ifjffjq+qJY5CO1oo9mn+hDOaKSxUIEYjhUR964QIUsVZTcSskpcuBdQtIxDbORg3p1NhCkcfA0G1byiE1e7G8UZ4QkgEh71yMLtlQxdkJORztqxW3zDLIfm3ozgcHQGGbG+ApTRsvnOMwSJQuYBNS3vvCHr1lYcY8F9Xr1hlq9i5BOOOdlqY+pjrJcHL5MZs6B9TN5PFDc8GILxLXqvF7gTIJBQF5K2CmHNQFql0nkhThv439z6W2ZFbSmKj6Sn8jXx6Ngb9+a9ZC55gFpLYWbyKg741a/HJTkntFy7uIzjTxh5bOVaEl7ilCQwDxgBl9H9OZ61hU= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(39860400002)(136003)(396003)(230922051799003)(186009)(82310400011)(451199024)(64100799003)(1800799012)(36840700001)(40470700004)(46966006)(83380400001)(356005)(7636003)(86362001)(478600001)(316002)(54906003)(6636002)(70206006)(426003)(70586007)(110136005)(82740400003)(2616005)(336012)(7696005)(6666004)(26005)(36756003)(4326008)(8676002)(30864003)(8936002)(41300700001)(5660300002)(2906002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2024 11:15:50.8339 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a035e7c8-e6f2-49aa-0d57-08dc2c85230a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4566 Content-Type: text/plain; charset="utf-8" Use u8, u32 and u64 instead of respective uintN_t types. Remove unnecessary newlines for function argument lists. Signed-off-by: Shravan Kumar Ramani --- drivers/platform/mellanox/mlxbf-pmc.c | 109 +++++++++++--------------- 1 file changed, 47 insertions(+), 62 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mella= nox/mlxbf-pmc.c index b1995ac268d7..86044d1b8fa5 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -149,17 +149,17 @@ struct mlxbf_pmc_block_info { */ struct mlxbf_pmc_context { struct platform_device *pdev; - uint32_t total_blocks; - uint32_t tile_count; - uint8_t llt_enable; - uint8_t mss_enable; - uint32_t group_num; + u32 total_blocks; + u32 tile_count; + u8 llt_enable; + u8 mss_enable; + u32 group_num; struct device *hwmon_dev; const char *block_name[MLXBF_PMC_MAX_BLOCKS]; struct mlxbf_pmc_block_info block[MLXBF_PMC_MAX_BLOCKS]; const struct attribute_group *groups[MLXBF_PMC_MAX_BLOCKS]; bool svc_sreg_support; - uint32_t sreg_tbl_perf; + u32 sreg_tbl_perf; unsigned int event_set; }; =20 @@ -865,8 +865,7 @@ static struct mlxbf_pmc_context *pmc; static const char *mlxbf_pmc_svc_uuid_str =3D "89c036b4-e7d7-11e6-8797-001= aca00bfc4"; =20 /* Calls an SMC to access a performance register */ -static int mlxbf_pmc_secure_read(void __iomem *addr, uint32_t command, - uint64_t *result) +static int mlxbf_pmc_secure_read(void __iomem *addr, u32 command, u64 *res= ult) { struct arm_smccc_res res; int status, err =3D 0; @@ -892,8 +891,7 @@ static int mlxbf_pmc_secure_read(void __iomem *addr, ui= nt32_t command, } =20 /* Read from a performance counter */ -static int mlxbf_pmc_read(void __iomem *addr, uint32_t command, - uint64_t *result) +static int mlxbf_pmc_read(void __iomem *addr, u32 command, u64 *result) { if (pmc->svc_sreg_support) return mlxbf_pmc_secure_read(addr, command, result); @@ -907,22 +905,21 @@ static int mlxbf_pmc_read(void __iomem *addr, uint32_= t command, } =20 /* Convenience function for 32-bit reads */ -static int mlxbf_pmc_readl(void __iomem *addr, uint32_t *result) +static int mlxbf_pmc_readl(void __iomem *addr, u32 *result) { - uint64_t read_out; + u64 read_out; int status; =20 status =3D mlxbf_pmc_read(addr, MLXBF_PMC_READ_REG_32, &read_out); if (status) return status; - *result =3D (uint32_t)read_out; + *result =3D (u32)read_out; =20 return 0; } =20 /* Calls an SMC to access a performance register */ -static int mlxbf_pmc_secure_write(void __iomem *addr, uint32_t command, - uint64_t value) +static int mlxbf_pmc_secure_write(void __iomem *addr, u32 command, u64 val= ue) { struct arm_smccc_res res; int status, err =3D 0; @@ -945,7 +942,7 @@ static int mlxbf_pmc_secure_write(void __iomem *addr, u= int32_t command, } =20 /* Write to a performance counter */ -static int mlxbf_pmc_write(void __iomem *addr, int command, uint64_t value) +static int mlxbf_pmc_write(void __iomem *addr, int command, u64 value) { if (pmc->svc_sreg_support) return mlxbf_pmc_secure_write(addr, command, value); @@ -959,7 +956,7 @@ static int mlxbf_pmc_write(void __iomem *addr, int comm= and, uint64_t value) } =20 /* Check if the register offset is within the mapped region for the block = */ -static bool mlxbf_pmc_valid_range(int blk_num, uint32_t offset) +static bool mlxbf_pmc_valid_range(int blk_num, u32 offset) { if ((offset >=3D 0) && !(offset % MLXBF_PMC_REG_SIZE) && (offset + MLXBF_PMC_REG_SIZE <=3D pmc->block[blk_num].blk_size)) @@ -1082,7 +1079,7 @@ static char *mlxbf_pmc_get_event_name(const char *blk= , int evt) /* Method to enable/disable/reset l3cache counters */ static int mlxbf_pmc_config_l3_counters(int blk_num, bool enable, bool res= et) { - uint32_t perfcnt_cfg =3D 0; + u32 perfcnt_cfg =3D 0; =20 if (enable) perfcnt_cfg |=3D MLXBF_PMC_L3C_PERF_CNT_CFG_EN; @@ -1095,12 +1092,9 @@ static int mlxbf_pmc_config_l3_counters(int blk_num,= bool enable, bool reset) } =20 /* Method to handle l3cache counter programming */ -static int mlxbf_pmc_program_l3_counter(int blk_num, uint32_t cnt_num, - uint32_t evt) +static int mlxbf_pmc_program_l3_counter(int blk_num, u32 cnt_num, u32 evt) { - uint32_t perfcnt_sel_1 =3D 0; - uint32_t perfcnt_sel =3D 0; - uint32_t *wordaddr; + u32 perfcnt_sel_1 =3D 0, perfcnt_sel =3D 0, *wordaddr; void __iomem *pmcaddr; int ret; =20 @@ -1162,11 +1156,10 @@ static int mlxbf_pmc_program_l3_counter(int blk_num= , uint32_t cnt_num, } =20 /* Method to handle crspace counter programming */ -static int mlxbf_pmc_program_crspace_counter(int blk_num, uint32_t cnt_num, - uint32_t evt) +static int mlxbf_pmc_program_crspace_counter(int blk_num, u32 cnt_num, u32= evt) { - uint32_t word; void *addr; + u32 word; int ret; =20 addr =3D pmc->block[blk_num].mmio_base + @@ -1187,7 +1180,7 @@ static int mlxbf_pmc_program_crspace_counter(int blk_= num, uint32_t cnt_num, } =20 /* Method to clear crspace counter value */ -static int mlxbf_pmc_clear_crspace_counter(int blk_num, uint32_t cnt_num) +static int mlxbf_pmc_clear_crspace_counter(int blk_num, u32 cnt_num) { void *addr; =20 @@ -1199,10 +1192,9 @@ static int mlxbf_pmc_clear_crspace_counter(int blk_n= um, uint32_t cnt_num) } =20 /* Method to program a counter to monitor an event */ -static int mlxbf_pmc_program_counter(int blk_num, uint32_t cnt_num, - uint32_t evt, bool is_l3) +static int mlxbf_pmc_program_counter(int blk_num, u32 cnt_num, u32 evt, bo= ol is_l3) { - uint64_t perfctl, perfevt, perfmon_cfg; + u64 perfctl, perfevt, perfmon_cfg; =20 if (cnt_num >=3D pmc->block[blk_num].counters) return -ENODEV; @@ -1263,12 +1255,11 @@ static int mlxbf_pmc_program_counter(int blk_num, u= int32_t cnt_num, } =20 /* Method to handle l3 counter reads */ -static int mlxbf_pmc_read_l3_counter(int blk_num, uint32_t cnt_num, - uint64_t *result) +static int mlxbf_pmc_read_l3_counter(int blk_num, u32 cnt_num, u64 *result) { - uint32_t perfcnt_low =3D 0, perfcnt_high =3D 0; - uint64_t value; + u32 perfcnt_low =3D 0, perfcnt_high =3D 0; int status; + u64 value; =20 status =3D mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + MLXBF_PMC_L3C_PERF_CNT_LOW + @@ -1295,11 +1286,10 @@ static int mlxbf_pmc_read_l3_counter(int blk_num, u= int32_t cnt_num, } =20 /* Method to handle crspace counter reads */ -static int mlxbf_pmc_read_crspace_counter(int blk_num, uint32_t cnt_num, - uint64_t *result) +static int mlxbf_pmc_read_crspace_counter(int blk_num, u32 cnt_num, u64 *r= esult) { - uint32_t value; int status =3D 0; + u32 value; =20 status =3D mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + MLXBF_PMC_CRSPACE_PERFMON_VAL0(pmc->block[blk_num].counters) + @@ -1313,11 +1303,10 @@ static int mlxbf_pmc_read_crspace_counter(int blk_n= um, uint32_t cnt_num, } =20 /* Method to read the counter value */ -static int mlxbf_pmc_read_counter(int blk_num, uint32_t cnt_num, bool is_l= 3, - uint64_t *result) +static int mlxbf_pmc_read_counter(int blk_num, u32 cnt_num, bool is_l3, u6= 4 *result) { - uint32_t perfcfg_offset, perfval_offset; - uint64_t perfmon_cfg; + u32 perfcfg_offset, perfval_offset; + u64 perfmon_cfg; int status; =20 if (cnt_num >=3D pmc->block[blk_num].counters) @@ -1351,13 +1340,11 @@ static int mlxbf_pmc_read_counter(int blk_num, uint= 32_t cnt_num, bool is_l3, } =20 /* Method to read L3 block event */ -static int mlxbf_pmc_read_l3_event(int blk_num, uint32_t cnt_num, - uint64_t *result) +static int mlxbf_pmc_read_l3_event(int blk_num, u32 cnt_num, u64 *result) { - uint32_t perfcnt_sel =3D 0, perfcnt_sel_1 =3D 0; - uint32_t *wordaddr; + u32 perfcnt_sel =3D 0, perfcnt_sel_1 =3D 0, *wordaddr; void __iomem *pmcaddr; - uint64_t evt; + u64 evt; =20 /* Select appropriate register information */ switch (cnt_num) { @@ -1405,10 +1392,9 @@ static int mlxbf_pmc_read_l3_event(int blk_num, uint= 32_t cnt_num, } =20 /* Method to read crspace block event */ -static int mlxbf_pmc_read_crspace_event(int blk_num, uint32_t cnt_num, - uint64_t *result) +static int mlxbf_pmc_read_crspace_event(int blk_num, u32 cnt_num, u64 *res= ult) { - uint32_t word, evt; + u32 word, evt; void *addr; int ret; =20 @@ -1429,11 +1415,10 @@ static int mlxbf_pmc_read_crspace_event(int blk_num= , uint32_t cnt_num, } =20 /* Method to find the event currently being monitored by a counter */ -static int mlxbf_pmc_read_event(int blk_num, uint32_t cnt_num, bool is_l3, - uint64_t *result) +static int mlxbf_pmc_read_event(int blk_num, u32 cnt_num, bool is_l3, u64 = *result) { - uint32_t perfcfg_offset, perfval_offset; - uint64_t perfmon_cfg, perfevt; + u32 perfcfg_offset, perfval_offset; + u64 perfmon_cfg, perfevt; =20 if (cnt_num >=3D pmc->block[blk_num].counters) return -EINVAL; @@ -1469,9 +1454,9 @@ static int mlxbf_pmc_read_event(int blk_num, uint32_t= cnt_num, bool is_l3, } =20 /* Method to read a register */ -static int mlxbf_pmc_read_reg(int blk_num, uint32_t offset, uint64_t *resu= lt) +static int mlxbf_pmc_read_reg(int blk_num, u32 offset, u64 *result) { - uint32_t ecc_out; + u32 ecc_out; =20 if (strstr(pmc->block_name[blk_num], "ecc")) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, @@ -1490,7 +1475,7 @@ static int mlxbf_pmc_read_reg(int blk_num, uint32_t o= ffset, uint64_t *result) } =20 /* Method to write to a register */ -static int mlxbf_pmc_write_reg(int blk_num, uint32_t offset, uint64_t data) +static int mlxbf_pmc_write_reg(int blk_num, u32 offset, u64 data) { if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, @@ -1512,7 +1497,7 @@ static ssize_t mlxbf_pmc_counter_show(struct device *= dev, attr, struct mlxbf_pmc_attribute, dev_attr); int blk_num, cnt_num, offset; bool is_l3 =3D false; - uint64_t value; + u64 value; =20 blk_num =3D attr_counter->nr; cnt_num =3D attr_counter->index; @@ -1546,7 +1531,7 @@ static ssize_t mlxbf_pmc_counter_store(struct device = *dev, attr, struct mlxbf_pmc_attribute, dev_attr); int blk_num, cnt_num, offset, err, data; bool is_l3 =3D false; - uint64_t evt_num; + u64 evt_num; =20 blk_num =3D attr_counter->nr; cnt_num =3D attr_counter->index; @@ -1597,7 +1582,7 @@ static ssize_t mlxbf_pmc_event_show(struct device *de= v, attr, struct mlxbf_pmc_attribute, dev_attr); int blk_num, cnt_num, err; bool is_l3 =3D false; - uint64_t evt_num; + u64 evt_num; char *evt_name; =20 blk_num =3D attr_event->nr; @@ -1686,7 +1671,7 @@ static ssize_t mlxbf_pmc_enable_show(struct device *d= ev, { struct mlxbf_pmc_attribute *attr_enable =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - uint32_t perfcnt_cfg, word; + u32 perfcnt_cfg, word; int blk_num, value; =20 blk_num =3D attr_enable->nr; @@ -1718,7 +1703,7 @@ static ssize_t mlxbf_pmc_enable_store(struct device *= dev, struct mlxbf_pmc_attribute *attr_enable =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); int err, en, blk_num; - uint32_t word; + u32 word; =20 blk_num =3D attr_enable->nr; =20 @@ -1914,7 +1899,7 @@ static bool mlxbf_pmc_guid_match(const guid_t *guid, /* Helper to map the Performance Counters from the varios blocks */ static int mlxbf_pmc_map_counters(struct device *dev) { - uint64_t info[MLXBF_PMC_INFO_SZ]; + u64 info[MLXBF_PMC_INFO_SZ]; int i, tile_num, ret; =20 for (i =3D 0; i < pmc->total_blocks; ++i) { --=20 2.30.1 From nobody Fri May 17 04:59:58 2024 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2088.outbound.protection.outlook.com [40.107.94.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 556DF364CF; Tue, 13 Feb 2024 11:15:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.88 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822958; cv=fail; b=jf7SGVRGP/AEpARNaFL7bfF5EamkjbxDJsOerWpPtUqfHDGu5r4Rw2aqs5rsnKrFdyLo+wTUH4n9pTrYa5822DjtjLp6cpkQihwpkuMeXt06OuAzHgIhcr94KT3u/K04TdxyTppUvn8rcvT4vqzHz4ERZ7XZ5G4PYAWcMMVp97I= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822958; c=relaxed/simple; bh=0E55QXLIpVd7RqZjbSbxvFTrxGnL+uF5Yylm5YW7asw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CNlJKC+5NDHvjf+2bFm4qmjmsELV7Wm2B8fEVhvfNGr1JyG01ZwgBMmZ/OQR5OfTL68xozNqrIlBy9vmtXz8wedthR2HU0ch5Irow6EXrCCnbEUWFv+84Tvc39x28KZDgTtMHkO7xo9rwmNFO/fXRf+xBqbBkfcrqYqttlUnkvM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=BB1787cE; arc=fail smtp.client-ip=40.107.94.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="BB1787cE" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VF57vxDdjUG4NvxNtku4TkFovYV7KMmmzYj3F6k7r6harc4zbyVwHflFRyZWHYlXBXbNtiVoGuikg4GbhAHDW9Pvmf4zQ3YjSUi1HopscsfIsBg5IQNKXqNvn1eNlLOdhfEiE9P//m3CbzCRSjcA3spibdgkri46Fe5HqAo2BqdKj3vj2F0OZwg/O7OmsPFBIu6CVJKNk4qgb2Xyd/jiP4S5JcEJzBa4DpSIQMvc1leshx1JKs6S6IY3/b6YPKmyqb/vC86827U6SrJWv6teHky3Ic3/mLdZ0GC6U44sTCH5z9zE2mrCcRRj9l0TDYBm/aHDdpVSGZP2/85cDalIEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=l4smij/kG6dq+0f9+u75XypkXVO1jpI1hr1hKqV7GcU=; b=c3uXoZJ3z8c3tn4C8Udoy8HvK2Vt9PJLFxeo4laZd3yiqxqbscjNGZFxcN+5gz9hlxhhHJ+Ws9uvYZSijUDmcwnt39Q67/5roiTJGMNq4Zi3SoM0OIRZw33ejnFo2oyN0chcwzATOOMGKoTCf5tEebVaKhcDYs/Wc60Rsm9FPp7+cXz9OYPvPneJ+LMx0UPEYHpzebTYB9m/b3CQoicpWCOeNzMreN0tH8t8UDZwSekYCBfeNx5b2Y7i6IsPgSMJbQ6xw3/aH4fe4+bIxUWuGmJlPRQT2NiR1O1KxEVFNvAgOhw14bOh0gnRRMnwKnf3v0yOkCPspXxu5mkczdXuQg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=l4smij/kG6dq+0f9+u75XypkXVO1jpI1hr1hKqV7GcU=; b=BB1787cELTPbv+na6WQmoTdkOqmOZh0zGICsHXjy+19ZqP/laZPgMK9BTN7Er6gNrse7QVyKfpsqtnF2PLAmNb9MPvNzb/2lvpkPRnFBYA6bqQUzsxda+yTCvpqIZuckHkXEdUfI8cGbq3+3xAeCuFbnbulsKFchur37/6ixkT+Cp76FuKRk3Pumpa2iHRNm7i4+2PU8uz3DKLuPoXFep766cqcf6O0zJxyo68csCI5w+t1hRdLdiZLdbPaZBONGCmO8hqwp4EUAXcowbfgsE5EFLNYsKjRLk0jQw39CAhP1wTgjDBQ1Tyn1rX7UzDi36FWIPF2AyzDrYRzlqDLq/w== Received: from CH0PR08CA0030.namprd08.prod.outlook.com (2603:10b6:610:33::35) by SJ2PR12MB7918.namprd12.prod.outlook.com (2603:10b6:a03:4cc::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.24; Tue, 13 Feb 2024 11:15:53 +0000 Received: from CH2PEPF0000009E.namprd02.prod.outlook.com (2603:10b6:610:33:cafe::37) by CH0PR08CA0030.outlook.office365.com (2603:10b6:610:33::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.40 via Frontend Transport; Tue, 13 Feb 2024 11:15:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009E.mail.protection.outlook.com (10.167.244.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 13 Feb 2024 11:15:52 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb 2024 03:15:40 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Feb 2024 03:15:40 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 13 Feb 2024 03:15:39 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v3 2/4] platform/mellanox: mlxbf-pmc: Fix signed/unsigned mix-up Date: Tue, 13 Feb 2024 06:15:26 -0500 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|SJ2PR12MB7918:EE_ X-MS-Office365-Filtering-Correlation-Id: e864fba9-aa82-435d-497a-08dc2c85244e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6kQdeX9DhVBB9uiJnBnEDBvMdKoVyEdkIN+A7LBurG5zERNfYil8COubHGOclPqiT52nDSOtKqjJu+lfg0VxwBTThTX6BBJD9s/U1Hvrx/0Z7dAGHxlo8LHb1zB2pGRW1LCGNQo2KaD39qpPLVvRK5JcaOHk6UDntlDaST+qYEvXC4zlqku6nbdyryWmXBnWMF6fW0yaFBDJfXyoZhK03FTQnfKDqT26NYNDmFqOn/15yYq3Dig72aNjATwS0OBuqYEc9BDwEYVcYNmy0jUza+hX1mp1/e0pVIoR04eUC3T90h6pm9P5BG6yaqWjaTAf8Vwe9OXV9TnR2RlejVCtjOT8xidDDM8ryWuM9ou3KdqdVP8///ayTaEF8vsCvThCzQ4M3rBHy4p0nQg/IKeg0NeJh5bvWEx06V/0/V1U7gmN6E0J/W5jGDZ/DgszX3Dr8TvtCklVQOPh8TyA5hsAJAbK0vj0Zc/ZGUs0EbLiNiJjQ1LkmuQI3Hc0xSYZNc+H8oFxEfsb/8OA8WKGWhqhu3Xk3m7syc+9VDb2z3zlDJCPlJeHzw99JtqKwytvT7vNFZwXuRpx8LUA76cnr0S5b/LHHCkMDOtOzyPkdN/hg0A= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(396003)(136003)(376002)(230922051799003)(82310400011)(1800799012)(186009)(64100799003)(451199024)(36840700001)(46966006)(40470700004)(86362001)(5660300002)(70206006)(70586007)(8676002)(8936002)(478600001)(4326008)(7696005)(30864003)(2906002)(7636003)(82740400003)(356005)(26005)(41300700001)(83380400001)(2616005)(426003)(336012)(316002)(6666004)(6636002)(54906003)(36756003)(110136005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2024 11:15:52.9588 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e864fba9-aa82-435d-497a-08dc2c85244e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7918 Content-Type: text/plain; charset="utf-8" Use unsigned integer types for register values and array indices. Use %u instead of %d accordingly. Signed-off-by: Shravan Kumar Ramani --- drivers/platform/mellanox/mlxbf-pmc.c | 129 ++++++++++++++------------ 1 file changed, 68 insertions(+), 61 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mella= nox/mlxbf-pmc.c index 86044d1b8fa5..250405bb59a7 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -99,8 +99,8 @@ */ struct mlxbf_pmc_attribute { struct device_attribute dev_attr; - int index; - int nr; + unsigned int index; + unsigned int nr; }; =20 /** @@ -121,7 +121,7 @@ struct mlxbf_pmc_block_info { void __iomem *mmio_base; size_t blk_size; size_t counters; - int type; + unsigned int type; struct mlxbf_pmc_attribute *attr_counter; struct mlxbf_pmc_attribute *attr_event; struct mlxbf_pmc_attribute attr_event_list; @@ -169,7 +169,7 @@ struct mlxbf_pmc_context { * @evt_name: Name of the event */ struct mlxbf_pmc_events { - int evt_num; + u32 evt_num; char *evt_name; }; =20 @@ -956,7 +956,7 @@ static int mlxbf_pmc_write(void __iomem *addr, int comm= and, u64 value) } =20 /* Check if the register offset is within the mapped region for the block = */ -static bool mlxbf_pmc_valid_range(int blk_num, u32 offset) +static bool mlxbf_pmc_valid_range(unsigned int blk_num, u32 offset) { if ((offset >=3D 0) && !(offset % MLXBF_PMC_REG_SIZE) && (offset + MLXBF_PMC_REG_SIZE <=3D pmc->block[blk_num].blk_size)) @@ -966,8 +966,7 @@ static bool mlxbf_pmc_valid_range(int blk_num, u32 offs= et) } =20 /* Get the event list corresponding to a certain block */ -static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk, - int *size) +static const struct mlxbf_pmc_events *mlxbf_pmc_event_list(const char *blk= , size_t *size) { const struct mlxbf_pmc_events *events; =20 @@ -1044,7 +1043,8 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event= _list(const char *blk, static int mlxbf_pmc_get_event_num(const char *blk, const char *evt) { const struct mlxbf_pmc_events *events; - int i, size; + unsigned int i; + size_t size; =20 events =3D mlxbf_pmc_event_list(blk, &size); if (!events) @@ -1059,10 +1059,11 @@ static int mlxbf_pmc_get_event_num(const char *blk,= const char *evt) } =20 /* Get the event number given the name */ -static char *mlxbf_pmc_get_event_name(const char *blk, int evt) +static char *mlxbf_pmc_get_event_name(const char *blk, u32 evt) { const struct mlxbf_pmc_events *events; - int i, size; + unsigned int i; + size_t size; =20 events =3D mlxbf_pmc_event_list(blk, &size); if (!events) @@ -1077,7 +1078,7 @@ static char *mlxbf_pmc_get_event_name(const char *blk= , int evt) } =20 /* Method to enable/disable/reset l3cache counters */ -static int mlxbf_pmc_config_l3_counters(int blk_num, bool enable, bool res= et) +static int mlxbf_pmc_config_l3_counters(unsigned int blk_num, bool enable,= bool reset) { u32 perfcnt_cfg =3D 0; =20 @@ -1092,7 +1093,7 @@ static int mlxbf_pmc_config_l3_counters(int blk_num, = bool enable, bool reset) } =20 /* Method to handle l3cache counter programming */ -static int mlxbf_pmc_program_l3_counter(int blk_num, u32 cnt_num, u32 evt) +static int mlxbf_pmc_program_l3_counter(unsigned int blk_num, u32 cnt_num,= u32 evt) { u32 perfcnt_sel_1 =3D 0, perfcnt_sel =3D 0, *wordaddr; void __iomem *pmcaddr; @@ -1156,7 +1157,7 @@ static int mlxbf_pmc_program_l3_counter(int blk_num, = u32 cnt_num, u32 evt) } =20 /* Method to handle crspace counter programming */ -static int mlxbf_pmc_program_crspace_counter(int blk_num, u32 cnt_num, u32= evt) +static int mlxbf_pmc_program_crspace_counter(unsigned int blk_num, u32 cnt= _num, u32 evt) { void *addr; u32 word; @@ -1180,7 +1181,7 @@ static int mlxbf_pmc_program_crspace_counter(int blk_= num, u32 cnt_num, u32 evt) } =20 /* Method to clear crspace counter value */ -static int mlxbf_pmc_clear_crspace_counter(int blk_num, u32 cnt_num) +static int mlxbf_pmc_clear_crspace_counter(unsigned int blk_num, u32 cnt_n= um) { void *addr; =20 @@ -1192,7 +1193,7 @@ static int mlxbf_pmc_clear_crspace_counter(int blk_nu= m, u32 cnt_num) } =20 /* Method to program a counter to monitor an event */ -static int mlxbf_pmc_program_counter(int blk_num, u32 cnt_num, u32 evt, bo= ol is_l3) +static int mlxbf_pmc_program_counter(unsigned int blk_num, u32 cnt_num, u3= 2 evt, bool is_l3) { u64 perfctl, perfevt, perfmon_cfg; =20 @@ -1255,7 +1256,7 @@ static int mlxbf_pmc_program_counter(int blk_num, u32= cnt_num, u32 evt, bool is_ } =20 /* Method to handle l3 counter reads */ -static int mlxbf_pmc_read_l3_counter(int blk_num, u32 cnt_num, u64 *result) +static int mlxbf_pmc_read_l3_counter(unsigned int blk_num, u32 cnt_num, u6= 4 *result) { u32 perfcnt_low =3D 0, perfcnt_high =3D 0; int status; @@ -1286,7 +1287,7 @@ static int mlxbf_pmc_read_l3_counter(int blk_num, u32= cnt_num, u64 *result) } =20 /* Method to handle crspace counter reads */ -static int mlxbf_pmc_read_crspace_counter(int blk_num, u32 cnt_num, u64 *r= esult) +static int mlxbf_pmc_read_crspace_counter(unsigned int blk_num, u32 cnt_nu= m, u64 *result) { int status =3D 0; u32 value; @@ -1303,7 +1304,7 @@ static int mlxbf_pmc_read_crspace_counter(int blk_num= , u32 cnt_num, u64 *result) } =20 /* Method to read the counter value */ -static int mlxbf_pmc_read_counter(int blk_num, u32 cnt_num, bool is_l3, u6= 4 *result) +static int mlxbf_pmc_read_counter(unsigned int blk_num, u32 cnt_num, bool = is_l3, u64 *result) { u32 perfcfg_offset, perfval_offset; u64 perfmon_cfg; @@ -1340,7 +1341,7 @@ static int mlxbf_pmc_read_counter(int blk_num, u32 cn= t_num, bool is_l3, u64 *res } =20 /* Method to read L3 block event */ -static int mlxbf_pmc_read_l3_event(int blk_num, u32 cnt_num, u64 *result) +static int mlxbf_pmc_read_l3_event(unsigned int blk_num, u32 cnt_num, u64 = *result) { u32 perfcnt_sel =3D 0, perfcnt_sel_1 =3D 0, *wordaddr; void __iomem *pmcaddr; @@ -1392,7 +1393,7 @@ static int mlxbf_pmc_read_l3_event(int blk_num, u32 c= nt_num, u64 *result) } =20 /* Method to read crspace block event */ -static int mlxbf_pmc_read_crspace_event(int blk_num, u32 cnt_num, u64 *res= ult) +static int mlxbf_pmc_read_crspace_event(unsigned int blk_num, u32 cnt_num,= u64 *result) { u32 word, evt; void *addr; @@ -1415,7 +1416,7 @@ static int mlxbf_pmc_read_crspace_event(int blk_num, = u32 cnt_num, u64 *result) } =20 /* Method to find the event currently being monitored by a counter */ -static int mlxbf_pmc_read_event(int blk_num, u32 cnt_num, bool is_l3, u64 = *result) +static int mlxbf_pmc_read_event(unsigned int blk_num, u32 cnt_num, bool is= _l3, u64 *result) { u32 perfcfg_offset, perfval_offset; u64 perfmon_cfg, perfevt; @@ -1454,7 +1455,7 @@ static int mlxbf_pmc_read_event(int blk_num, u32 cnt_= num, bool is_l3, u64 *resul } =20 /* Method to read a register */ -static int mlxbf_pmc_read_reg(int blk_num, u32 offset, u64 *result) +static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *resul= t) { u32 ecc_out; =20 @@ -1475,7 +1476,7 @@ static int mlxbf_pmc_read_reg(int blk_num, u32 offset= , u64 *result) } =20 /* Method to write to a register */ -static int mlxbf_pmc_write_reg(int blk_num, u32 offset, u64 data) +static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, @@ -1495,7 +1496,7 @@ static ssize_t mlxbf_pmc_counter_show(struct device *= dev, { struct mlxbf_pmc_attribute *attr_counter =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - int blk_num, cnt_num, offset; + unsigned int blk_num, cnt_num, offset; bool is_l3 =3D false; u64 value; =20 @@ -1529,14 +1530,15 @@ static ssize_t mlxbf_pmc_counter_store(struct devic= e *dev, { struct mlxbf_pmc_attribute *attr_counter =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - int blk_num, cnt_num, offset, err, data; + unsigned int blk_num, cnt_num, offset, data; bool is_l3 =3D false; u64 evt_num; + int err; =20 blk_num =3D attr_counter->nr; cnt_num =3D attr_counter->index; =20 - err =3D kstrtoint(buf, 0, &data); + err =3D kstrtouint(buf, 0, &data); if (err < 0) return err; =20 @@ -1565,7 +1567,7 @@ static ssize_t mlxbf_pmc_counter_store(struct device = *dev, if (err) return err; } else if (pmc->block[blk_num].type =3D=3D MLXBF_PMC_TYPE_CRSPACE) { - if (sscanf(attr->attr.name, "counter%d", &cnt_num) !=3D 1) + if (sscanf(attr->attr.name, "counter%u", &cnt_num) !=3D 1) return -EINVAL; err =3D mlxbf_pmc_clear_crspace_counter(blk_num, cnt_num); } else @@ -1580,10 +1582,11 @@ static ssize_t mlxbf_pmc_event_show(struct device *= dev, { struct mlxbf_pmc_attribute *attr_event =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - int blk_num, cnt_num, err; + unsigned int blk_num, cnt_num; bool is_l3 =3D false; - u64 evt_num; char *evt_name; + u64 evt_num; + int err; =20 blk_num =3D attr_event->nr; cnt_num =3D attr_event->index; @@ -1609,8 +1612,9 @@ static ssize_t mlxbf_pmc_event_store(struct device *d= ev, { struct mlxbf_pmc_attribute *attr_event =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - int blk_num, cnt_num, evt_num, err; + unsigned int blk_num, cnt_num, evt_num; bool is_l3 =3D false; + int err; =20 blk_num =3D attr_event->nr; cnt_num =3D attr_event->index; @@ -1621,7 +1625,7 @@ static ssize_t mlxbf_pmc_event_store(struct device *d= ev, if (evt_num < 0) return -EINVAL; } else { - err =3D kstrtoint(buf, 0, &evt_num); + err =3D kstrtouint(buf, 0, &evt_num); if (err < 0) return err; } @@ -1643,9 +1647,11 @@ static ssize_t mlxbf_pmc_event_list_show(struct devi= ce *dev, { struct mlxbf_pmc_attribute *attr_event_list =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - int blk_num, i, size, len =3D 0, ret =3D 0; const struct mlxbf_pmc_events *events; char e_info[MLXBF_PMC_EVENT_INFO_LEN]; + unsigned int blk_num, i, len =3D 0; + size_t size; + int ret =3D 0; =20 blk_num =3D attr_event_list->nr; =20 @@ -1671,8 +1677,8 @@ static ssize_t mlxbf_pmc_enable_show(struct device *d= ev, { struct mlxbf_pmc_attribute *attr_enable =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num, value; u32 perfcnt_cfg, word; - int blk_num, value; =20 blk_num =3D attr_enable->nr; =20 @@ -1692,7 +1698,7 @@ static ssize_t mlxbf_pmc_enable_show(struct device *d= ev, value =3D FIELD_GET(MLXBF_PMC_L3C_PERF_CNT_CFG_EN, perfcnt_cfg); } =20 - return sysfs_emit(buf, "%d\n", value); + return sysfs_emit(buf, "%u\n", value); } =20 /* Store function for "enable" sysfs files - only for l3cache & crspace */ @@ -1702,12 +1708,13 @@ static ssize_t mlxbf_pmc_enable_store(struct device= *dev, { struct mlxbf_pmc_attribute *attr_enable =3D container_of( attr, struct mlxbf_pmc_attribute, dev_attr); - int err, en, blk_num; + unsigned int en, blk_num; u32 word; + int err; =20 blk_num =3D attr_enable->nr; =20 - err =3D kstrtoint(buf, 0, &en); + err =3D kstrtouint(buf, 0, &en); if (err < 0) return err; =20 @@ -1745,10 +1752,10 @@ static ssize_t mlxbf_pmc_enable_store(struct device= *dev, } =20 /* Populate attributes for blocks with counters to monitor performance */ -static int mlxbf_pmc_init_perftype_counter(struct device *dev, int blk_num) +static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned in= t blk_num) { struct mlxbf_pmc_attribute *attr; - int i =3D 0, j =3D 0; + unsigned int i =3D 0, j =3D 0; =20 /* "event_list" sysfs to list events supported by the block */ attr =3D &pmc->block[blk_num].attr_event_list; @@ -1797,8 +1804,7 @@ static int mlxbf_pmc_init_perftype_counter(struct dev= ice *dev, int blk_num) attr->dev_attr.store =3D mlxbf_pmc_counter_store; attr->index =3D j; attr->nr =3D blk_num; - attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, - "counter%d", j); + attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, "counter%u"= , j); if (!attr->dev_attr.attr.name) return -ENOMEM; pmc->block[blk_num].block_attr[++i] =3D &attr->dev_attr.attr; @@ -1810,8 +1816,7 @@ static int mlxbf_pmc_init_perftype_counter(struct dev= ice *dev, int blk_num) attr->dev_attr.store =3D mlxbf_pmc_event_store; attr->index =3D j; attr->nr =3D blk_num; - attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, - "event%d", j); + attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, "event%u", = j); if (!attr->dev_attr.attr.name) return -ENOMEM; pmc->block[blk_num].block_attr[++i] =3D &attr->dev_attr.attr; @@ -1822,30 +1827,31 @@ static int mlxbf_pmc_init_perftype_counter(struct d= evice *dev, int blk_num) } =20 /* Populate attributes for blocks with registers to monitor performance */ -static int mlxbf_pmc_init_perftype_reg(struct device *dev, int blk_num) +static int mlxbf_pmc_init_perftype_reg(struct device *dev, unsigned int bl= k_num) { - struct mlxbf_pmc_attribute *attr; const struct mlxbf_pmc_events *events; - int i =3D 0, j =3D 0; + struct mlxbf_pmc_attribute *attr; + unsigned int i =3D 0; + size_t count =3D 0; =20 - events =3D mlxbf_pmc_event_list(pmc->block_name[blk_num], &j); + events =3D mlxbf_pmc_event_list(pmc->block_name[blk_num], &count); if (!events) return -EINVAL; =20 pmc->block[blk_num].attr_event =3D devm_kcalloc( - dev, j, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL); + dev, count, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL); if (!pmc->block[blk_num].attr_event) return -ENOMEM; =20 - while (j > 0) { - --j; - attr =3D &pmc->block[blk_num].attr_event[j]; + while (count > 0) { + --count; + attr =3D &pmc->block[blk_num].attr_event[count]; attr->dev_attr.attr.mode =3D 0644; attr->dev_attr.show =3D mlxbf_pmc_counter_show; attr->dev_attr.store =3D mlxbf_pmc_counter_store; attr->nr =3D blk_num; attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, - events[j].evt_name); + events[count].evt_name); if (!attr->dev_attr.attr.name) return -ENOMEM; pmc->block[blk_num].block_attr[i] =3D &attr->dev_attr.attr; @@ -1857,7 +1863,7 @@ static int mlxbf_pmc_init_perftype_reg(struct device = *dev, int blk_num) } =20 /* Helper to create the bfperf sysfs sub-directories and files */ -static int mlxbf_pmc_create_groups(struct device *dev, int blk_num) +static int mlxbf_pmc_create_groups(struct device *dev, unsigned int blk_nu= m) { int err; =20 @@ -1900,18 +1906,19 @@ static bool mlxbf_pmc_guid_match(const guid_t *guid, static int mlxbf_pmc_map_counters(struct device *dev) { u64 info[MLXBF_PMC_INFO_SZ]; - int i, tile_num, ret; + unsigned int tile_num, i; + int ret; =20 for (i =3D 0; i < pmc->total_blocks; ++i) { /* Create sysfs for tiles only if block number < tile_count */ if (strstr(pmc->block_name[i], "tilenet")) { - if (sscanf(pmc->block_name[i], "tilenet%d", &tile_num) !=3D 1) + if (sscanf(pmc->block_name[i], "tilenet%u", &tile_num) !=3D 1) continue; =20 if (tile_num >=3D pmc->tile_count) continue; } else if (strstr(pmc->block_name[i], "tile")) { - if (sscanf(pmc->block_name[i], "tile%d", &tile_num) !=3D 1) + if (sscanf(pmc->block_name[i], "tile%u", &tile_num) !=3D 1) continue; =20 if (tile_num >=3D pmc->tile_count) @@ -1921,9 +1928,9 @@ static int mlxbf_pmc_map_counters(struct device *dev) /* Create sysfs only for enabled MSS blocks */ if (strstr(pmc->block_name[i], "mss") && pmc->event_set =3D=3D MLXBF_PMC_EVENT_SET_BF3) { - int mss_num; + unsigned int mss_num; =20 - if (sscanf(pmc->block_name[i], "mss%d", &mss_num) !=3D 1) + if (sscanf(pmc->block_name[i], "mss%u", &mss_num) !=3D 1) continue; =20 if (!((pmc->mss_enable >> mss_num) & 0x1)) @@ -1932,17 +1939,17 @@ static int mlxbf_pmc_map_counters(struct device *de= v) =20 /* Create sysfs only for enabled LLT blocks */ if (strstr(pmc->block_name[i], "llt_miss")) { - int llt_num; + unsigned int llt_num; =20 - if (sscanf(pmc->block_name[i], "llt_miss%d", &llt_num) !=3D 1) + if (sscanf(pmc->block_name[i], "llt_miss%u", &llt_num) !=3D 1) continue; =20 if (!((pmc->llt_enable >> llt_num) & 0x1)) continue; } else if (strstr(pmc->block_name[i], "llt")) { - int llt_num; + unsigned int llt_num; =20 - if (sscanf(pmc->block_name[i], "llt%d", &llt_num) !=3D 1) + if (sscanf(pmc->block_name[i], "llt%u", &llt_num) !=3D 1) continue; =20 if (!((pmc->llt_enable >> llt_num) & 0x1)) --=20 2.30.1 From nobody Fri May 17 04:59:58 2024 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2060.outbound.protection.outlook.com [40.107.92.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BA7137715; Tue, 13 Feb 2024 11:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.92.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822967; cv=fail; b=d0LiiA59hGpjW1nAjqjZpC+kF8XkOI2IRy536fJO21eXFSf8JGYO/Dn68PVY6XWBGhW/Nmy/siih0xRx0/ysZgI5N+wlV6SfsXY2Nsc3CI7DWzG9HEr6K+2wx0MUbc+QQOWaZAkCrdQGTtE/4ri5va4rx6QlORe1Q08mgnG/Tzc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822967; c=relaxed/simple; bh=Apl11HVjbUMRZbtvERcmPJSZcq7c341hvsj4EOgI6lw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Fl7mUYgKS5t1ecU3JxBdtuVfg5y+//0HtoVc9/dAWsJqtrEG5I6AbN+GG7RENvRAY1n402wVIjkeNN2GFXObGB940nt5xHCLBHtyd6fuK9b7zU0fbV7ALfzsaqlLWST8kwZWhyyKtiFvzUiXMBStdz4cgRQU2mpj45D3/pRp3Zc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ZJcHPtjW; arc=fail smtp.client-ip=40.107.92.60 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ZJcHPtjW" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IWZ77015bRil6X5Xr67cIr1A9juSXF7KKhJjZL3CG1vQVtFPl0fOrWjX5gu8e71/RiV5wmA0TWFlLDhHxfJajwS9BUgeZGyxEe15t0tvPjxDMmbwLVn1ix73EpefPhfMMzfH92Yzqu2dVxf+PFbVUzaSodq/ifAJuNsKcAy7jk1pQUDPPjaTKV/75zK4KF4XLMOHKxHecII0TI7X4FiirqGrmGvmBAxPdYpYK0onhPvvq+Cu3kA+9ub4BpnLqGsnbUhTI5SYYK4jf1gdzX+tQo7RjJM1Lg2ifk1JY94L0RtvwdwMXMwmIbDOc5oe/ODa77IBvWk5UPF1URclRgEKgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=nRR1k1bcbQ7EzfF9+NsdS62xy4Q/64ebL5m5XlOcf3w=; b=OSgHiEQcgyjwB9GRAXTSzMS9uCEVA5NuLTiukgZ62MTSt/VEsXtBqaj1AGqykaPXpXO0OWR+J/KgV0MjR83GDu4/r1S5gsKOJgvnij3L2wdLAMYSn9ASVhFSbT8/2VSFN7Ol4drJwAHRpACkvjsi0LTNxwu5kLONgNsDtQrC1vvog3IQ7vOQvGwYh7LjW7/EWnhpp8QpleVnhK0uDfbk28NHDQzvPqW5GOC2KuJh4c5fG0nW+IuuFxvFniZwz8BKHlAPTR/ZOrNUSjY3lnnDaztQdKxJiGEwVQA3Gm3JfGKGPmr2ccfht9PlQ4aNinGO84WpcZZ7bst0qo0IG4N05w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=nRR1k1bcbQ7EzfF9+NsdS62xy4Q/64ebL5m5XlOcf3w=; b=ZJcHPtjWxsD8F9HnMan1HyaBtuvSQFnLKI7yz5bWNKR2aHmSM/s1bTCu5b+jH8cYPbLZsut+3lvfJi0ShJFlP94+usKq0CmYrUQrM6TkB7PLEviTWJy88bIfeQ0gP1TPI602+Bg5QFNiwBH4SukHYT/iR043lRqHtMXrgQAqCJI+VB/WZ5R4N5B+A2E799aVYuK4N9IjZOQ/LbIbxM6jXNXqmnmECBeElVYJsG9vgQZp+oqGK4QiGNrQkcvgvzA0d35PKlUm3YevRy/EuODHugo+wgcwEPMaVySOx0VqCsoVH9VwfZqKHSAdi0ztiKEk1Ue6A+4XPknkdH6iIFlokg== Received: from SJ0PR03CA0046.namprd03.prod.outlook.com (2603:10b6:a03:33e::21) by SA1PR12MB9247.namprd12.prod.outlook.com (2603:10b6:806:3af::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25; Tue, 13 Feb 2024 11:15:58 +0000 Received: from SJ5PEPF000001CA.namprd05.prod.outlook.com (2603:10b6:a03:33e:cafe::ee) by SJ0PR03CA0046.outlook.office365.com (2603:10b6:a03:33e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.40 via Frontend Transport; Tue, 13 Feb 2024 11:15:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by SJ5PEPF000001CA.mail.protection.outlook.com (10.167.242.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 13 Feb 2024 11:15:57 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb 2024 03:15:42 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Feb 2024 03:15:42 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 13 Feb 2024 03:15:41 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v3 3/4] platform/mellanox: mlxbf-pmc: Add support for 64-bit counters and cycle count Date: Tue, 13 Feb 2024 06:15:27 -0500 Message-ID: X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CA:EE_|SA1PR12MB9247:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bf02be4-92ce-49d8-60b0-08dc2c852705 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GptkxDxOWr6vGiwJeySZJy+G6mqFdiMM/54tE2g9sqfv8BnqoiLYeYIKffHSnrolnu6yZXD4trB5GGnqH6q1pI1nrNh1Fm++N8tz8m6TwBKQY2T5Bzq2acCjPngV2v1M40XA5ej5k0lxhvuZ1cn1LMeTOHU/VkuDBRWb8t6qG2zioCvavmxlYSfEmPjBmyk7yshF8XwXaT30sTnuzqJ09O0C5l4S56zQn+7+YWBk1GJ91insXvOvi4tnX5aAppWiGs+89xLjx8THSok7RztCaj8A5nbEFT1hmxCTT+6lMt1SwRVUvxhTJzDe6gcQ/RqgZy3Tnb6gkkvH1BMwLoa9UvD0Vm5+yDCUrFStGjVHr/tCZcS3mW0bLKDGVYL06AwkeAtXqr2ZDdYzYIvEzavRR9dckIie3ZHhzZhK8itQv7bSFmB0uSg689t1ea0s0LuXaqSXYRzK0QaI5wi3HU3pSBfhqtyJ1n1Oxv+It/nwZaTLfOkP2lEr/XvFCx+ueKAtzo1YcYbS6NmFBEuiywFIbjEDZ8DryVYARqSuAk6dAcGnfV5L7OjbLl38VPgqY7sCqbx8NOwvAQBArOEGrOmvJji+ZCtOkKv4YCV2nmIW4IA= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(39860400002)(346002)(136003)(230922051799003)(64100799003)(451199024)(1800799012)(186009)(82310400011)(46966006)(36840700001)(40470700004)(41300700001)(2906002)(4326008)(6666004)(36756003)(2616005)(7696005)(478600001)(356005)(86362001)(7636003)(83380400001)(26005)(426003)(336012)(82740400003)(8676002)(8936002)(5660300002)(110136005)(70206006)(70586007)(6636002)(316002)(54906003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2024 11:15:57.6391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bf02be4-92ce-49d8-60b0-08dc2c852705 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CA.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9247 Content-Type: text/plain; charset="utf-8" Add support for programming any counter to monitor the cycle count. Since counting of cycles using 32-bit ocunters would result in frequent wraparounds, add the ability to combine 2 adjacent 32-bit counters to form 1 64-bit counter. Both these features are supported by BlueField-3 PMC hardware, hence the required bit-fields are exposed by the driver via sysfs to allow the user to configure as needed. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 134 ++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mella= nox/mlxbf-pmc.c index 250405bb59a7..e2f11c0c63e9 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -88,6 +88,8 @@ #define MLXBF_PMC_CRSPACE_PERFMON_CTL(n) (n * MLXBF_PMC_CRSPACE_PERFMON_RE= G0_SZ) #define MLXBF_PMC_CRSPACE_PERFMON_EN BIT(30) #define MLXBF_PMC_CRSPACE_PERFMON_CLR BIT(28) +#define MLXBF_PMC_CRSPACE_PERFMON_UOC GENMASK(15, 0) +#define MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(n) (MLXBF_PMC_CRSPACE_PERFMO= N_CTL(n) + 0x4) #define MLXBF_PMC_CRSPACE_PERFMON_VAL0(n) (MLXBF_PMC_CRSPACE_PERFMON_CTL(n= ) + 0xc) =20 /** @@ -114,6 +116,8 @@ struct mlxbf_pmc_attribute { * @attr_event: Attributes for "event" sysfs files * @attr_event_list: Attributes for "event_list" sysfs files * @attr_enable: Attributes for "enable" sysfs files + * @attr_use_odd_counter: Attributes for "use_odd_counter" sysfs files + * @attr_count_clock: Attributes for "count_clock" sysfs files * @block_attr: All attributes needed for the block * @block_attr_grp: Attribute group for the block */ @@ -126,6 +130,8 @@ struct mlxbf_pmc_block_info { struct mlxbf_pmc_attribute *attr_event; struct mlxbf_pmc_attribute attr_event_list; struct mlxbf_pmc_attribute attr_enable; + struct mlxbf_pmc_attribute attr_use_odd_counter; + struct mlxbf_pmc_attribute attr_count_clock; struct attribute *block_attr[MLXBF_PMC_MAX_ATTRS]; struct attribute_group block_attr_grp; }; @@ -1751,6 +1757,103 @@ static ssize_t mlxbf_pmc_enable_store(struct device= *dev, return count; } =20 +/* Show function for "use_odd_counter" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_use_odd_counter_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_use_odd_counter =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 value, reg; + + blk_num =3D attr_use_odd_counter->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + value =3D FIELD_GET(MLXBF_PMC_CRSPACE_PERFMON_UOC, reg); + + return sysfs_emit(buf, "%u\n", value); +} + +/* Store function for "use_odd_counter" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_use_odd_counter_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_use_odd_counter =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 uoc, reg; + int err; + + blk_num =3D attr_use_odd_counter->nr; + + err =3D kstrtouint(buf, 0, &uoc); + if (err < 0) + return err; + + err =3D mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + ®); + if (err) + return -EINVAL; + + reg &=3D ~MLXBF_PMC_CRSPACE_PERFMON_UOC; + reg |=3D FIELD_PREP(MLXBF_PMC_CRSPACE_PERFMON_UOC, uoc); + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_CTL(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + +/* Show function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mlxbf_pmc_attribute *attr_count_clock =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + + blk_num =3D attr_count_clock->nr; + + if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + ®)) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", reg); +} + +/* Store function for "count_clock" sysfs files - only for crspace */ +static ssize_t mlxbf_pmc_count_clock_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mlxbf_pmc_attribute *attr_count_clock =3D container_of( + attr, struct mlxbf_pmc_attribute, dev_attr); + unsigned int blk_num; + u32 reg; + int err; + + blk_num =3D attr_count_clock->nr; + + err =3D kstrtouint(buf, 0, ®); + if (err < 0) + return err; + + mlxbf_pmc_write(pmc->block[blk_num].mmio_base + + MLXBF_PMC_CRSPACE_PERFMON_COUNT_CLOCK(pmc->block[blk_num].counters), + MLXBF_PMC_WRITE_REG_32, reg); + + return count; +} + /* Populate attributes for blocks with counters to monitor performance */ static int mlxbf_pmc_init_perftype_counter(struct device *dev, unsigned in= t blk_num) { @@ -1784,6 +1887,37 @@ static int mlxbf_pmc_init_perftype_counter(struct de= vice *dev, unsigned int blk_ attr =3D NULL; } =20 + if (pmc->block[blk_num].type =3D=3D MLXBF_PMC_TYPE_CRSPACE) { + /* + * Couple adjacent odd and even 32-bit counters to form 64-bit counters + * using "use_odd_counter" sysfs which has one bit per even counter. + */ + attr =3D &pmc->block[blk_num].attr_use_odd_counter; + attr->dev_attr.attr.mode =3D 0644; + attr->dev_attr.show =3D mlxbf_pmc_use_odd_counter_show; + attr->dev_attr.store =3D mlxbf_pmc_use_odd_counter_store; + attr->nr =3D blk_num; + attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, + "use_odd_counter"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] =3D &attr->dev_attr.attr; + attr =3D NULL; + + /* Program crspace counters to count clock cycles using "count_clock" sy= sfs */ + attr =3D &pmc->block[blk_num].attr_count_clock; + attr->dev_attr.attr.mode =3D 0644; + attr->dev_attr.show =3D mlxbf_pmc_count_clock_show; + attr->dev_attr.store =3D mlxbf_pmc_count_clock_store; + attr->nr =3D blk_num; + attr->dev_attr.attr.name =3D devm_kasprintf(dev, GFP_KERNEL, + "count_clock"); + if (!attr->dev_attr.attr.name) + return -ENOMEM; + pmc->block[blk_num].block_attr[++i] =3D &attr->dev_attr.attr; + attr =3D NULL; + } + pmc->block[blk_num].attr_counter =3D devm_kcalloc( dev, pmc->block[blk_num].counters, sizeof(struct mlxbf_pmc_attribute), GFP_KERNEL); --=20 2.30.1 From nobody Fri May 17 04:59:58 2024 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2077.outbound.protection.outlook.com [40.107.93.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C867B37710; Tue, 13 Feb 2024 11:16:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.93.77 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822963; cv=fail; b=Ww6ddHSRoWqaN5J3B3lkU4AXa0rJOhfcZLlihVvw4MxqZlQ3bErNuc7n+tP4C2LwEN1Sy+tnSl9jLQnm4zHbejhLoH0MbdWMZeeF+7YenWCwS9kdKs9Rkka1sgi2O0aOYAfEbvSpqvcRN7sIL3Ue55ABcSrMgdWpMIGhJkNdbp0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707822963; c=relaxed/simple; bh=Jy6eVYV3XOONq40i68ru4ykCL2BVRK/o9lE5PSdfHIY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R20d7jeJKhUGw9NxgxK+S5sSLotZTAw8tNdKMRoUNOhIgNGEQeD1bpyqInf0NcT1LE7cNo2M1HcDwOvjN6bIKuBHfUP01FRfkj5WH/RGmPM8lwO8rS+oLLbJoEe56OX3i8ppxmznJboQGYGPnZWXJV6OLXjhjraf69qjFrYwb/4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=aIqqe8VX; arc=fail smtp.client-ip=40.107.93.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="aIqqe8VX" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HTOID17ZIqFfMlGj+wezFp39+c84C3mSTPbrjvBX6OPGaB5kR+F6PED1/hIdaejTVfH0AOjfR4V2UjC+pcxf2YWUTg+SinpjKT8t827XfqTBX1XoG1JTekuWhZI9NKF3d7lnZriQGak17qBXnGjqw0pbrdfMrbTk7aVRyaJiv5HZAI5UFlXAGC4UKTwW2nxx1u6C0IYXilxUChTRpuw+rn8aEZ6xWGoDA7Ia8zaW2TLBQKA6xc7ga6DWS/+I9eL1l988JDbo3BeUZXgYNWbJh7Io1Vww5V8u2CAZGcoaze4YErpNzDCU51J/wRRbXyvm0guDnfB6dXKuyVL8OrqabA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ThFSIJZGp841I63Van74rEmxPS4mnIBwWMX9Kk8WlPY=; b=no5ygbdd6mALKx5Fw7EUqJO6ti6P+pvuyteTfndaDOQ40ooI3BtfyuH2Cwd9KDv+9J0oos+MbquhkrLJU71RIMZAFAqy0YCkoObhUxdBMoF2dMMXwWZ9p9VyE8GW4q7s2SOi1wXXLyCVw5kr+e5iiee0AZey1WU+AS04D1qWcAWkN+rFSfZ/fsQWrGlQohHEdyqWp88SZPqArTIqTWZb2igJCTUV9pDVzE44/bTm1jmLjKb6MrHRz/wgne1evw5U6n1LJxw3bhZyJVJFwXplM/lvbopD0vinjzEQkhqEIoag/y3uFzLi9AvPQWKmElyjFlqpWnumipncPg+mJF1azg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ThFSIJZGp841I63Van74rEmxPS4mnIBwWMX9Kk8WlPY=; b=aIqqe8VXN1Rv/C4ajeGcqsS+3+z+dO71qikoIdK0ci4/cjj6NGDW0LWX9oRWKNniJhd02ZPQH42s743OF+E2gcDvo58+vtCbiX06jBBkyZ5cSyHwfxLKCmjM96xhyQJXDdxpzJYY5JarQw0P7kssI3z7EuwjHoBmt7D9VyFR+aUtea9yji98I4cmcdCSc+o/nMq6JblYr7eGBj6roaukSsDYnuPZQ8qLQ4x2q/m5m72iV/Mzd0+NLCwcFA+nDYa1oMDKhejQW6zsPIkUZ2HMVRnI4bW7hFAnw/MuwFaRxL6apc40vwM0/bvREtu/o+fMd5bK4xVwdhtY1rMbBnSp3g== Received: from CH2PR16CA0007.namprd16.prod.outlook.com (2603:10b6:610:50::17) by DM4PR12MB5232.namprd12.prod.outlook.com (2603:10b6:5:39c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25; Tue, 13 Feb 2024 11:15:59 +0000 Received: from CH2PEPF0000009A.namprd02.prod.outlook.com (2603:10b6:610:50:cafe::96) by CH2PR16CA0007.outlook.office365.com (2603:10b6:610:50::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.39 via Frontend Transport; Tue, 13 Feb 2024 11:15:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Tue, 13 Feb 2024 11:15:59 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb 2024 03:15:44 -0800 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 13 Feb 2024 03:15:44 -0800 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Tue, 13 Feb 2024 03:15:43 -0800 From: Shravan Kumar Ramani To: Hans de Goede , Ilpo Jarvinen , Vadim Pasternak , "David Thompson" CC: Shravan Kumar Ramani , , Subject: [PATCH v3 4/4] platform/mellanox: mlxbf-pmc: Add support for clock_measure performance block Date: Tue, 13 Feb 2024 06:15:28 -0500 Message-ID: <1c2f1b6da51523fe0f338f9ddce9e3903148f604.1707808180.git.shravankr@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009A:EE_|DM4PR12MB5232:EE_ X-MS-Office365-Filtering-Correlation-Id: 747482e4-121d-4650-29aa-08dc2c8527f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: T9RBRNlAH7ykjg3as2NI2CnHr0k/UHn4/hi26pMtN0nCJo3f+QDe3rPKAw9BLWqkZitaWov6CBjMaaSXPAYjfNY1dv4orHsseFLz+5NRZ3BEOl13QBdqEFeRK2BoRQC5PNdrC3k6QFcaASxd6elao84WDij6oaTrppHVRmOmSicT5LgB+XPFJgQ8CWVoDsI6WdyONRIsJY0YZOF4bztifGumCc7hD6B6OsyNaR1h6gdRZejl1NmBzKXKbjWlL3Lf/hQm7PbHDkvChgwh12fGIqeP5zeAiBwoCOU+Lrs8yTF/bMVAsBwkK/mt4T/RPx/o+5eraVikF8AIiraLiH9hBILi1p7X3L8GuR8Q7XWvY1BZm4u538S5qZc+G0FOgDqEQigqoapYSpxbsaZb+Lf7RfbPXVTWFHcIgXOrJZBlqsN0g0uzI5ucpsUcCau6zlCC8K0gPoO8v2BZ0Vdju4bxQDve+WUvjdGNdb9zKchqi+Gyvjc+doEtF2xkxyPt/WhV8jwip0hQV18UjtQf0ER+mjBOGwbip3DlfuZvPDcaHPP/5qblVBrLrFG3ry200EK5UBrZAjqb/ZhKUk/CPE70M5oiE6Yo45hGq8x6VQNwquA= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(396003)(376002)(39860400002)(346002)(230922051799003)(186009)(82310400011)(451199024)(64100799003)(1800799012)(40470700004)(36840700001)(46966006)(316002)(110136005)(54906003)(70586007)(70206006)(6636002)(41300700001)(2906002)(5660300002)(8676002)(8936002)(4326008)(478600001)(6666004)(2616005)(7696005)(36756003)(82740400003)(83380400001)(86362001)(26005)(336012)(426003)(7636003)(356005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2024 11:15:59.0528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 747482e4-121d-4650-29aa-08dc2c8527f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5232 Content-Type: text/plain; charset="utf-8" The HW clock_measure counter info is passed to the driver from ACPI. Create a new sub-directory for clock_measure events and provide read access to the user. Writes are blocked since the fields are RO. Signed-off-by: Shravan Kumar Ramani Reviewed-by: David Thompson Reviewed-by: Vadim Pasternak --- drivers/platform/mellanox/mlxbf-pmc.c | 46 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 4 deletions(-) diff --git a/drivers/platform/mellanox/mlxbf-pmc.c b/drivers/platform/mella= nox/mlxbf-pmc.c index e2f11c0c63e9..b14fec062e62 100644 --- a/drivers/platform/mellanox/mlxbf-pmc.c +++ b/drivers/platform/mellanox/mlxbf-pmc.c @@ -865,6 +865,37 @@ static const struct mlxbf_pmc_events mlxbf_pmc_llt_mis= s_events[] =3D { {75, "HISTOGRAM_HISTOGRAM_BIN9"}, }; =20 +static const struct mlxbf_pmc_events mlxbf_pmc_clock_events[] =3D { + { 0x0, "FMON_CLK_LAST_COUNT_PLL_D1_INST0" }, + { 0x4, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST0" }, + { 0x8, "FMON_CLK_LAST_COUNT_PLL_D1_INST1" }, + { 0xc, "REFERENCE_WINDOW_WIDTH_PLL_D1_INST1" }, + { 0x10, "FMON_CLK_LAST_COUNT_PLL_G1" }, + { 0x14, "REFERENCE_WINDOW_WIDTH_PLL_G1" }, + { 0x18, "FMON_CLK_LAST_COUNT_PLL_W1" }, + { 0x1c, "REFERENCE_WINDOW_WIDTH_PLL_W1" }, + { 0x20, "FMON_CLK_LAST_COUNT_PLL_T1" }, + { 0x24, "REFERENCE_WINDOW_WIDTH_PLL_T1" }, + { 0x28, "FMON_CLK_LAST_COUNT_PLL_A0" }, + { 0x2c, "REFERENCE_WINDOW_WIDTH_PLL_A0" }, + { 0x30, "FMON_CLK_LAST_COUNT_PLL_C0" }, + { 0x34, "REFERENCE_WINDOW_WIDTH_PLL_C0" }, + { 0x38, "FMON_CLK_LAST_COUNT_PLL_N1" }, + { 0x3c, "REFERENCE_WINDOW_WIDTH_PLL_N1" }, + { 0x40, "FMON_CLK_LAST_COUNT_PLL_I1" }, + { 0x44, "REFERENCE_WINDOW_WIDTH_PLL_I1" }, + { 0x48, "FMON_CLK_LAST_COUNT_PLL_R1" }, + { 0x4c, "REFERENCE_WINDOW_WIDTH_PLL_R1" }, + { 0x50, "FMON_CLK_LAST_COUNT_PLL_P1" }, + { 0x54, "REFERENCE_WINDOW_WIDTH_PLL_P1" }, + { 0x58, "FMON_CLK_LAST_COUNT_REF_100_INST0" }, + { 0x5c, "REFERENCE_WINDOW_WIDTH_REF_100_INST0" }, + { 0x60, "FMON_CLK_LAST_COUNT_REF_100_INST1" }, + { 0x64, "REFERENCE_WINDOW_WIDTH_REF_100_INST1" }, + { 0x68, "FMON_CLK_LAST_COUNT_REF_156" }, + { 0x6c, "REFERENCE_WINDOW_WIDTH_REF_156" }, +}; + static struct mlxbf_pmc_context *pmc; =20 /* UUID used to probe ATF service. */ @@ -1037,6 +1068,9 @@ static const struct mlxbf_pmc_events *mlxbf_pmc_event= _list(const char *blk, size } else if (strstr(blk, "llt")) { events =3D mlxbf_pmc_llt_events; *size =3D ARRAY_SIZE(mlxbf_pmc_llt_events); + } else if (strstr(blk, "clock_measure")) { + events =3D mlxbf_pmc_clock_events; + *size =3D ARRAY_SIZE(mlxbf_pmc_clock_events); } else { events =3D NULL; *size =3D 0; @@ -1463,14 +1497,15 @@ static int mlxbf_pmc_read_event(unsigned int blk_nu= m, u32 cnt_num, bool is_l3, u /* Method to read a register */ static int mlxbf_pmc_read_reg(unsigned int blk_num, u32 offset, u64 *resul= t) { - u32 ecc_out; + u32 reg; =20 - if (strstr(pmc->block_name[blk_num], "ecc")) { + if ((strstr(pmc->block_name[blk_num], "ecc")) || + (strstr(pmc->block_name[blk_num], "clock_measure"))) { if (mlxbf_pmc_readl(pmc->block[blk_num].mmio_base + offset, - &ecc_out)) + ®)) return -EFAULT; =20 - *result =3D ecc_out; + *result =3D reg; return 0; } =20 @@ -1484,6 +1519,9 @@ static int mlxbf_pmc_read_reg(unsigned int blk_num, u= 32 offset, u64 *result) /* Method to write to a register */ static int mlxbf_pmc_write_reg(unsigned int blk_num, u32 offset, u64 data) { + if (strstr(pmc->block_name[blk_num], "clock_measure")) + return -EINVAL; + if (strstr(pmc->block_name[blk_num], "ecc")) { return mlxbf_pmc_write(pmc->block[blk_num].mmio_base + offset, MLXBF_PMC_WRITE_REG_32, data); --=20 2.30.1