From nobody Fri Dec 19 20:10:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 573EBC4332F for ; Sat, 4 Nov 2023 08:53:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbjKDIxe (ORCPT ); Sat, 4 Nov 2023 04:53:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230144AbjKDIxa (ORCPT ); Sat, 4 Nov 2023 04:53:30 -0400 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0BAD9D5E for ; Sat, 4 Nov 2023 01:53:24 -0700 (PDT) Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 202311040852207dfe9c953c6b8895c8 for ; Sat, 04 Nov 2023 09:52:20 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=KRsaZaotDzBqRLlyM/Wzg+W2fZv67OoozB01SLJHNHw=; b=P+a7nJeiwF5LvaBfye56+FlE2wo6GUaqCB1JVay6Fh4k98wv6oJ+s6Fzd5rvqhhgGqbPVc OXvPVoV8AvhKOudR+t4qZgabkpNwLJKen88Pf4rzIzAxIeQuWyvtM7IR32B2I+Nb7o8SiqBt OrjF5tija+ZySecWon8PjD2l5p+dk=; From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Benedikt Niedermayr Subject: [PATCH v4 1/5] arm64: dts: ti: iot2050: Re-add aliases Date: Sat, 4 Nov 2023 09:52:15 +0100 Message-Id: <1edbc1b56ed4ff2256d7afb7db3cab4b3a423692.1699087938.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Lost while dropping them from the common dtsi. Fixes: ffc449e016e2 ("arm64: dts: ti: k3-am65: Drop aliases") Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index ba1c14a54acf..b849648d51f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -14,6 +14,16 @@ =20 / { aliases { + serial0 =3D &wkup_uart0; + serial1 =3D &mcu_uart0; + serial2 =3D &main_uart0; + serial3 =3D &main_uart1; + i2c0 =3D &wkup_i2c0; + i2c1 =3D &mcu_i2c0; + i2c2 =3D &main_i2c0; + i2c3 =3D &main_i2c1; + i2c4 =3D &main_i2c2; + i2c5 =3D &main_i2c3; spi0 =3D &mcu_spi0; mmc0 =3D &sdhci1; mmc1 =3D &sdhci0; --=20 2.35.3 From nobody Fri Dec 19 20:10:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B360DC4332F for ; Sat, 4 Nov 2023 08:53:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230006AbjKDIwc (ORCPT ); Sat, 4 Nov 2023 04:52:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229475AbjKDIw2 (ORCPT ); Sat, 4 Nov 2023 04:52:28 -0400 Received: from mta-65-225.siemens.flowmailer.net (mta-65-225.siemens.flowmailer.net [185.136.65.225]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29596D44 for ; Sat, 4 Nov 2023 01:52:22 -0700 (PDT) Received: by mta-65-225.siemens.flowmailer.net with ESMTPSA id 20231104085220acd58ef895f05d141d for ; Sat, 04 Nov 2023 09:52:21 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=WAgTrsyOkM2Z/pbjkiAN/Jv1epYEBMIOyHeuSB3TCUc=; b=peTiw96tvDCj4Hf9WNZIdOMTre7Wh0zr+t0bRUkOUcUvMCw5/B2J067CwQfXrMNYw7U2nU ua/aJEDJZR+v8075/NoPgFZfQ28R7RFBCS1fmfa82Tg0++GzhFrWsAnnvgH/YgcUPOLGsfgu Rbaf5/321Tpoaa+uOLQZUDxF39zEk=; From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Benedikt Niedermayr Subject: [PATCH v4 2/5] arm64: dts: ti: iot2050: Drop unused ecap0 PWM Date: Sat, 4 Nov 2023 09:52:16 +0100 Message-Id: <6131d44e0505ca3efbb9039e5f2b637a3e139312.1699087938.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jan Kiszka In fact, this was never used by the final device, only dates back to first prototypes. Signed-off-by: Jan Kiszka --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index b849648d51f9..fc39ae0f9587 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -355,12 +355,6 @@ AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL = */ AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ >; }; - - ecap0_pins_default: ecap0-default-pins { - pinctrl-single,pins =3D < - AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ - >; - }; }; =20 &wkup_uart0 { @@ -557,12 +551,6 @@ &mcu_cpsw { status =3D "disabled"; }; =20 -&ecap0 { - status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&ecap0_pins_default>; -}; - &sdhci1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; --=20 2.35.3 From nobody Fri Dec 19 20:10:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4010C4332F for ; Sat, 4 Nov 2023 08:58:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230402AbjKDIwh (ORCPT ); Sat, 4 Nov 2023 04:52:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229576AbjKDIw3 (ORCPT ); Sat, 4 Nov 2023 04:52:29 -0400 Received: from mta-65-227.siemens.flowmailer.net (mta-65-227.siemens.flowmailer.net [185.136.65.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA661BC for ; Sat, 4 Nov 2023 01:52:22 -0700 (PDT) Received: by mta-65-227.siemens.flowmailer.net with ESMTPSA id 202311040852219d91b93b902f6cbb10 for ; Sat, 04 Nov 2023 09:52:21 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=mr9H5RhQ1S8dXd4gQnVb/qGHxNMEzjP6cXLbWdSNFG8=; b=hhsb+KTwzAucf/cX6hcSMnGqCWfg24bVCTyq2ii0/8etsAyWniBWDV8jXUY6DS9blUyuM5 K3pEsS9TjJQyuUJVRAWJbQZMweUNJV8UrBtm34qNI9xdQp/k75L2vnNeya24EEjUPI4SNNzi IFsQH2SJC1HRY12yeZ6UKUr9yicVY=; From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Benedikt Niedermayr Subject: [PATCH v4 3/5] arm64: dts: ti: iot2050: Definitions for runtime pinmuxing Date: Sat, 4 Nov 2023 09:52:17 +0100 Message-Id: <3f90f3e521758622aa9b10f030cf0de1e68e77a4.1699087938.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Benedikt Niedermayr Add multiple device tree nodes in order to support runtime pinmuxing via debugfs. All nodes are added to the pinctrl device node, since they are now belonging to multiple interfaces now. Note: Pinconf is also handled by debugfs-pinmux. This is possible since pinconf and pinmux accessing the same 32-Bit register and setting the function mask to 32-Bit allows writes to the whole register. Signed-off-by: Benedikt Niedermayr [Jan: fix node name style] Signed-off-by: Jan Kiszka --- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 663 +++++++++++++++++- .../dts/ti/k3-am6548-iot2050-advanced-m2.dts | 4 +- 2 files changed, 628 insertions(+), 39 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index fc39ae0f9587..41c980d2a242 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -114,6 +114,425 @@ dp_refclk: clock { }; =20 &wkup_pmx0 { + pinctrl-names =3D + "default", + "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown", + "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown", + "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown", + "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown", + "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown", + "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown", + "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown", + "d13-spi0-clk", "d13-gpio", "d13-gpio-pullup", "d13-gpio-pulldown", + "a0-gpio", "a0-gpio-pullup", "a0-gpio-pulldown", + "a1-gpio", "a1-gpio-pullup", "a1-gpio-pulldown", + "a2-gpio", "a2-gpio-pullup", "a2-gpio-pulldown", + "a3-gpio", "a3-gpio-pullup", "a3-gpio-pulldown", + "a4-gpio", "a4-gpio-pullup", "a4-gpio-pulldown", + "a5-gpio", "a5-gpio-pullup", "a5-gpio-pulldown"; + + pinctrl-0 =3D <&d0_uart0_rxd>; + pinctrl-1 =3D <&d0_uart0_rxd>; + pinctrl-2 =3D <&d0_gpio>; + pinctrl-3 =3D <&d0_gpio_pullup>; + pinctrl-4 =3D <&d0_gpio_pulldown>; + pinctrl-5 =3D <&d1_uart0_txd>; + pinctrl-6 =3D <&d1_gpio>; + pinctrl-7 =3D <&d1_gpio_pullup>; + pinctrl-8 =3D <&d1_gpio_pulldown>; + pinctrl-9 =3D <&d2_uart0_ctsn>; + pinctrl-10 =3D <&d2_gpio>; + pinctrl-11 =3D <&d2_gpio_pullup>; + pinctrl-12 =3D <&d2_gpio_pulldown>; + pinctrl-13 =3D <&d3_uart0_rtsn>; + pinctrl-14 =3D <&d3_gpio>; + pinctrl-15 =3D <&d3_gpio_pullup>; + pinctrl-16 =3D <&d3_gpio_pulldown>; + pinctrl-17 =3D <&d10_spi0_cs0>; + pinctrl-18 =3D <&d10_gpio>; + pinctrl-19 =3D <&d10_gpio_pullup>; + pinctrl-20 =3D <&d10_gpio_pulldown>; + pinctrl-21 =3D <&d11_spi0_d0>; + pinctrl-22 =3D <&d11_gpio>; + pinctrl-23 =3D <&d11_gpio_pullup>; + pinctrl-24 =3D <&d11_gpio_pulldown>; + pinctrl-25 =3D <&d12_spi0_d1>; + pinctrl-26 =3D <&d12_gpio>; + pinctrl-27 =3D <&d12_gpio_pullup>; + pinctrl-28 =3D <&d12_gpio_pulldown>; + pinctrl-29 =3D <&d13_spi0_clk>; + pinctrl-30 =3D <&d13_gpio>; + pinctrl-31 =3D <&d13_gpio_pullup>; + pinctrl-32 =3D <&d13_gpio_pulldown>; + pinctrl-33 =3D <&a0_gpio>; + pinctrl-34 =3D <&a0_gpio_pullup>; + pinctrl-35 =3D <&a0_gpio_pulldown>; + pinctrl-36 =3D <&a1_gpio>; + pinctrl-37 =3D <&a1_gpio_pullup>; + pinctrl-38 =3D <&a1_gpio_pulldown>; + pinctrl-39 =3D <&a2_gpio>; + pinctrl-40 =3D <&a2_gpio_pullup>; + pinctrl-41 =3D <&a2_gpio_pulldown>; + pinctrl-42 =3D <&a3_gpio>; + pinctrl-43 =3D <&a3_gpio_pullup>; + pinctrl-44 =3D <&a3_gpio_pulldown>; + pinctrl-45 =3D <&a4_gpio>; + pinctrl-46 =3D <&a4_gpio_pullup>; + pinctrl-47 =3D <&a4_gpio_pulldown>; + pinctrl-48 =3D <&a5_gpio>; + pinctrl-49 =3D <&a5_gpio_pullup>; + pinctrl-50 =3D <&a5_gpio_pulldown>; + + d0_uart0_rxd: d0-uart0-rxd-pins { + pinctrl-single,pins =3D < + /* (P4) MCU_UART0_RXD */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) + >; + }; + + d0_gpio: d0-gpio-pins { + pinctrl-single,pins =3D < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 7) + >; + }; + + d0_gpio_pullup: d0-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLUP, 7) + >; + }; + + d0_gpio_pulldown: d0-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (P4) WKUP_GPIO0_29 */ + AM65X_WKUP_IOPAD(0x0044, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d1_uart0_txd: d1-uart0-txd-pins { + pinctrl-single,pins =3D < + /* (P5) MCU_UART0_TXD */ + AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) + >; + }; + + d1_gpio: d1-gpio-pins { + pinctrl-single,pins =3D < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pullup: d1-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT, 7) + >; + }; + + d1_gpio_pulldown: d1-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (P5) WKUP_GPIO0_30 */ + AM65X_WKUP_IOPAD(0x0048, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d2_uart0_ctsn: d2-uart0-ctsn-pins { + pinctrl-single,pins =3D < + /* (P1) MCU_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) + >; + }; + + d2_gpio: d2-gpio-pins { + pinctrl-single,pins =3D < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pullup: d2-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 7) + >; + }; + + d2_gpio_pulldown: d2-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (P5) WKUP_GPIO0_31 */ + AM65X_WKUP_IOPAD(0x004C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d3_uart0_rtsn: d3-uart0-rtsn-pins { + pinctrl-single,pins =3D < + /* (N3) MCU_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) + >; + }; + + d3_gpio: d3-gpio-pins { + pinctrl-single,pins =3D < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pullup: d3-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + d3_gpio_pulldown: d3-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (N3) WKUP_GPIO0_33 */ + AM65X_WKUP_IOPAD(0x0054, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d10_spi0_cs0: d10-spi0-cs0-pins { + pinctrl-single,pins =3D < + /* (Y4) MCU_SPI0_CS0 */ + AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) + >; + }; + + d10_gpio: d10-gpio-pins { + pinctrl-single,pins =3D < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pullup: d10-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT, 7) + >; + }; + + d10_gpio_pulldown: d10-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (Y4) WKUP_GPIO0_51 */ + AM65X_WKUP_IOPAD(0x009c, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d11_spi0_d0: d11-spi0-d0-pins { + pinctrl-single,pins =3D < + /* (Y3) MCU_SPI0_D0 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) + >; + }; + + d11_gpio: d11-gpio-pins { + pinctrl-single,pins =3D < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pullup: d11-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 7) + >; + }; + + d11_gpio_pulldown: d11-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (Y3) WKUP_GPIO0_49 */ + AM65X_WKUP_IOPAD(0x0094, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d12_spi0_d1: d12-spi0-d1-pins { + pinctrl-single,pins =3D < + /* (Y2) MCU_SPI0_D1 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) + >; + }; + + d12_gpio: d12-gpio-pins { + pinctrl-single,pins =3D < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pullup: d12-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d12_gpio_pulldown: d12-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (Y2) WKUP_GPIO0_50 */ + AM65X_WKUP_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d13_spi0_clk: d13-spi0-clk-pins { + pinctrl-single,pins =3D < + /* (Y1) MCU_SPI0_CLK */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) + >; + }; + + d13_gpio: d13-gpio-pins { + pinctrl-single,pins =3D < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pullup: d13-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 7) + >; + }; + + d13_gpio_pulldown: d13-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (Y1) WKUP_GPIO0_48 */ + AM65X_WKUP_IOPAD(0x0090, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a0_gpio: a0-gpio-pins { + pinctrl-single,pins =3D < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pullup: a0-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + a0_gpio_pulldown: a0-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (L6) WKUP_GPIO0_45 */ + AM65X_WKUP_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a1_gpio: a1-gpio-pins { + pinctrl-single,pins =3D < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pullup: a1-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 7) + >; + }; + + a1_gpio_pulldown: a1-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (M6) WKUP_GPIO0_44 */ + AM65X_WKUP_IOPAD(0x0080, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a2_gpio: a2-gpio-pins { + pinctrl-single,pins =3D < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pullup: a2-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT, 7) + >; + }; + + a2_gpio_pulldown: a2-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (L5) WKUP_GPIO0_43 */ + AM65X_WKUP_IOPAD(0x007C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a3_gpio: a3-gpio-pins { + pinctrl-single,pins =3D < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pullup: a3-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT, 7) + >; + }; + + a3_gpio_pulldown: a3-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (M5) WKUP_GPIO0_39 */ + AM65X_WKUP_IOPAD(0x006C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a4_gpio: a4-gpio-pins { + pinctrl-single,pins =3D < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pullup: a4-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 7) + >; + }; + + a4_gpio_pulldown: a4-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (L2) WKUP_GPIO0_42 */ + AM65X_WKUP_IOPAD(0x0078, PIN_INPUT_PULLDOWN, 7) + >; + }; + + a5_gpio: a5-gpio-pins { + pinctrl-single,pins =3D < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT, 7) + >; + }; + + a5_gpio_pullup: a5-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLUP, 7) + >; + }; + + a5_gpio_pulldown: a5-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (N5) WKUP_GPIO0_35 */ + AM65X_WKUP_IOPAD(0x005C, PIN_INPUT_PULLDOWN, 7) + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-default-pins { pinctrl-single,pins =3D < /* (AC7) WKUP_I2C0_SCL */ @@ -146,23 +565,6 @@ AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) >; }; =20 - arduino_uart_pins_default: arduino-uart-default-pins { - pinctrl-single,pins =3D < - /* (P4) MCU_UART0_RXD */ - AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) - /* (P5) MCU_UART0_TXD */ - AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) - >; - }; - - arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-default-pins { - pinctrl-single,pins =3D < - /* (P1) WKUP_GPIO0_31 */ - AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7) - /* (N3) WKUP_GPIO0_33 */ - AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7) - >; - }; =20 arduino_io_oe_pins_default: arduino-io-oe-default-pins { pinctrl-single,pins =3D < @@ -242,6 +644,214 @@ AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7) }; =20 &main_pmx0 { + pinctrl-names =3D + "default", + "d4-ehrpwm0-a", "d4-gpio", "d4-gpio-pullup", "d4-gpio-pulldown", + "d5-ehrpwm1-a", "d5-gpio", "d5-gpio-pullup", "d5-gpio-pulldown", + "d6-ehrpwm2-a", "d6-gpio", "d6-gpio-pullup", "d6-gpio-pulldown", + "d7-ehrpwm3-a", "d7-gpio", "d7-gpio-pullup", "d7-gpio-pulldown", + "d8-ehrpwm4-a", "d8-gpio", "d8-gpio-pullup", "d8-gpio-pulldown", + "d9-ehrpwm5-a", "d9-gpio", "d9-gpio-pullup", "d9-gpio-pulldown"; + + pinctrl-0 =3D <&d4_ehrpwm0_a>; + pinctrl-1 =3D <&d4_ehrpwm0_a>; + pinctrl-2 =3D <&d4_gpio>; + pinctrl-3 =3D <&d4_gpio_pullup>; + pinctrl-4 =3D <&d4_gpio_pulldown>; + + pinctrl-5 =3D <&d5_ehrpwm1_a>; + pinctrl-6 =3D <&d5_gpio>; + pinctrl-7 =3D <&d5_gpio_pullup>; + pinctrl-8 =3D <&d5_gpio_pulldown>; + + pinctrl-9 =3D <&d6_ehrpwm2_a>; + pinctrl-10 =3D <&d6_gpio>; + pinctrl-11 =3D <&d6_gpio_pullup>; + pinctrl-12 =3D <&d6_gpio_pulldown>; + + pinctrl-13 =3D <&d7_ehrpwm3_a>; + pinctrl-14 =3D <&d7_gpio>; + pinctrl-15 =3D <&d7_gpio_pullup>; + pinctrl-16 =3D <&d7_gpio_pulldown>; + + pinctrl-17 =3D <&d8_ehrpwm4_a>; + pinctrl-18 =3D <&d8_gpio>; + pinctrl-19 =3D <&d8_gpio_pullup>; + pinctrl-20 =3D <&d8_gpio_pulldown>; + + pinctrl-21 =3D <&d9_ehrpwm5_a>; + pinctrl-22 =3D <&d9_gpio>; + pinctrl-23 =3D <&d9_gpio_pullup>; + pinctrl-24 =3D <&d9_gpio_pulldown>; + + d4_ehrpwm0_a: d4-ehrpwm0-a-pins { + pinctrl-single,pins =3D < + /* (AG18) EHRPWM0_A */ + AM65X_IOPAD(0x0084, PIN_OUTPUT, 5) + >; + }; + + d4_gpio: d4-gpio-pins { + pinctrl-single,pins =3D < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT, 7) + >; + }; + + d4_gpio_pullup: d4-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLUP, 7) + >; + }; + + d4_gpio_pulldown: d4-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (AG18) GPIO0_33 */ + AM65X_IOPAD(0x0084, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d5_ehrpwm1_a: d5-ehrpwm1-a-pins { + pinctrl-single,pins =3D < + /* (AF17) EHRPWM1_A */ + AM65X_IOPAD(0x008C, PIN_OUTPUT, 5) + >; + }; + + d5_gpio: d5-gpio-pins { + pinctrl-single,pins =3D < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT, 7) + >; + }; + + d5_gpio_pullup: d5-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLUP, 7) + >; + }; + + d5_gpio_pulldown: d5-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (AF17) GPIO0_35 */ + AM65X_IOPAD(0x008C, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d6_ehrpwm2_a: d6-ehrpwm2-a-pins { + pinctrl-single,pins =3D < + /* (AH16) EHRPWM2_A */ + AM65X_IOPAD(0x0098, PIN_OUTPUT, 5) + >; + }; + + d6_gpio: d6-gpio-pins { + pinctrl-single,pins =3D < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT, 7) + >; + }; + + d6_gpio_pullup: d6-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLUP, 7) + >; + }; + + d6_gpio_pulldown: d6-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (AH16) GPIO0_38 */ + AM65X_IOPAD(0x0098, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d7_ehrpwm3_a: d7-ehrpwm3-a-pins { + pinctrl-single,pins =3D < + /* (AH15) EHRPWM3_A */ + AM65X_IOPAD(0x00AC, PIN_OUTPUT, 5) + >; + }; + + d7_gpio: d7-gpio-pins { + pinctrl-single,pins =3D < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT, 7) + >; + }; + + d7_gpio_pullup: d7-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLUP, 7) + >; + }; + + d7_gpio_pulldown: d7-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (AH15) GPIO0_43 */ + AM65X_IOPAD(0x00AC, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d8_ehrpwm4_a: d8-ehrpwm4-a-pins { + pinctrl-single,pins =3D < + /* (AG15) EHRPWM4_A */ + AM65X_IOPAD(0x00C0, PIN_OUTPUT, 5) + >; + }; + + d8_gpio: d8-gpio-pins { + pinctrl-single,pins =3D < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT, 7) + >; + }; + + d8_gpio_pullup: d8-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLUP, 7) + >; + }; + + d8_gpio_pulldown: d8-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (AG15) GPIO0_48 */ + AM65X_IOPAD(0x00C0, PIN_INPUT_PULLDOWN, 7) + >; + }; + + d9_ehrpwm5_a: d9-ehrpwm5-a-pins { + pinctrl-single,pins =3D < + /* (AD15) EHRPWM5_A */ + AM65X_IOPAD(0x00CC, PIN_OUTPUT, 5) + >; + }; + + d9_gpio: d9-gpio-pins { + pinctrl-single,pins =3D < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT, 7) + >; + }; + + d9_gpio_pullup: d9-gpio-pullup-pins { + pinctrl-single,pins =3D < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLUP, 7) + >; + }; + + d9_gpio_pulldown: d9-gpio-pulldown-pins { + pinctrl-single,pins =3D < + /* (AD15) GPIO0_51 */ + AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins =3D < AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ @@ -283,17 +893,6 @@ AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVV= BUS */ >; }; =20 - arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-default-pins { - pinctrl-single,pins =3D < - AM65X_IOPAD(0x0084, PIN_OUTPUT, 7) /* (AG18) GPIO0_33 */ - AM65X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (AF17) GPIO0_35 */ - AM65X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (AH16) GPIO0_38 */ - AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7) /* (AH15) GPIO0_43 */ - AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (AG15) GPIO0_48 */ - AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7) /* (AD15) GPIO0_51 */ - >; - }; - dss_vout1_pins_default: dss-vout1-default-pins { pinctrl-single,pins =3D < AM65X_IOPAD(0x0000, PIN_OUTPUT, 1) /* VOUT1_DATA0 */ @@ -370,13 +969,9 @@ &main_uart1 { =20 &mcu_uart0 { status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&arduino_uart_pins_default>; }; =20 &main_gpio0 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&arduino_io_d4_to_d9_pins_default>; gpio-line-names =3D "main_gpio0-base", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", @@ -389,7 +984,6 @@ &main_gpio0 { &wkup_gpio0 { pinctrl-names =3D "default"; pinctrl-0 =3D - <&arduino_io_d2_to_d3_pins_default>, <&arduino_i2c_aio_switch_pins_default>, <&arduino_io_oe_pins_default>, <&push_button_pins_default>, @@ -572,9 +1166,6 @@ &usb1 { =20 &mcu_spi0 { status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&mcu_spi0_pins_default>; - #address-cells =3D <1>; #size-cells =3D <0>; ti,pindir-d0-out-d1-in; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arc= h/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 774eb14ac907..8301c35c31b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -66,9 +66,7 @@ AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_= 89 */ =20 &main_gpio0 { pinctrl-names =3D "default"; - pinctrl-0 =3D - <&main_m2_pcie_mux_control>, - <&arduino_io_d4_to_d9_pins_default>; + pinctrl-0 =3D <&main_m2_pcie_mux_control>; }; =20 &main_gpio1 { --=20 2.35.3 From nobody Fri Dec 19 20:10:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B706C4167B for ; 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From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Benedikt Niedermayr Subject: [PATCH v4 4/5] arm64: dts: ti: iot2050: Refactor the m.2 and minipcie power pin Date: Sat, 4 Nov 2023 09:52:18 +0100 Message-Id: <8b2f8c1698421b8d0694eb337ad7ea2320d76aa6.1699087938.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Su Bao Cheng Make the m.2 power control pin also available on miniPCIE variants. This can fix some miniPCIE card hang issue, by forcing a power on reset during boot. Signed-off-by: Baocheng Su Signed-off-by: Jan Kiszka --- .../arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi | 4 +++- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 11 +++++++++++ .../boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts | 8 +------- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/= arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi index e9419c4fe605..e9b57b87e42e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi @@ -20,7 +20,9 @@ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) =20 &main_gpio1 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&cp2102n_reset_pin_default>; + pinctrl-0 =3D + <&main_pcie_enable_pins_default>, + <&cp2102n_reset_pin_default>; gpio-line-names =3D "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 41c980d2a242..d2b6439cf496 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -852,6 +852,12 @@ AM65X_IOPAD(0x00CC, PIN_INPUT_PULLDOWN, 7) >; }; =20 + main_pcie_enable_pins_default: main-pcie-enable-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ + >; + }; + main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins =3D < AM65X_IOPAD(0x0174, PIN_INPUT, 6) /* (AE23) UART1_RXD */ @@ -981,6 +987,11 @@ &main_gpio0 { "", "IO9"; }; =20 +&main_gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_pcie_enable_pins_default>; +}; + &wkup_gpio0 { pinctrl-names =3D "default"; pinctrl-0 =3D diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arc= h/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index 8301c35c31b3..bd6f2e696e94 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -27,12 +27,6 @@ &mcu_r5fss0 { }; =20 &main_pmx0 { - main_m2_enable_pins_default: main-m2-enable-default-pins { - pinctrl-single,pins =3D < - AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ - >; - }; - main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins =3D < AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ @@ -72,7 +66,7 @@ &main_gpio0 { &main_gpio1 { pinctrl-names =3D "default"; pinctrl-0 =3D - <&main_m2_enable_pins_default>, + <&main_pcie_enable_pins_default>, <&main_pmx0_m2_config_pins_default>, <&main_pmx1_m2_config_pins_default>, <&cp2102n_reset_pin_default>; --=20 2.35.3 From nobody Fri Dec 19 20:10:28 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4ABBC4167D for ; Sat, 4 Nov 2023 08:53:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230123AbjKDIwf (ORCPT ); Sat, 4 Nov 2023 04:52:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbjKDIw2 (ORCPT ); Sat, 4 Nov 2023 04:52:28 -0400 Received: from mta-64-227.siemens.flowmailer.net (mta-64-227.siemens.flowmailer.net [185.136.64.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94A49D51 for ; Sat, 4 Nov 2023 01:52:24 -0700 (PDT) Received: by mta-64-227.siemens.flowmailer.net with ESMTPSA id 2023110408522202c210bd1c6543127d for ; Sat, 04 Nov 2023 09:52:22 +0100 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm1; d=siemens.com; i=jan.kiszka@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc:References:In-Reply-To; bh=ywFwNboZZKYcNPO0K9ZuTF1g7+TmpkPYE9IXZevrQiw=; b=A2kDYOYqp3QkQekYaqwZ3n7pImD3cnIgFYxxC/Jua/2QVjCg+KgRtKtXGjGTG5bPsa4654 fTaN6zCU4DI1EEVAowAdhBeacPybGg2lmjkLZhEc2sdDb+kJdUV456TFCSWyIjWHQGDW/HwJ FibktR3+/tRRgIzitGEuUdEaci0hE=; From: Jan Kiszka To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Bao Cheng Su , Benedikt Niedermayr Subject: [PATCH v4 5/5] arm64: dts: ti: iot2050: Add icssg-prueth nodes for PG2 devices Date: Sat, 4 Nov 2023 09:52:19 +0100 Message-Id: <565d31a5fd29c4dd0cf28e347049a1247a6e446c.1699087938.git.jan.kiszka@siemens.com> In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-294854:519-21489:flowmailer Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Jan Kiszka Add the required nodes to enable ICSSG SR2.0 based prueth networking. As the driver still needs to be extended for SR1.0 support, keep related nodes disabled on PG1 devices. Signed-off-by: Jan Kiszka --- .../dts/ti/k3-am65-iot2050-common-pg1.dtsi | 10 +- .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 128 ++++++++++++++++++ 2 files changed, 137 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi b/arch/= arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi index 51f902fa35a7..1d1979859583 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) Siemens AG, 2021 + * Copyright (c) Siemens AG, 2021-2023 * * Authors: * Jan Kiszka @@ -44,3 +44,11 @@ &tx_pru2_0 { &tx_pru2_1 { status =3D "disabled"; }; + +&icssg0_eth { + status =3D "disabled"; +}; + +&icssg0_mdio { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index d2b6439cf496..ab1dffa5c1c6 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -11,6 +11,7 @@ =20 #include "k3-am654.dtsi" #include +#include =20 / { aliases { @@ -27,6 +28,8 @@ aliases { spi0 =3D &mcu_spi0; mmc0 =3D &sdhci1; mmc1 =3D &sdhci0; + ethernet1 =3D &icssg0_emac0; + ethernet2 =3D &icssg0_emac1; }; =20 chosen { @@ -111,6 +114,76 @@ dp_refclk: clock { #clock-cells =3D <0>; clock-frequency =3D <19200000>; }; + + /* Dual Ethernet application node on PRU-ICSSG0 */ + icssg0_eth: icssg0-eth { + compatible =3D "ti,am654-icssg-prueth"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_rgmii_pins_default>; + sram =3D <&msmc_ram>; + + ti,prus =3D <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, + <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>; + firmware-name =3D "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", + "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", + "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", + "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf"; + + ti,pruss-gp-mux-sel =3D <2>, /* MII mode */ + <2>, + <2>, + <2>, /* MII mode */ + <2>, + <2>; + + ti,mii-g-rt =3D <&icssg0_mii_g_rt>; + ti,mii-rt =3D <&icssg0_mii_rt>; + ti,iep =3D <&icssg0_iep0>, <&icssg0_iep1>; + + interrupt-parent =3D <&icssg0_intc>; + interrupts =3D <24 0 2>, <25 1 3>; + interrupt-names =3D "tx_ts0", "tx_ts1"; + + dmas =3D <&main_udmap 0xc100>, /* egress slice 0 */ + <&main_udmap 0xc101>, /* egress slice 0 */ + <&main_udmap 0xc102>, /* egress slice 0 */ + <&main_udmap 0xc103>, /* egress slice 0 */ + <&main_udmap 0xc104>, /* egress slice 1 */ + <&main_udmap 0xc105>, /* egress slice 1 */ + <&main_udmap 0xc106>, /* egress slice 1 */ + <&main_udmap 0xc107>, /* egress slice 1 */ + <&main_udmap 0x4100>, /* ingress slice 0 */ + <&main_udmap 0x4101>; /* ingress slice 1 */ + dma-names =3D "tx0-0", "tx0-1", "tx0-2", "tx0-3", + "tx1-0", "tx1-1", "tx1-2", "tx1-3", + "rx0", "rx1"; + + ethernet-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + icssg0_emac0: port@0 { + reg =3D <0>; + phy-handle =3D <&icssg0_eth0_phy>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4100>; + ti,half-duplex-capable; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + + icssg0_emac1: port@1 { + reg =3D <1>; + phy-handle =3D <&icssg0_eth1_phy>; + phy-mode =3D "rgmii-id"; + ti,syscon-rgmii-delay =3D <&scm_conf 0x4104>; + ti,half-duplex-capable; + /* Filled in by bootloader */ + local-mac-address =3D [00 00 00 00 00 00]; + }; + }; + }; }; =20 &wkup_pmx0 { @@ -944,6 +1017,43 @@ AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL= */ AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */ >; }; + + icssg0_mdio_pins_default: icssg0-mdio-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */ + AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */ + >; + }; + + icssg0_rgmii_pins_default: icssg0-rgmii-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_= RD0 */ + AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_= RD1 */ + AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_= RD2 */ + AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_= RD3 */ + AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII= 2_TD0 */ + AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII= 2_TD1 */ + AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII= 2_TD2 */ + AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII= 2_TD3 */ + AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2= _TXC */ + AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII= 2_TX_CTL */ + AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_= RXC */ + AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_= RX_CTL */ + + AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_R= D0 */ + AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_R= D1 */ + AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_R= D2 */ + AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_= RD3 */ + AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII= 1_TD0 */ + AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII= 1_TD1 */ + AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII= 1_TD2 */ + AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII= 1_TD3 */ + AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1= _TXC */ + AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII= 1_TX_CTL */ + AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_R= XC */ + AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_R= X_CTL */ + >; + }; }; =20 &main_pmx1 { @@ -1316,3 +1426,21 @@ &mcu_r5fss0_core1 { <&mcu_r5fss0_core1_memory_region>; mboxes =3D <&mailbox0_cluster1>, <&mbox_mcu_r5fss0_core1>; }; + +&icssg0_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&icssg0_mdio_pins_default>; + + icssg0_eth0_phy: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; + + icssg0_eth1_phy: ethernet-phy@1 { + reg =3D <1>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + }; +}; --=20 2.35.3