From nobody Thu Dec 18 05:16:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E505CDB47E for ; Wed, 18 Oct 2023 19:46:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231154AbjJRTqN (ORCPT ); Wed, 18 Oct 2023 15:46:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229695AbjJRTqK (ORCPT ); Wed, 18 Oct 2023 15:46:10 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60915B8; Wed, 18 Oct 2023 12:46:06 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1c9bca1d96cso50271755ad.3; Wed, 18 Oct 2023 12:46:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697658366; x=1698263166; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=QrkT+IAn+2hPywlhHEXybKgnC1gq9qhiBL1kaUboifs=; b=SjoT6WnxI72KtBOjPhwjH8PbIyAxHgi+uKFrJBo9fwXatgsuS0ZEJlLm88KacwfBxR 6r1JGtd+nqI/mhug4UHH2EM8TNdyfbuimi3SnXNhJjjKMmeTBN8ycss74+S6sIiAsyO8 mJ8ApjR5e/dVOGLcyNIvsgm+ApMzQ+UFHXW/xxTpelb6MSjj5fauCAvjVJcgUVNSnrvw 2vKs+FzEniNH/LadtYImqxdDDQ52sl5sagrnvVHS9K22pwJM+0mN+FhL0LyyS3n6RCzp HSPbCExa02pWiZCjZHSXuKh7EX5+nflzZIksFOoB7LEdPcw+tN0u6QxZhFEinWbVluSM 4EJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697658366; x=1698263166; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=QrkT+IAn+2hPywlhHEXybKgnC1gq9qhiBL1kaUboifs=; b=Su8qlvdsP4zKvGQK3BF3G5MzH1r86SZNoimSjEYoWYQKSE67qitVsYJ+imCubbxEE/ +yf5IvOK7ZiOmP1s/atcDxnSzNIx36/K2RA/WMIU0UHsHusqTwEWZe9h5sUYV9FAjBew 2qbS0RAHPlTQp9x7QxJu0ZX5egxRVlktUZJdrgJvhH+MwmRB83a0yxPPDV/gq3pSW6JG 3XAzsXxonMWf3oqofHHK1Gszw0HjKLmm0Pg1RJnuv48qESfo72LCp0Dandb4ZklaE8/X SyE85GdxCxhs7swuASswZHoOi3AqA21Q1fbximbgxY+HPd7gYGksjlFBggD6DTFnMMvx 6aIg== X-Gm-Message-State: AOJu0Yy3FriIxp0ZVAPuK2YIhufyVrpDK0dRgS9YoLNfW7MDAMRqw5XK jYShCXhk3F/fmAjf/v6z13U= X-Google-Smtp-Source: AGHT+IEkYVcloFJbYYIkwAPrvghyus4I1mdGuBMb0bet8nBYtxMJXXDojvlqdE1QUHNUaFACa3azcA== X-Received: by 2002:a17:902:d483:b0:1c8:9a60:387f with SMTP id c3-20020a170902d48300b001c89a60387fmr338232plg.56.1697658365617; Wed, 18 Oct 2023 12:46:05 -0700 (PDT) Received: from ubuntu ([223.226.54.200]) by smtp.gmail.com with ESMTPSA id jm17-20020a17090304d100b001c9dac0fbbasm319958plb.63.2023.10.18.12.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 12:46:04 -0700 (PDT) Date: Wed, 18 Oct 2023 12:46:00 -0700 From: Nandha Kumar Singaram To: Manish Chopra , GR-Linux-NIC-Dev@marvell.com, Coiby Xu , Greg Kroah-Hartman , netdev@vger.kernel.org, linux-staging@lists.linux.dev, linux-kernel@vger.kernel.org Cc: kumaran.4353@gmail.com Subject: [PATCH v2 1/2] staging: qlge: Fix coding style in qlge.h Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace all occurrnces of (1< Reviewed-by: Simon Horman --- drivers/staging/qlge/qlge.h | 388 ++++++++++++++++++------------------ 1 file changed, 194 insertions(+), 194 deletions(-) diff --git a/drivers/staging/qlge/qlge.h b/drivers/staging/qlge/qlge.h index 69c5b332fd7c..dcf5187b9ccc 100644 --- a/drivers/staging/qlge/qlge.h +++ b/drivers/staging/qlge/qlge.h @@ -96,16 +96,16 @@ enum { MPI_TEST_FUNC_RST_STS =3D 0x100a, MPI_TEST_FUNC_RST_FRC =3D 0x00000003, MPI_TEST_NIC_FUNC_MASK =3D 0x00000007, - MPI_TEST_NIC1_FUNCTION_ENABLE =3D (1 << 0), + MPI_TEST_NIC1_FUNCTION_ENABLE =3D BIT(0), MPI_TEST_NIC1_FUNCTION_MASK =3D 0x0000000e, MPI_TEST_NIC1_FUNC_SHIFT =3D 1, - MPI_TEST_NIC2_FUNCTION_ENABLE =3D (1 << 4), + MPI_TEST_NIC2_FUNCTION_ENABLE =3D BIT(4), MPI_TEST_NIC2_FUNCTION_MASK =3D 0x000000e0, MPI_TEST_NIC2_FUNC_SHIFT =3D 5, - MPI_TEST_FC1_FUNCTION_ENABLE =3D (1 << 8), + MPI_TEST_FC1_FUNCTION_ENABLE =3D BIT(8), MPI_TEST_FC1_FUNCTION_MASK =3D 0x00000e00, MPI_TEST_FC1_FUNCTION_SHIFT =3D 9, - MPI_TEST_FC2_FUNCTION_ENABLE =3D (1 << 12), + MPI_TEST_FC2_FUNCTION_ENABLE =3D BIT(12), MPI_TEST_FC2_FUNCTION_MASK =3D 0x0000e000, MPI_TEST_FC2_FUNCTION_SHIFT =3D 13, =20 @@ -122,10 +122,10 @@ enum { MAILBOX_COUNT =3D 16, MAILBOX_TIMEOUT =3D 5, =20 - PROC_ADDR_RDY =3D (1 << 31), - PROC_ADDR_R =3D (1 << 30), - PROC_ADDR_ERR =3D (1 << 29), - PROC_ADDR_DA =3D (1 << 28), + PROC_ADDR_RDY =3D BIT(31), + PROC_ADDR_R =3D BIT(30), + PROC_ADDR_ERR =3D BIT(29), + PROC_ADDR_DA =3D BIT(28), PROC_ADDR_FUNC0_MBI =3D 0x00001180, PROC_ADDR_FUNC0_MBO =3D (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT), PROC_ADDR_FUNC0_CTL =3D 0x000011a1, @@ -142,33 +142,33 @@ enum { * System Register (SYS) bit definitions. */ enum { - SYS_EFE =3D (1 << 0), - SYS_FAE =3D (1 << 1), - SYS_MDC =3D (1 << 2), - SYS_DST =3D (1 << 3), - SYS_DWC =3D (1 << 4), - SYS_EVW =3D (1 << 5), + SYS_EFE =3D BIT(0), + SYS_FAE =3D BIT(1), + SYS_MDC =3D BIT(2), + SYS_DST =3D BIT(3), + SYS_DWC =3D BIT(4), + SYS_EVW =3D BIT(5), SYS_OMP_DLY_MASK =3D 0x3f000000, /* * There are no values defined as of edit #15. */ - SYS_ODI =3D (1 << 14), + SYS_ODI =3D BIT(14), }; =20 /* * Reset/Failover Register (RST_FO) bit definitions. */ enum { - RST_FO_TFO =3D (1 << 0), + RST_FO_TFO =3D BIT(0), RST_FO_RR_MASK =3D 0x00060000, RST_FO_RR_CQ_CAM =3D 0x00000000, RST_FO_RR_DROP =3D 0x00000002, RST_FO_RR_DQ =3D 0x00000004, RST_FO_RR_RCV_FUNC_CQ =3D 0x00000006, - RST_FO_FRB =3D (1 << 12), - RST_FO_MOP =3D (1 << 13), - RST_FO_REG =3D (1 << 14), - RST_FO_FR =3D (1 << 15), + RST_FO_FRB =3D BIT(12), + RST_FO_MOP =3D BIT(13), + RST_FO_REG =3D BIT(14), + RST_FO_FR =3D BIT(15), }; =20 /* @@ -185,19 +185,19 @@ enum { FSC_DBL_MAX_PLD =3D 0x00000008, FSC_DBL_MAX_BRST =3D 0x00000010, FSC_DBL_128_BYTES =3D 0x00000018, - FSC_EC =3D (1 << 5), + FSC_EC =3D BIT(5), FSC_EPC_MASK =3D 0x00c00000, - FSC_EPC_INBOUND =3D (1 << 6), - FSC_EPC_OUTBOUND =3D (1 << 7), + FSC_EPC_INBOUND =3D BIT(6), + FSC_EPC_OUTBOUND =3D BIT(7), FSC_VM_PAGESIZE_MASK =3D 0x07000000, FSC_VM_PAGE_2K =3D 0x00000100, FSC_VM_PAGE_4K =3D 0x00000200, FSC_VM_PAGE_8K =3D 0x00000300, FSC_VM_PAGE_64K =3D 0x00000600, - FSC_SH =3D (1 << 11), - FSC_DSB =3D (1 << 12), - FSC_STE =3D (1 << 13), - FSC_FE =3D (1 << 15), + FSC_SH =3D BIT(11), + FSC_DSB =3D BIT(12), + FSC_STE =3D BIT(13), + FSC_FE =3D BIT(15), }; =20 /* @@ -208,9 +208,9 @@ enum { /* * There are no valued defined as of edit #15. */ - CSR_RR =3D (1 << 8), - CSR_HRI =3D (1 << 9), - CSR_RP =3D (1 << 10), + CSR_RR =3D BIT(8), + CSR_HRI =3D BIT(9), + CSR_RP =3D BIT(10), CSR_CMD_PARM_SHIFT =3D 22, CSR_CMD_NOP =3D 0x00000000, CSR_CMD_SET_RST =3D 0x10000000, @@ -229,13 +229,13 @@ enum { * Configuration Register (CFG) bit definitions. */ enum { - CFG_LRQ =3D (1 << 0), - CFG_DRQ =3D (1 << 1), - CFG_LR =3D (1 << 2), - CFG_DR =3D (1 << 3), - CFG_LE =3D (1 << 5), - CFG_LCQ =3D (1 << 6), - CFG_DCQ =3D (1 << 7), + CFG_LRQ =3D BIT(0), + CFG_DRQ =3D BIT(1), + CFG_LR =3D BIT(2), + CFG_DR =3D BIT(3), + CFG_LE =3D BIT(5), + CFG_LCQ =3D BIT(6), + CFG_DCQ =3D BIT(7), CFG_Q_SHIFT =3D 8, CFG_Q_MASK =3D 0x7f000000, }; @@ -244,19 +244,19 @@ enum { * Status Register (STS) bit definitions. */ enum { - STS_FE =3D (1 << 0), - STS_PI =3D (1 << 1), - STS_PL0 =3D (1 << 2), - STS_PL1 =3D (1 << 3), - STS_PI0 =3D (1 << 4), - STS_PI1 =3D (1 << 5), + STS_FE =3D BIT(0), + STS_PI =3D BIT(1), + STS_PL0 =3D BIT(2), + STS_PL1 =3D BIT(3), + STS_PI0 =3D BIT(4), + STS_PI1 =3D BIT(5), STS_FUNC_ID_MASK =3D 0x000000c0, STS_FUNC_ID_SHIFT =3D 6, - STS_F0E =3D (1 << 8), - STS_F1E =3D (1 << 9), - STS_F2E =3D (1 << 10), - STS_F3E =3D (1 << 11), - STS_NFE =3D (1 << 12), + STS_F0E =3D BIT(8), + STS_F1E =3D BIT(9), + STS_F2E =3D BIT(10), + STS_F3E =3D BIT(11), + STS_NFE =3D BIT(12), }; =20 /* @@ -268,24 +268,24 @@ enum { INTR_EN_TYPE_ENABLE =3D 0x00000100, INTR_EN_TYPE_DISABLE =3D 0x00000200, INTR_EN_TYPE_READ =3D 0x00000300, - INTR_EN_IHD =3D (1 << 13), + INTR_EN_IHD =3D BIT(13), INTR_EN_IHD_MASK =3D (INTR_EN_IHD << 16), - INTR_EN_EI =3D (1 << 14), - INTR_EN_EN =3D (1 << 15), + INTR_EN_EI =3D BIT(14), + INTR_EN_EN =3D BIT(15), }; =20 /* * Interrupt Mask Register (INTR_MASK) bit definitions. */ enum { - INTR_MASK_PI =3D (1 << 0), - INTR_MASK_HL0 =3D (1 << 1), - INTR_MASK_LH0 =3D (1 << 2), - INTR_MASK_HL1 =3D (1 << 3), - INTR_MASK_LH1 =3D (1 << 4), - INTR_MASK_SE =3D (1 << 5), - INTR_MASK_LSC =3D (1 << 6), - INTR_MASK_MC =3D (1 << 7), + INTR_MASK_PI =3D BIT(0), + INTR_MASK_HL0 =3D BIT(1), + INTR_MASK_LH0 =3D BIT(2), + INTR_MASK_HL1 =3D BIT(3), + INTR_MASK_LH1 =3D BIT(4), + INTR_MASK_SE =3D BIT(5), + INTR_MASK_LSC =3D BIT(6), + INTR_MASK_MC =3D BIT(7), INTR_MASK_LINK_IRQS =3D INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC, }; =20 @@ -305,38 +305,38 @@ enum { * Force ECC Error Register (FRC_ECC_ERR) bit definitions. */ enum { - FRC_ECC_ERR_VW =3D (1 << 12), - FRC_ECC_ERR_VB =3D (1 << 13), - FRC_ECC_ERR_NI =3D (1 << 14), - FRC_ECC_ERR_NO =3D (1 << 15), + FRC_ECC_ERR_VW =3D BIT(12), + FRC_ECC_ERR_VB =3D BIT(13), + FRC_ECC_ERR_NI =3D BIT(14), + FRC_ECC_ERR_NO =3D BIT(15), FRC_ECC_PFE_SHIFT =3D 16, - FRC_ECC_ERR_DO =3D (1 << 18), - FRC_ECC_P14 =3D (1 << 19), + FRC_ECC_ERR_DO =3D BIT(18), + FRC_ECC_P14 =3D BIT(19), }; =20 /* * Error Status Register (ERR_STS) bit definitions. */ enum { - ERR_STS_NOF =3D (1 << 0), - ERR_STS_NIF =3D (1 << 1), - ERR_STS_DRP =3D (1 << 2), - ERR_STS_XGP =3D (1 << 3), - ERR_STS_FOU =3D (1 << 4), - ERR_STS_FOC =3D (1 << 5), - ERR_STS_FOF =3D (1 << 6), - ERR_STS_FIU =3D (1 << 7), - ERR_STS_FIC =3D (1 << 8), - ERR_STS_FIF =3D (1 << 9), - ERR_STS_MOF =3D (1 << 10), - ERR_STS_TA =3D (1 << 11), - ERR_STS_MA =3D (1 << 12), - ERR_STS_MPE =3D (1 << 13), - ERR_STS_SCE =3D (1 << 14), - ERR_STS_STE =3D (1 << 15), - ERR_STS_FOW =3D (1 << 16), - ERR_STS_UE =3D (1 << 17), - ERR_STS_MCH =3D (1 << 26), + ERR_STS_NOF =3D BIT(0), + ERR_STS_NIF =3D BIT(1), + ERR_STS_DRP =3D BIT(2), + ERR_STS_XGP =3D BIT(3), + ERR_STS_FOU =3D BIT(4), + ERR_STS_FOC =3D BIT(5), + ERR_STS_FOF =3D BIT(6), + ERR_STS_FIU =3D BIT(7), + ERR_STS_FIC =3D BIT(8), + ERR_STS_FIF =3D BIT(9), + ERR_STS_MOF =3D BIT(10), + ERR_STS_TA =3D BIT(11), + ERR_STS_MA =3D BIT(12), + ERR_STS_MPE =3D BIT(13), + ERR_STS_SCE =3D BIT(14), + ERR_STS_STE =3D BIT(15), + ERR_STS_FOW =3D BIT(16), + ERR_STS_UE =3D BIT(17), + ERR_STS_MCH =3D BIT(26), ERR_STS_LOC_SHIFT =3D 27, }; =20 @@ -344,8 +344,8 @@ enum { * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions. */ enum { - RAM_DBG_ADDR_FW =3D (1 << 30), - RAM_DBG_ADDR_FR =3D (1 << 31), + RAM_DBG_ADDR_FW =3D BIT(30), + RAM_DBG_ADDR_FR =3D BIT(31), }; =20 /* @@ -381,33 +381,33 @@ enum { * 10G MAC Address Register (XGMAC_ADDR) bit definitions. */ enum { - XGMAC_ADDR_RDY =3D (1 << 31), - XGMAC_ADDR_R =3D (1 << 30), - XGMAC_ADDR_XME =3D (1 << 29), + XGMAC_ADDR_RDY =3D BIT(31), + XGMAC_ADDR_R =3D BIT(30), + XGMAC_ADDR_XME =3D BIT(29), =20 /* XGMAC control registers */ PAUSE_SRC_LO =3D 0x00000100, PAUSE_SRC_HI =3D 0x00000104, GLOBAL_CFG =3D 0x00000108, - GLOBAL_CFG_RESET =3D (1 << 0), - GLOBAL_CFG_JUMBO =3D (1 << 6), - GLOBAL_CFG_TX_STAT_EN =3D (1 << 10), - GLOBAL_CFG_RX_STAT_EN =3D (1 << 11), + GLOBAL_CFG_RESET =3D BIT(0), + GLOBAL_CFG_JUMBO =3D BIT(6), + GLOBAL_CFG_TX_STAT_EN =3D BIT(10), + GLOBAL_CFG_RX_STAT_EN =3D BIT(11), TX_CFG =3D 0x0000010c, - TX_CFG_RESET =3D (1 << 0), - TX_CFG_EN =3D (1 << 1), - TX_CFG_PREAM =3D (1 << 2), + TX_CFG_RESET =3D BIT(0), + TX_CFG_EN =3D BIT(1), + TX_CFG_PREAM =3D BIT(2), RX_CFG =3D 0x00000110, - RX_CFG_RESET =3D (1 << 0), - RX_CFG_EN =3D (1 << 1), - RX_CFG_PREAM =3D (1 << 2), + RX_CFG_RESET =3D BIT(0), + RX_CFG_EN =3D BIT(1), + RX_CFG_PREAM =3D BIT(2), FLOW_CTL =3D 0x0000011c, PAUSE_OPCODE =3D 0x00000120, PAUSE_TIMER =3D 0x00000124, PAUSE_FRM_DEST_LO =3D 0x00000128, PAUSE_FRM_DEST_HI =3D 0x0000012c, MAC_TX_PARAMS =3D 0x00000134, - MAC_TX_PARAMS_JUMBO =3D (1 << 31), + MAC_TX_PARAMS_JUMBO =3D BIT(31), MAC_TX_PARAMS_SIZE_SHIFT =3D 16, MAC_RX_PARAMS =3D 0x00000138, MAC_SYS_INT =3D 0x00000144, @@ -444,8 +444,8 @@ enum { RX_OVERFLOW_MASK =3D 0x000002b8, TX_OVERFLOW_MASK =3D 0x000002bc, STAT_CNT_CTL =3D 0x000002c0, - STAT_CNT_CTL_CLEAR_TX =3D (1 << 0), - STAT_CNT_CTL_CLEAR_RX =3D (1 << 1), + STAT_CNT_CTL_CLEAR_TX =3D BIT(0), + STAT_CNT_CTL_CLEAR_RX =3D BIT(1), AUX_RX_HALF_FULL_DET =3D 0x000002d0, AUX_TX_HALF_FULL_DET =3D 0x000002d4, AUX_RX_OVERFLOW_DET =3D 0x000002d8, @@ -499,9 +499,9 @@ enum { */ enum { ETS_QUEUE_SHIFT =3D 29, - ETS_REF =3D (1 << 26), - ETS_RS =3D (1 << 27), - ETS_P =3D (1 << 28), + ETS_REF =3D BIT(26), + ETS_RS =3D BIT(27), + ETS_P =3D BIT(28), ETS_FC_COS_SHIFT =3D 23, }; =20 @@ -509,9 +509,9 @@ enum { * Flash Address Register (FLASH_ADDR) bit definitions. */ enum { - FLASH_ADDR_RDY =3D (1 << 31), - FLASH_ADDR_R =3D (1 << 30), - FLASH_ADDR_ERR =3D (1 << 29), + FLASH_ADDR_RDY =3D BIT(31), + FLASH_ADDR_R =3D BIT(30), + FLASH_ADDR_ERR =3D BIT(29), }; =20 /* @@ -523,7 +523,7 @@ enum { CQ_STOP_TYPE_START =3D 0x00000100, CQ_STOP_TYPE_STOP =3D 0x00000200, CQ_STOP_TYPE_READ =3D 0x00000300, - CQ_STOP_EN =3D (1 << 15), + CQ_STOP_EN =3D BIT(15), }; =20 /* @@ -544,11 +544,11 @@ enum { MAC_ADDR_TYPE_MGMT_V4 =3D 0x00070000, MAC_ADDR_TYPE_MGMT_V6 =3D 0x00080000, MAC_ADDR_TYPE_MGMT_TU_DP =3D 0x00090000, - MAC_ADDR_ADR =3D (1 << 25), - MAC_ADDR_RS =3D (1 << 26), - MAC_ADDR_E =3D (1 << 27), - MAC_ADDR_MR =3D (1 << 30), - MAC_ADDR_MW =3D (1 << 31), + MAC_ADDR_ADR =3D BIT(25), + MAC_ADDR_RS =3D BIT(26), + MAC_ADDR_E =3D BIT(27), + MAC_ADDR_MR =3D BIT(30), + MAC_ADDR_MW =3D BIT(31), MAX_MULTICAST_ENTRIES =3D 32, =20 /* Entry count and words per entry @@ -580,34 +580,34 @@ enum { * MAC Protocol Address Index Register (SPLT_HDR) bit definitions. */ enum { - SPLT_HDR_EP =3D (1 << 31), + SPLT_HDR_EP =3D BIT(31), }; =20 /* * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions. */ enum { - FC_RCV_CFG_ECT =3D (1 << 15), - FC_RCV_CFG_DFH =3D (1 << 20), - FC_RCV_CFG_DVF =3D (1 << 21), - FC_RCV_CFG_RCE =3D (1 << 27), - FC_RCV_CFG_RFE =3D (1 << 28), - FC_RCV_CFG_TEE =3D (1 << 29), - FC_RCV_CFG_TCE =3D (1 << 30), - FC_RCV_CFG_TFE =3D (1 << 31), + FC_RCV_CFG_ECT =3D BIT(15), + FC_RCV_CFG_DFH =3D BIT(20), + FC_RCV_CFG_DVF =3D BIT(21), + FC_RCV_CFG_RCE =3D BIT(27), + FC_RCV_CFG_RFE =3D BIT(28), + FC_RCV_CFG_TEE =3D BIT(29), + FC_RCV_CFG_TCE =3D BIT(30), + FC_RCV_CFG_TFE =3D BIT(31), }; =20 /* * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions. */ enum { - NIC_RCV_CFG_PPE =3D (1 << 0), + NIC_RCV_CFG_PPE =3D BIT(0), NIC_RCV_CFG_VLAN_MASK =3D 0x00060000, NIC_RCV_CFG_VLAN_ALL =3D 0x00000000, NIC_RCV_CFG_VLAN_MATCH_ONLY =3D 0x00000002, NIC_RCV_CFG_VLAN_MATCH_AND_NON =3D 0x00000004, NIC_RCV_CFG_VLAN_NONE_AND_NON =3D 0x00000006, - NIC_RCV_CFG_RV =3D (1 << 3), + NIC_RCV_CFG_RV =3D BIT(3), NIC_RCV_CFG_DFQ_MASK =3D (0x7f000000), NIC_RCV_CFG_DFQ_SHIFT =3D 8, NIC_RCV_CFG_DFQ =3D 0, /* HARDCODE default queue to 0. */ @@ -617,20 +617,20 @@ enum { * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions. */ enum { - MGMT_RCV_CFG_ARP =3D (1 << 0), - MGMT_RCV_CFG_DHC =3D (1 << 1), - MGMT_RCV_CFG_DHS =3D (1 << 2), - MGMT_RCV_CFG_NP =3D (1 << 3), - MGMT_RCV_CFG_I6N =3D (1 << 4), - MGMT_RCV_CFG_I6R =3D (1 << 5), - MGMT_RCV_CFG_DH6 =3D (1 << 6), - MGMT_RCV_CFG_UD1 =3D (1 << 7), - MGMT_RCV_CFG_UD0 =3D (1 << 8), - MGMT_RCV_CFG_BCT =3D (1 << 9), - MGMT_RCV_CFG_MCT =3D (1 << 10), - MGMT_RCV_CFG_DM =3D (1 << 11), - MGMT_RCV_CFG_RM =3D (1 << 12), - MGMT_RCV_CFG_STL =3D (1 << 13), + MGMT_RCV_CFG_ARP =3D BIT(0), + MGMT_RCV_CFG_DHC =3D BIT(1), + MGMT_RCV_CFG_DHS =3D BIT(2), + MGMT_RCV_CFG_NP =3D BIT(3), + MGMT_RCV_CFG_I6N =3D BIT(4), + MGMT_RCV_CFG_I6R =3D BIT(5), + MGMT_RCV_CFG_DH6 =3D BIT(6), + MGMT_RCV_CFG_UD1 =3D BIT(7), + MGMT_RCV_CFG_UD0 =3D BIT(8), + MGMT_RCV_CFG_BCT =3D BIT(9), + MGMT_RCV_CFG_MCT =3D BIT(10), + MGMT_RCV_CFG_DM =3D BIT(11), + MGMT_RCV_CFG_RM =3D BIT(12), + MGMT_RCV_CFG_STL =3D BIT(13), MGMT_RCV_CFG_VLAN_MASK =3D 0xc0000000, MGMT_RCV_CFG_VLAN_ALL =3D 0x00000000, MGMT_RCV_CFG_VLAN_MATCH_ONLY =3D 0x00004000, @@ -655,44 +655,44 @@ enum { RT_IDX_DST_COS_Q =3D 0x00200000, RT_IDX_DST_DFLT_Q =3D 0x00300000, RT_IDX_DST_DEST_Q =3D 0x00400000, - RT_IDX_RS =3D (1 << 26), - RT_IDX_E =3D (1 << 27), - RT_IDX_MR =3D (1 << 30), - RT_IDX_MW =3D (1 << 31), + RT_IDX_RS =3D BIT(26), + RT_IDX_E =3D BIT(27), + RT_IDX_MR =3D BIT(30), + RT_IDX_MW =3D BIT(31), =20 /* Nic Queue format - type 2 bits */ - RT_IDX_BCAST =3D (1 << 0), - RT_IDX_MCAST =3D (1 << 1), - RT_IDX_MCAST_MATCH =3D (1 << 2), - RT_IDX_MCAST_REG_MATCH =3D (1 << 3), - RT_IDX_MCAST_HASH_MATCH =3D (1 << 4), - RT_IDX_FC_MACH =3D (1 << 5), - RT_IDX_ETH_FCOE =3D (1 << 6), - RT_IDX_CAM_HIT =3D (1 << 7), - RT_IDX_CAM_BIT0 =3D (1 << 8), - RT_IDX_CAM_BIT1 =3D (1 << 9), - RT_IDX_VLAN_TAG =3D (1 << 10), - RT_IDX_VLAN_MATCH =3D (1 << 11), - RT_IDX_VLAN_FILTER =3D (1 << 12), - RT_IDX_ETH_SKIP1 =3D (1 << 13), - RT_IDX_ETH_SKIP2 =3D (1 << 14), - RT_IDX_BCAST_MCAST_MATCH =3D (1 << 15), - RT_IDX_802_3 =3D (1 << 16), - RT_IDX_LLDP =3D (1 << 17), - RT_IDX_UNUSED018 =3D (1 << 18), - RT_IDX_UNUSED019 =3D (1 << 19), - RT_IDX_UNUSED20 =3D (1 << 20), - RT_IDX_UNUSED21 =3D (1 << 21), - RT_IDX_ERR =3D (1 << 22), - RT_IDX_VALID =3D (1 << 23), - RT_IDX_TU_CSUM_ERR =3D (1 << 24), - RT_IDX_IP_CSUM_ERR =3D (1 << 25), - RT_IDX_MAC_ERR =3D (1 << 26), - RT_IDX_RSS_TCP6 =3D (1 << 27), - RT_IDX_RSS_TCP4 =3D (1 << 28), - RT_IDX_RSS_IPV6 =3D (1 << 29), - RT_IDX_RSS_IPV4 =3D (1 << 30), - RT_IDX_RSS_MATCH =3D (1 << 31), + RT_IDX_BCAST =3D BIT(0), + RT_IDX_MCAST =3D BIT(1), + RT_IDX_MCAST_MATCH =3D BIT(2), + RT_IDX_MCAST_REG_MATCH =3D BIT(3), + RT_IDX_MCAST_HASH_MATCH =3D BIT(4), + RT_IDX_FC_MACH =3D BIT(5), + RT_IDX_ETH_FCOE =3D BIT(6), + RT_IDX_CAM_HIT =3D BIT(7), + RT_IDX_CAM_BIT0 =3D BIT(8), + RT_IDX_CAM_BIT1 =3D BIT(9), + RT_IDX_VLAN_TAG =3D BIT(10), + RT_IDX_VLAN_MATCH =3D BIT(11), + RT_IDX_VLAN_FILTER =3D BIT(12), + RT_IDX_ETH_SKIP1 =3D BIT(13), + RT_IDX_ETH_SKIP2 =3D BIT(14), + RT_IDX_BCAST_MCAST_MATCH =3D BIT(15), + RT_IDX_802_3 =3D BIT(16), + RT_IDX_LLDP =3D BIT(17), + RT_IDX_UNUSED018 =3D BIT(18), + RT_IDX_UNUSED019 =3D BIT(19), + RT_IDX_UNUSED20 =3D BIT(20), + RT_IDX_UNUSED21 =3D BIT(21), + RT_IDX_ERR =3D BIT(22), + RT_IDX_VALID =3D BIT(23), + RT_IDX_TU_CSUM_ERR =3D BIT(24), + RT_IDX_IP_CSUM_ERR =3D BIT(25), + RT_IDX_MAC_ERR =3D BIT(26), + RT_IDX_RSS_TCP6 =3D BIT(27), + RT_IDX_RSS_TCP4 =3D BIT(28), + RT_IDX_RSS_IPV6 =3D BIT(29), + RT_IDX_RSS_IPV4 =3D BIT(30), + RT_IDX_RSS_MATCH =3D BIT(31), =20 /* Hierarchy for the NIC Queue Mask */ RT_IDX_ALL_ERR_SLOT =3D 0, @@ -721,8 +721,8 @@ enum { * Serdes Address Register (XG_SERDES_ADDR) bit definitions. */ enum { - XG_SERDES_ADDR_RDY =3D (1 << 31), - XG_SERDES_ADDR_R =3D (1 << 30), + XG_SERDES_ADDR_RDY =3D BIT(31), + XG_SERDES_ADDR_R =3D BIT(30), =20 XG_SERDES_ADDR_STS =3D 0x00001E06, XG_SERDES_ADDR_XFI1_PWR_UP =3D 0x00000005, @@ -752,9 +752,9 @@ enum { * NIC Probe Mux Address Register (PRB_MX_ADDR) bit definitions. */ enum { - PRB_MX_ADDR_ARE =3D (1 << 16), - PRB_MX_ADDR_UP =3D (1 << 15), - PRB_MX_ADDR_SWP =3D (1 << 14), + PRB_MX_ADDR_ARE =3D BIT(16), + PRB_MX_ADDR_UP =3D BIT(15), + PRB_MX_ADDR_SWP =3D BIT(14), =20 /* Module select values. */ PRB_MX_ADDR_MAX_MODS =3D 21, @@ -890,8 +890,8 @@ enum { CAM_OUT_ROUTE_FC =3D 0, CAM_OUT_ROUTE_NIC =3D 1, CAM_OUT_FUNC_SHIFT =3D 2, - CAM_OUT_RV =3D (1 << 4), - CAM_OUT_SH =3D (1 << 15), + CAM_OUT_RV =3D BIT(4), + CAM_OUT_SH =3D BIT(15), CAM_OUT_CQ_ID_SHIFT =3D 5, }; =20 @@ -936,14 +936,14 @@ enum { MB_CMD_IDC_ACK =3D 0x00000101, /* Inter-Driver Communication */ MB_CMD_SET_WOL_MODE =3D 0x00000110, /* Wake On Lan */ MB_WOL_DISABLE =3D 0, - MB_WOL_MAGIC_PKT =3D (1 << 1), - MB_WOL_FLTR =3D (1 << 2), - MB_WOL_UCAST =3D (1 << 3), - MB_WOL_MCAST =3D (1 << 4), - MB_WOL_BCAST =3D (1 << 5), - MB_WOL_LINK_UP =3D (1 << 6), - MB_WOL_LINK_DOWN =3D (1 << 7), - MB_WOL_MODE_ON =3D (1 << 16), /* Wake on Lan Mode on */ + MB_WOL_MAGIC_PKT =3D BIT(1), + MB_WOL_FLTR =3D BIT(2), + MB_WOL_UCAST =3D BIT(3), + MB_WOL_MCAST =3D BIT(4), + MB_WOL_BCAST =3D BIT(5), + MB_WOL_LINK_UP =3D BIT(6), + MB_WOL_LINK_DOWN =3D BIT(7), + MB_WOL_MODE_ON =3D BIT(16), /* Wake on Lan Mode on */ MB_CMD_SET_WOL_FLTR =3D 0x00000111, /* Wake On Lan Filter */ MB_CMD_CLEAR_WOL_FLTR =3D 0x00000112, /* Wake On Lan Filter */ MB_CMD_SET_WOL_MAGIC =3D 0x00000113, /* Wake On Lan Magic Packet */ @@ -957,11 +957,11 @@ enum { QL_LED_BLINK =3D 0x03e803e8, MB_CMD_GET_LED_CFG =3D 0x00000126, /* Get LED Configuration Register */ MB_CMD_SET_MGMNT_TFK_CTL =3D 0x00000160, /* Set Mgmnt Traffic Control */ - MB_SET_MPI_TFK_STOP =3D (1 << 0), - MB_SET_MPI_TFK_RESUME =3D (1 << 1), + MB_SET_MPI_TFK_STOP =3D BIT(0), + MB_SET_MPI_TFK_RESUME =3D BIT(1), MB_CMD_GET_MGMNT_TFK_CTL =3D 0x00000161, /* Get Mgmnt Traffic Control */ - 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if ((ctx->irq_mask & (1 << trx_ring->cq_id)) && + if ((ctx->irq_mask & BIT(trx_ring->cq_id)) && (qlge_read_sh_reg(trx_ring->prod_idx_sh_reg) !=3D trx_ring->cnsmr_idx)) { netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev, @@ -3222,13 +3222,13 @@ static void qlge_set_irq_mask(struct qlge_adapter *= qdev, struct intr_context *ct /* Add the RSS ring serviced by this vector * to the mask. */ - ctx->irq_mask =3D (1 << qdev->rx_ring[vect].cq_id); + ctx->irq_mask =3D BIT(qdev->rx_ring[vect].cq_id); /* Add the TX ring(s) serviced by this vector * to the mask. */ for (j =3D 0; j < tx_rings_per_vector; j++) { ctx->irq_mask |=3D - (1 << qdev->rx_ring[qdev->rss_ring_count + + BIT(qdev->rx_ring[qdev->rss_ring_count + (vect * tx_rings_per_vector) + j].cq_id); } } else { @@ -3236,7 +3236,7 @@ static void qlge_set_irq_mask(struct qlge_adapter *qd= ev, struct intr_context *ct * ID into the mask. */ for (j =3D 0; j < qdev->rx_ring_count; j++) - ctx->irq_mask |=3D (1 << qdev->rx_ring[j].cq_id); + ctx->irq_mask |=3D BIT(qdev->rx_ring[j].cq_id); } } =20 diff --git a/drivers/staging/qlge/qlge_mpi.c b/drivers/staging/qlge/qlge_mp= i.c index 96a4de6d2b34..ce0b54603071 100644 --- a/drivers/staging/qlge/qlge_mpi.c +++ b/drivers/staging/qlge/qlge_mpi.c @@ -113,7 +113,7 @@ int qlge_own_firmware(struct qlge_adapter *qdev) * core dump and firmware reset after an error. */ temp =3D qlge_read32(qdev, STS); - if (!(temp & (1 << (8 + qdev->alt_func)))) + if (!(temp & BIT((8 + qdev->alt_func)))) return 1; =20 return 0; --=20 2.25.1