From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F1C9E7C4CE for ; Wed, 4 Oct 2023 15:38:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233719AbjJDPix (ORCPT ); Wed, 4 Oct 2023 11:38:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233443AbjJDPiw (ORCPT ); Wed, 4 Oct 2023 11:38:52 -0400 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75254BF; Wed, 4 Oct 2023 08:38:49 -0700 (PDT) Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3af609c3e74so1499762b6e.2; Wed, 04 Oct 2023 08:38:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696433929; x=1697038729; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YvpIgA1NrzZoExz057WGLdJuiKTT6FN12MIO7ifzbic=; b=aMVs+eg9yhgQfEhjsdSIuB3/cRfh5ZEBmp0vcDsTesNp6KKAmsfgwi3wO9414s5/lm lGGSSqDbt8D9HIxLVE+2Or923wwuE5LiZ8X4DU1fZNWq+LWVc2ZyEsP+8i/hZGlWUfT1 MN4stLQedYdLBuQvyNqmG6qr1VD1sFlS6oUkJoPWgBeZZd+WAGLa20CJjy8MMWb8oOr2 ck8trxyIq2ZLZ8TwLD2N4qX2SKJf5y88oa/Q/DPmohyyII/4sG6uiBt3jd5vaR0wpLD7 zNfnJprEeJH2bRMq09dffNgG9IFWBC/IPbGDCpeLdfvQAl10pgWP7fQaMKq2Tzh7a69D hVpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696433929; x=1697038729; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YvpIgA1NrzZoExz057WGLdJuiKTT6FN12MIO7ifzbic=; b=aHULSexLSizxn1f9J3nCnoXCerG0Pu+TWiYfq2A2s2ClbjeP/wjN40sM4zIZ0JlLQ3 f99CDJoWxF7O27tNRHz2BsJXrrdxQgRQlrfsZRTLMdFk1DPx3AWwqwgktYrpkBe6uTnA D4SZ4DgHwwLtsN2qILzHBXW6fr2ZKXdFxk6XNTpSPeOHCotnWusTGc1PHy2UwrHIUkHk RLs9K3VjUKqoDjIpeioVWeR6zyShgDV3qhqKaEdmhp8OCa7vEC+UuXGUcI9sroKdZSEM UZQOw4Uq77LXIckImqCfh49ZDaaeP0sdHV3RZF7cTBON7EfYMeE+tXfjkw8aW/bBPXD+ XX0A== X-Gm-Message-State: AOJu0Yz1McMiQ/sGHPK3DcjkxEqYJCuyfWP19HmQtyevq1qQp4xp1wpH zU7iG/jaJLDsmO9vfx5EehQ= X-Google-Smtp-Source: AGHT+IF6NBfKh7H6lOBUPb8/5Av2JxoQiA0M+JJQ1P26d/Dn8ttnK9MCbFGsUzJJC5LJ6rSsak9IuA== X-Received: by 2002:a05:6808:1829:b0:3ab:84f0:b49d with SMTP id bh41-20020a056808182900b003ab84f0b49dmr3646541oib.3.1696433928750; Wed, 04 Oct 2023 08:38:48 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id b24-20020aca1b18000000b003ae24b38f99sm541000oib.2.2023.10.04.08.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:38:48 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley Subject: [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support Date: Wed, 4 Oct 2023 23:38:39 +0800 Message-Id: <46e7460668bcd88f35fbcc3cc55a96d1fd2a1fea.1696433229.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V cores. Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Acked-by: Chao Wei Signed-off-by: Chen Wang Acked-by: Chen Wang --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6833d01e2e70..d4df7b5d0f16 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,11 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. =20 +config ARCH_SOPHGO + bool "Sophgo SoCs" + help + This enables support for Sophgo SoC platform hardware. + config ARCH_STARFIVE def_bool SOC_STARFIVE =20 --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DBFFE7C4D4 for ; Wed, 4 Oct 2023 15:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243156AbjJDPk5 (ORCPT ); Wed, 4 Oct 2023 11:40:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243104AbjJDPkq (ORCPT ); Wed, 4 Oct 2023 11:40:46 -0400 Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7518F112; Wed, 4 Oct 2023 08:40:41 -0700 (PDT) Received: by mail-oo1-xc34.google.com with SMTP id 006d021491bc7-57ddde51033so540789eaf.1; Wed, 04 Oct 2023 08:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696434041; x=1697038841; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JGAJAL4u2VX3FIWEkVnsPhkCa6a31tzGgZXni0+jw5s=; b=Ivtq1BQI8RsQQ5fd0UQz646ec25V5AN05GeW7zJTxIIBF5mdbotQmv8xwyP5HCIksr mWrCslOcHrVptQdDPB9JW3hnDI3PVrFyCUfpJQ24gjvZ/j7JAD+yyeMfytoHm3Ci2nYn qy1Y3VWEWjocMnThwnt1ddkw9ZNIsDoosSCysF7AVlmQ0EAYGy3/7sntMBAEzzV5b5pK yMD5NufDG9qYtc47TnV/uB0fmwiPa1KvTM6gY+VHpvZrX0XB3k/OLE0LnhD+7BYX0CCO Rp/eLe8/1L3hw55v0NklwVA9BJ0pBTGmV8nqDdUHbTFa3BBFxyoTeFnrDIol0EGk9ZB9 JQOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696434041; x=1697038841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JGAJAL4u2VX3FIWEkVnsPhkCa6a31tzGgZXni0+jw5s=; b=A6ovLa2DdWKMC3evtjzrrqehKZrczqI1+VHeQBj5sHO1lpmjCM8FwJOaC7lCoBSuTt 88Yr9CrzORAXdTVnlqE8YZUlpzqa89h0TrQq+3TgWbPsgSqaZyHJrQlSfPCApbCX7AI9 hqYSaYMK7tMYWsnWOsO9UrJIn3DEwtd734PC52lEQZxSbly1qo1B23b7bc8qny666bg4 4RYiihFC0hajyi6jRIRnAry9S8nbPYNwHwFkSlj0nmB3cLPaXWBZOxsYZtWeqgGV3xWo /GQ9lBm9anEM3eje0SaY6ctB8/x59gPxXJsdwyIDcvU3bFenqLw+v4WoyCPEGkUe5o06 AxAQ== X-Gm-Message-State: AOJu0Yy/M2pSyzffvaUoO/uLN6tVv+WkD+LulBUl5TWRRDdqfiXxSQ0i qF1NYytUQL02J4j6N+svdE8= X-Google-Smtp-Source: AGHT+IFTIU1nASd/e+dc6F3k6Dv/9g628/YQ1wR0t0xkHX0r9SBPbwv40GV37Gq9oXgdJhnenlUoOg== X-Received: by 2002:a4a:255c:0:b0:571:1c44:c9c0 with SMTP id v28-20020a4a255c000000b005711c44c9c0mr8013ooe.1.1696434040692; Wed, 04 Oct 2023 08:40:40 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 128-20020a4a1d86000000b0057b43a25deasm677359oog.3.2023.10.04.08.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:40:40 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley Subject: [PATCH v4 02/10] dt-bindings: vendor-prefixes: add milkv/sophgo Date: Wed, 4 Oct 2023 23:40:32 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang Add new vendor strings to dt bindings. These new vendor strings are used by - SOPHGO's SG2042 SoC [1] - Milk-V Pioneer board [2], which uses SG2042 chip. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Link: https://milkv.io/pioneer [2] Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Acked-by: Chao Wei Signed-off-by: Chen Wang Acked-by: Chen Wang --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 573578db9509..fcca9e070a9a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -863,6 +863,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milkv,.*": + description: MilkV Technology Co., Ltd "^miniand,.*": description: Miniand Tech "^minix,.*": @@ -1273,6 +1275,8 @@ patternProperties: description: Solomon Systech Limited "^sony,.*": description: Sony Corporation + "^sophgo,.*": + description: Sophgo Technology Inc. "^sourceparts,.*": description: Source Parts Inc. "^spansion,.*": --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A26FFE7C4D4 for ; Wed, 4 Oct 2023 15:42:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242951AbjJDPmT (ORCPT ); Wed, 4 Oct 2023 11:42:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233775AbjJDPmQ (ORCPT ); Wed, 4 Oct 2023 11:42:16 -0400 Received: from mail-oo1-xc2d.google.com (mail-oo1-xc2d.google.com [IPv6:2607:f8b0:4864:20::c2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07752D7; Wed, 4 Oct 2023 08:42:13 -0700 (PDT) Received: by mail-oo1-xc2d.google.com with SMTP id 006d021491bc7-57b74782be6so1294919eaf.2; Wed, 04 Oct 2023 08:42:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696434132; x=1697038932; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WnxaBYdRGKVgJldzBvlLszd95TgiOglWQuyS4MNphf0=; b=JkLUUjhU0GuUBAvofFTHDBuggUKVXkr9S8Z8+QJ4bo57dtuKA3b5KYCnV359GKtceo 4xPeHnk6HXwqUxjL+u2Ff4veQHMY/8kwIqQveUnzi+9gKz54MGzH0CIW9enrZYDUU++q g1xY5NpBRsSc6n1zQAPJxr0JEnoGxlV2o0ehToxIQ9OaMeNRSWOeYbNRLvvzrH6+Qjkc GNrHGTbWrbFklwyY2IgAr+BaaPQGjdhHLUTESBy85U159TWZCOmR7C/0lK2ijKp0wQ2R qc56yPTx4uWtTVwReVhGs4Y+xUdDDzfT3TgFCzggJQVsqkxZxF+HzYMN8EByGD8gk1DV CLJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696434132; x=1697038932; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WnxaBYdRGKVgJldzBvlLszd95TgiOglWQuyS4MNphf0=; b=hZ5483NRBzJufhDjXuMc5efDiCJMZjSEt160p+OghrTd/suK5KEXXrw+vVKQ0uaP7/ EPHiamkyIXo5VXCNIGoeO/x5sl1wPFHLc0iRysXUEBIlJEHgE6R92LgP/LvDwAo0AjLB hfI53R0262Nq3Lefw1EnZIWiINXJo36SEuU3Z/NRj7/gonHOzWo8q/WxkCddfVOpmTmL 3O/VbWUGk6EjMcsAwJTV1GY1UjTCtD/IO3EU4zEiEuz0Cn1MROtOXRz7sX6tgaIiIRKg p7npFF6MIt56SFi0HtghpBsj1EaKOqK7UFYztVs09luM7F+E5rQnJz7gDu20JVNg8O8R BwKw== X-Gm-Message-State: AOJu0YyDXHdIGXprGEy0Hmksapjz5XGULSzCsqGabYhdJqOJjQSolkLX MBibWem8L0Ed+nCgaAhjJ5JMOpsvW/izdA== X-Google-Smtp-Source: AGHT+IEQbM2bZQBMikxUSN8+tNBqkEpBzn/Q1qrIXW/53+hljMBT5wP0e0XQ6KwfcYnOIkCY6UfnuA== X-Received: by 2002:a05:6820:220e:b0:56c:cd0c:1d67 with SMTP id cj14-20020a056820220e00b0056ccd0c1d67mr2315269oob.7.1696434131744; Wed, 04 Oct 2023 08:42:11 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id f65-20020a4a5844000000b0057dd74ad3casm672580oob.41.2023.10.04.08.42.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:42:11 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Krzysztof Kozlowski Subject: [PATCH v4 03/10] dt-bindings: riscv: add sophgo sg2042 bindings Date: Wed, 4 Oct 2023 23:42:03 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang Add DT binding documentation for the SOPHGO's SG2042 Soc [1] and the Milk-V Pioneer board [2]. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Link: https://milkv.io/pioneer [2] Acked-by: Chao Wei Reviewed-by: Guo Ren Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chen Wang Acked-by: Chen Wang --- .../devicetree/bindings/riscv/sophgo.yaml | 28 +++++++++++++++++++ MAINTAINERS | 6 ++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Document= ation/devicetree/bindings/riscv/sophgo.yaml new file mode 100644 index 000000000000..8adb5f39ca53 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sophgo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SoC-based boards + +maintainers: + - Chao Wei + - Chen Wang + +description: + Sophgo SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milkv,pioneer + - const: sophgo,sg2042 + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..97cb8abcfeee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20063,6 +20063,12 @@ F: drivers/char/sonypi.c F: drivers/platform/x86/sony-laptop.c F: include/linux/sony-laptop.h =20 +SOPHGO DEVICETREES +M: Chao Wei +M: Chen Wang +S: Maintained +F: Documentation/devicetree/bindings/riscv/sophgo.yaml + SOUND M: Jaroslav Kysela M: Takashi Iwai --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9565AE7C4D4 for ; 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Wed, 04 Oct 2023 08:42:31 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id n9-20020a0568301e8900b006b954f7f422sm486778otr.6.2023.10.04.08.42.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:42:31 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley Subject: [PATCH v4 04/10] dt-bindings: riscv: Add T-HEAD C920 compatibles Date: Wed, 4 Oct 2023 23:42:23 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang The C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO's SG2042 SoC. Acked-by: Chao Wei Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Chen Wang Acked-by: Chen Wang --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 38c0b5213736..185a0191bad6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - sifive,u74-mc - thead,c906 - thead,c910 + - thead,c920 - const: riscv - items: - enum: --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6E73E7C4D4 for ; Wed, 4 Oct 2023 15:42:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243041AbjJDPm4 (ORCPT ); Wed, 4 Oct 2023 11:42:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45980 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242943AbjJDPmw (ORCPT ); Wed, 4 Oct 2023 11:42:52 -0400 Received: from mail-oi1-x236.google.com (mail-oi1-x236.google.com [IPv6:2607:f8b0:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10BEEC4; Wed, 4 Oct 2023 08:42:49 -0700 (PDT) Received: by mail-oi1-x236.google.com with SMTP id 5614622812f47-3ae214a077cso1625682b6e.0; Wed, 04 Oct 2023 08:42:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696434168; x=1697038968; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NfM5XCGs2tSFYtxKjnEgC+KhHndiRz+hbU9xrIiDamk=; b=Cbhp+7K+tnrjQrVKxo7JSPvNHUaoq3Kvzt18lbdkr0LOH0RKK2E67qvyyLIxMjHqAb 1MkS3mlIoTAI0xh3Du/y2esDzHRFwazuo6BYdHiu0Wjg/HVpyE+O/sooi5EVS+3KJqh5 vs54QFSQP5zhhG9tjLJLbkLy4TIQ9pnaUd83gUjIBbwbqX5DiXI9qkA2oWymJfw8SAsp X+XgQ305QI3XeBHx1wXNqR4GsZexW/iZRjVVNTd07hcBoHgv9KIPh+udtgcu0XYT0e8e hpmScuBy+vsXXev+oANffEJA2Dkt7YnqXXBLKtQNIokShhJrnqq1rb1c7P2HcoCHFAR/ bGMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696434168; x=1697038968; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NfM5XCGs2tSFYtxKjnEgC+KhHndiRz+hbU9xrIiDamk=; b=HjV6MINauWPDH7yR8nj9AAzY3nuvzwsArslWFAN6ffdSkQIB3xcmUK+9XKfF4pSFz4 T4LpBvxehu9/nTzvXsIUYKI+DqcvwW0bhbwgLJGkkgnFm4yBM8AR0vFyMM2kCqT2tVUR 7tQTvmg+GB9mCL3HOYAeC9x+XCgwLATOvG9l3Fphxy5rv+fMJ04X5JTh7NVVE6XUW5T7 2b/lsDvY6W3BkZhNVlzvq8SOV6QFbZRecunz8FFo2Vdd3aCt6mPvoBojLUHR+IU0Xux7 uEqdCQ6BJOfpaHobFGPgZoE53JWabfr2HbqIdR/JdwHT6VZeoSLR1qqHTb/CGKuJPDKu FRWA== X-Gm-Message-State: AOJu0Yz2lSwgRxHw/df/VxY1xGM9tcnzNDltxCbR45AhDvwRQgh9lx+j w/J1VVyXxdGeCplAMmxHLlQ= X-Google-Smtp-Source: AGHT+IHtVip/Sx3qhTmZhBJxHyVWkRBSXIODOPj/xBcCYq61Wz1gSwS6iTyG8GCGDEx8qhjHgg/n5A== X-Received: by 2002:a05:6808:200c:b0:3a3:47c5:1de3 with SMTP id q12-20020a056808200c00b003a347c51de3mr3124437oiw.49.1696434168310; Wed, 04 Oct 2023 08:42:48 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 25-20020a544199000000b003ae59076b90sm540093oiy.14.2023.10.04.08.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:42:47 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley Subject: [PATCH v4 05/10] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC Date: Wed, 4 Oct 2023 23:42:41 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang Add compatible string for SOPHGO SG2042 plic. Acked-by: Chao Wei Reviewed-by: Guo Ren Acked-by: Conor Dooley Signed-off-by: Chen Wang Acked-by: Chen Wang --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index dc1f28e55266..16f9c4760c0f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic - items: --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F934E7C4D4 for ; Wed, 4 Oct 2023 15:43:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243043AbjJDPnl (ORCPT ); Wed, 4 Oct 2023 11:43:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242943AbjJDPnk (ORCPT ); Wed, 4 Oct 2023 11:43:40 -0400 Received: from mail-oo1-xc33.google.com (mail-oo1-xc33.google.com [IPv6:2607:f8b0:4864:20::c33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23AC3BD; Wed, 4 Oct 2023 08:43:37 -0700 (PDT) Received: by mail-oo1-xc33.google.com with SMTP id 006d021491bc7-57bc2c2f13dso1275490eaf.2; Wed, 04 Oct 2023 08:43:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696434216; x=1697039016; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hHNexQjEWqwmHrfiry0buaBQbrLt3wpcuExz+BRupW0=; b=RGe8Bj3soUScS1IDg7Le2LCbewwmiNWE7lvQbnc9vCjDPGqPrj9aaHVS2wE4GNqS5/ 3tVlRf/0gI7WwYmi0861fSM0D+G5FECU4pe3Cuj2F/aN0nXbA++odzkBLO3zRQSQXnKR ABoOF0HmmbSaUC/ThPS0GKA4Ac2t0Lz0WeGkN5gjMnU0dfRxSgt5rYuzQsc+5jvVK1x8 0JVPLwuHTku0YTmVHiMQQdoaPGFARNFLzcHwdr5PpR3nszs40aZgodUZtlm9s2mx7uUh SaApmmsPrKvf4ZCHGJefa8iopTk+9BeIscPnMybBxDjDV7yhWM4doDwrkOL3wf44P3ZZ ASng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696434216; x=1697039016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hHNexQjEWqwmHrfiry0buaBQbrLt3wpcuExz+BRupW0=; b=WebXiz4fqxYH6Ocj6swYb4NVQbdPWDlao4RC46xWsQHfgjn7NmStt69SJAH2fOgBqT oMK6rkjKoGpFRdPxZFbfRmhWTlHa51fdZBCClawoA25a/WZQI7eteKYoutG+v/NU1ICo B4rJbZg7HcxcqWABA4ArV5uPIlr6Eu3fa0D8Hi0OVMwE0WKYERbcJsNoy9swmp04tVmu a4rdwfw3CGcQzUw0V8SoNnh3NPC9+gxLfG+TfAbUT95BSsyfcvSYdRsA5JnuiIAv3BSZ rB05nrHmiB6XwYqPy616qZiVDQgN1z8WFqbtO8NlgAWEfdv8in/n+Q6NwCD8oGvowQwp 1HRA== X-Gm-Message-State: AOJu0YzKCSN+U57xxYM/5jP2vA7BbuxCsj3BMNtEzBDsCTEsQ9N643zu +//l4NDcvARr/lVcGJ3GaN0= X-Google-Smtp-Source: AGHT+IF6r0Nf92b8yMVSXzfb//2cKp9M6wexeSeiIG3LAk4U7LnHo3090pI0Juj4ICyo7zS2BWchyQ== X-Received: by 2002:a4a:d2dc:0:b0:571:1a1d:f230 with SMTP id j28-20020a4ad2dc000000b005711a1df230mr2546119oos.9.1696434216397; Wed, 04 Oct 2023 08:43:36 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id m1-20020a4aab81000000b00573fb6178a6sm654637oon.44.2023.10.04.08.43.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:43:36 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Inochi Amaoto , Chen Wang Subject: [PATCH v4 06/10] dt-bindings: timer: Add Sophgo sg2042 CLINT timer Date: Wed, 4 Oct 2023 23:43:28 +0800 Message-Id: <6e48cbe5e60f9ada2fd1fe58e803e127f1a678e5.1696433229.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Inochi Amaoto The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, but Sophgo changes this IP layout to fit its cpu design and is incompatible with the standard sifive clint. The timer and ipi device are on the different address, and can not be handled by the sifive,clint dt-bindings. If we use the same compatible string for mswi and timer of the sg2042 clint like sifive,clint, the DT may be like this: mswi: interrupt-controller@94000000 { compatible =3D "sophgo,sg2042-clint", "thead,c900-clint"; interrupts-extended =3D <&cpu1intc 3>; reg =3D <0x94000000 0x00010000>; }; timer: timer@ac000000 { compatible =3D "sophgo,sg2042-clint", "thead,c900-clint"; interrupts-extended =3D <&cpu1intc 7>; reg =3D <0xac000000 0x00010000>; }; Since the address of mswi and timer are different, it is hard to merge them directly. So we need two DT nodes to handle both devices. If we use this DT for SBI, it will parse the mswi device in the timer initialization as the compatible string is the same, so will mswi. As they are different devices, this incorrect initialization will cause the system unusable. There is a more robust ACLINT spec. can handle this situation, but the spec. seems to be abandoned and will not be frozen in the predictable future. So it is not the time to add ACLINT spec in the kernel bindings. Instead, using vendor bindings is more acceptable. Add new vendor specific compatible strings to identify timer of sg2042 clint. Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Acked-by: Chen Wang --- .../timer/thead,c900-aclint-mtimer.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-acli= nt-mtimer.yaml diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtim= er.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.= yaml new file mode 100644 index 000000000000..fbd235650e52 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CLINT Timer + +maintainers: + - Inochi Amaoto + +properties: + compatible: + items: + - enum: + - sophgo,sg2042-aclint-mtimer + - const: thead,c900-aclint-mtimer + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@ac000000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mti= mer"; + interrupts-extended =3D <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg =3D <0xac000000 0x00010000>; + }; +... --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88135E7C4D0 for ; Wed, 4 Oct 2023 15:43:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243172AbjJDPoA (ORCPT ); Wed, 4 Oct 2023 11:44:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233616AbjJDPn6 (ORCPT ); Wed, 4 Oct 2023 11:43:58 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 761EABD; Wed, 4 Oct 2023 08:43:55 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-3af5fda8f6fso1506294b6e.3; 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charset="utf-8" From: Inochi Amaoto The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, but Sophgo changes this IP layout to fit its cpu design and is incompatible with the standard sifive clint. The timer and ipi device are on the different address, and can not be handled by the sifive,clint dt-bindings. If we use the same compatible string for mswi and timer of the sg2042 clint like sifive,clint, the DT may be like this: mswi: interrupt-controller@94000000 { compatible =3D "sophgo,sg2042-clint", "thead,c900-clint"; interrupts-extended =3D <&cpu1intc 3>; reg =3D <0x94000000 0x00010000>; }; timer: timer@ac000000 { compatible =3D "sophgo,sg2042-clint", "thead,c900-clint"; interrupts-extended =3D <&cpu1intc 7>; reg =3D <0xac000000 0x00010000>; }; Since the address of mswi and timer are different, it is hard to merge them directly. So we need two DT nodes to handle both devices. If we use this DT for SBI, it will parse the mswi device in the timer initialization as the compatible string is the same, so will mswi. As they are different devices, this incorrect initialization will cause the system unusable. There is a more robust ACLINT spec. can handle this situation, but the spec. seems to be abandoned and will not be frozen in the predictable future. So it is not the time to add ACLINT spec in the kernel bindings. Instead, using vendor bindings is more acceptable. Add new vendor specific compatible strings to identify mswi of sg2042 clint. Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Acked-by: Chen Wang --- .../thead,c900-aclint-mswi.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= thead,c900-aclint-mswi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c= 900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controll= er/thead,c900-aclint-mswi.yaml new file mode 100644 index 000000000000..065f2544b63b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-acl= int-mswi.yaml @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-= mswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device + +maintainers: + - Inochi Amaoto + +properties: + compatible: + items: + - enum: + - sophgo,sg2042-aclint-mswi + - const: thead,c900-aclint-mswi + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible =3D "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; + interrupts-extended =3D <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg =3D <0x94000000 0x00010000>; + }; +... --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B33DE7C4D0 for ; Wed, 4 Oct 2023 15:44:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243180AbjJDPoX (ORCPT ); Wed, 4 Oct 2023 11:44:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233616AbjJDPoV (ORCPT ); Wed, 4 Oct 2023 11:44:21 -0400 Received: from mail-ot1-x32f.google.com (mail-ot1-x32f.google.com [IPv6:2607:f8b0:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5597C1; Wed, 4 Oct 2023 08:44:14 -0700 (PDT) Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6c4e38483d2so1578739a34.1; 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charset="utf-8" From: Chen Wang Milk-V Pioneer motherboard is powered by SG2042. SG2042 is server grade chip with high performance, low power consumption and high data throughput. Key features: - 64 RISC-V cpu cores - 4 cores per cluster, 16 clusters on chip - More info is available at [1]. Currently only support booting into console with only uart, other features will be added soon later. Reviewed-by: Guo Ren Acked-by: Chao Wei Co-developed-by: Xiaoguang Xing Signed-off-by: Xiaoguang Xing Co-developed-by: Inochi Amaoto Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Acked-by: Chen Wang --- MAINTAINERS | 1 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++ 3 files changed, 2326 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 97cb8abcfeee..fedf042e5fb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES M: Chao Wei M: Chen Wang S: Maintained +F: arch/riscv/boot/dts/sophgo/ F: Documentation/devicetree/bindings/riscv/sophgo.yaml =20 SOUND diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/sg2042-cpus.dtsi new file mode 100644 index 000000000000..b136b6c4128c --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -0,0 +1,2000 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <50000000>; + + cpu-map { + socket0 { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + core1 { + cpu =3D <&cpu5>; + }; + core2 { + cpu =3D <&cpu6>; + }; + core3 { + cpu =3D <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu16>; + }; + core1 { + cpu =3D <&cpu17>; + }; + core2 { + cpu =3D <&cpu18>; + }; + core3 { + cpu =3D <&cpu19>; + }; + }; + + cluster3 { + core0 { + cpu =3D <&cpu20>; + }; + core1 { + cpu =3D <&cpu21>; + }; + core2 { + cpu =3D <&cpu22>; + }; + core3 { + cpu =3D <&cpu23>; + }; + }; + + cluster4 { + core0 { + cpu =3D <&cpu8>; + }; + core1 { + cpu =3D <&cpu9>; + }; + core2 { + cpu =3D <&cpu10>; + }; + core3 { + cpu =3D <&cpu11>; + }; + }; + + cluster5 { + core0 { + cpu =3D <&cpu12>; + }; + core1 { + cpu =3D <&cpu13>; + }; + core2 { + cpu =3D <&cpu14>; + }; + core3 { + cpu =3D <&cpu15>; + }; + }; + + cluster6 { + core0 { + cpu =3D <&cpu24>; + }; + core1 { + cpu =3D <&cpu25>; + }; + core2 { + cpu =3D <&cpu26>; + }; + core3 { + cpu =3D <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu =3D <&cpu28>; + }; + core1 { + cpu =3D <&cpu29>; + }; + core2 { + cpu =3D <&cpu30>; + }; + core3 { + cpu =3D <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu =3D <&cpu32>; + }; + core1 { + cpu =3D <&cpu33>; + }; + core2 { + cpu =3D <&cpu34>; + }; + core3 { + cpu =3D <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu =3D <&cpu36>; + }; + core1 { + cpu =3D <&cpu37>; + }; + core2 { + cpu =3D <&cpu38>; + }; + core3 { + cpu =3D <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu =3D <&cpu48>; + }; + core1 { + cpu =3D <&cpu49>; + }; + core2 { + cpu =3D <&cpu50>; + }; + core3 { + cpu =3D <&cpu51>; + }; + }; + + cluster11 { + core0 { + cpu =3D <&cpu52>; + }; + core1 { + cpu =3D <&cpu53>; + }; + core2 { + cpu =3D <&cpu54>; + }; + core3 { + cpu =3D <&cpu55>; + }; + }; + + cluster12 { + core0 { + cpu =3D <&cpu40>; + }; + core1 { + cpu =3D <&cpu41>; + }; + core2 { + cpu =3D <&cpu42>; + }; + core3 { + cpu =3D <&cpu43>; + }; + }; + + cluster13 { + core0 { + cpu =3D <&cpu44>; + }; + core1 { + cpu =3D <&cpu45>; + }; + core2 { + cpu =3D <&cpu46>; + }; + core3 { + cpu =3D <&cpu47>; + }; + }; + + cluster14 { + core0 { + cpu =3D <&cpu56>; + }; + core1 { + cpu =3D <&cpu57>; + }; + core2 { + cpu =3D <&cpu58>; + }; + core3 { + cpu =3D <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu =3D <&cpu60>; + }; + core1 { + cpu =3D <&cpu61>; + }; + core2 { + cpu =3D <&cpu62>; + }; + core3 { + cpu =3D <&cpu63>; + }; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <0>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <1>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <2>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <3>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu4: cpu@4 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <4>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu5: cpu@5 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <5>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu6: cpu@6 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <6>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu7: cpu@7 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <7>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu8: cpu@8 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <8>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu8_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu9: cpu@9 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <9>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu9_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu10: cpu@10 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <10>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu10_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu11: cpu@11 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <11>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu11_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu12: cpu@12 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <12>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu12_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu13: cpu@13 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <13>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu13_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu14: cpu@14 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <14>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu14_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu15: cpu@15 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <15>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu15_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu16: cpu@16 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <16>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu16_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu17: cpu@17 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <17>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu17_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu18: cpu@18 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <18>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu18_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu19: cpu@19 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <19>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu19_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu20: cpu@20 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <20>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu20_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu21: cpu@21 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <21>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu21_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu22: cpu@22 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <22>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu22_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu23: cpu@23 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <23>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu23_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu24: cpu@24 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <24>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu24_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu25: cpu@25 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <25>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu25_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu26: cpu@26 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <26>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu26_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu27: cpu@27 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <27>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu27_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu28: cpu@28 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <28>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu28_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu29: cpu@29 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <29>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu29_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu30: cpu@30 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <30>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu30_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu31: cpu@31 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <31>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu31_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu32: cpu@32 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <32>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu32_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu33: cpu@33 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <33>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu33_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu34: cpu@34 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <34>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu34_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu35: cpu@35 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <35>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu35_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu36: cpu@36 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <36>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu36_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu37: cpu@37 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <37>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu37_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu38: cpu@38 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <38>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu38_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu39: cpu@39 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <39>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu39_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu40: cpu@40 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <40>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu40_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu41: cpu@41 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <41>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu41_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu42: cpu@42 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <42>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu42_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu43: cpu@43 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <43>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu43_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu44: cpu@44 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <44>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu44_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu45: cpu@45 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <45>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu45_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu46: cpu@46 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <46>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu46_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu47: cpu@47 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <47>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu47_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu48: cpu@48 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <48>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu48_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu49: cpu@49 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <49>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu49_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu50: cpu@50 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <50>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu50_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu51: cpu@51 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <51>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu51_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu52: cpu@52 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <52>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu52_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu53: cpu@53 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <53>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu53_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu54: cpu@54 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <54>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu54_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu55: cpu@55 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <55>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu55_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu56: cpu@56 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <56>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu56_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu57: cpu@57 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <57>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu57_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu58: cpu@58 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <58>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu58_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu59: cpu@59 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <59>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu59_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu60: cpu@60 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <60>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu60_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu61: cpu@61 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <61>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu61_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu62: cpu@62 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <62>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu62_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu63: cpu@63 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm"; + reg =3D <63>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu63_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + l2_cache0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache2: cache-controller-2 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache3: cache-controller-3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache4: cache-controller-4 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache5: cache-controller-5 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache6: cache-controller-6 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache7: cache-controller-7 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache8: cache-controller-8 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache9: cache-controller-9 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache10: cache-controller-10 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache11: cache-controller-11 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache12: cache-controller-12 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache13: cache-controller-13 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache14: cache-controller-14 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache15: cache-controller-15 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi new file mode 100644 index 000000000000..572c24471b87 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/dts-v1/; +#include + +#include "sg2042-cpus.dtsi" + +/ { + compatible =3D "sophgo,sg2042"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + + aliases { + serial0 =3D &uart0; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint_mswi: interrupt-controller@7094000000 { + compatible =3D "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; + reg =3D <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended =3D <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>, + <&cpu4_intc 3>, + <&cpu5_intc 3>, + <&cpu6_intc 3>, + <&cpu7_intc 3>, + <&cpu8_intc 3>, + <&cpu9_intc 3>, + <&cpu10_intc 3>, + <&cpu11_intc 3>, + <&cpu12_intc 3>, + <&cpu13_intc 3>, + <&cpu14_intc 3>, + <&cpu15_intc 3>, + <&cpu16_intc 3>, + <&cpu17_intc 3>, + <&cpu18_intc 3>, + <&cpu19_intc 3>, + <&cpu20_intc 3>, + <&cpu21_intc 3>, + <&cpu22_intc 3>, + <&cpu23_intc 3>, + <&cpu24_intc 3>, + <&cpu25_intc 3>, + <&cpu26_intc 3>, + <&cpu27_intc 3>, + <&cpu28_intc 3>, + <&cpu29_intc 3>, + <&cpu30_intc 3>, + <&cpu31_intc 3>, + <&cpu32_intc 3>, + <&cpu33_intc 3>, + <&cpu34_intc 3>, + <&cpu35_intc 3>, + <&cpu36_intc 3>, + <&cpu37_intc 3>, + <&cpu38_intc 3>, + <&cpu39_intc 3>, + <&cpu40_intc 3>, + <&cpu41_intc 3>, + <&cpu42_intc 3>, + <&cpu43_intc 3>, + <&cpu44_intc 3>, + <&cpu45_intc 3>, + <&cpu46_intc 3>, + <&cpu47_intc 3>, + <&cpu48_intc 3>, + <&cpu49_intc 3>, + <&cpu50_intc 3>, + <&cpu51_intc 3>, + <&cpu52_intc 3>, + <&cpu53_intc 3>, + <&cpu54_intc 3>, + <&cpu55_intc 3>, + <&cpu56_intc 3>, + <&cpu57_intc 3>, + <&cpu58_intc 3>, + <&cpu59_intc 3>, + <&cpu60_intc 3>, + <&cpu61_intc 3>, + <&cpu62_intc 3>, + <&cpu63_intc 3>; + }; + + clint_mtimer0: timer@70ac000000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac000000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + clint_mtimer1: timer@70ac010000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac010000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu4_intc 7>, + <&cpu5_intc 7>, + <&cpu6_intc 7>, + <&cpu7_intc 7>; + }; + + clint_mtimer2: timer@70ac020000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac020000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu8_intc 7>, + <&cpu9_intc 7>, + <&cpu10_intc 7>, + <&cpu11_intc 7>; + }; + + clint_mtimer3: timer@70ac030000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac030000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu12_intc 7>, + <&cpu13_intc 7>, + <&cpu14_intc 7>, + <&cpu15_intc 7>; + }; + + clint_mtimer4: timer@70ac040000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac040000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu16_intc 7>, + <&cpu17_intc 7>, + <&cpu18_intc 7>, + <&cpu19_intc 7>; + }; + + clint_mtimer5: timer@70ac050000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac050000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu20_intc 7>, + <&cpu21_intc 7>, + <&cpu22_intc 7>, + <&cpu23_intc 7>; + }; + + clint_mtimer6: timer@70ac060000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac060000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu24_intc 7>, + <&cpu25_intc 7>, + <&cpu26_intc 7>, + <&cpu27_intc 7>; + }; + + clint_mtimer7: timer@70ac070000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac070000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu28_intc 7>, + <&cpu29_intc 7>, + <&cpu30_intc 7>, + <&cpu31_intc 7>; + }; + + clint_mtimer8: timer@70ac080000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac080000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu32_intc 7>, + <&cpu33_intc 7>, + <&cpu34_intc 7>, + <&cpu35_intc 7>; + }; + + clint_mtimer9: timer@70ac090000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac090000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu36_intc 7>, + <&cpu37_intc 7>, + <&cpu38_intc 7>, + <&cpu39_intc 7>; + }; + + clint_mtimer10: timer@70ac0a0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu40_intc 7>, + <&cpu41_intc 7>, + <&cpu42_intc 7>, + <&cpu43_intc 7>; + }; + + clint_mtimer11: timer@70ac0b0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu44_intc 7>, + <&cpu45_intc 7>, + <&cpu46_intc 7>, + <&cpu47_intc 7>; + }; + + clint_mtimer12: timer@70ac0c0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu48_intc 7>, + <&cpu49_intc 7>, + <&cpu50_intc 7>, + <&cpu51_intc 7>; + }; + + clint_mtimer13: timer@70ac0d0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu52_intc 7>, + <&cpu53_intc 7>, + <&cpu54_intc 7>, + <&cpu55_intc 7>; + }; + + clint_mtimer14: timer@70ac0e0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu56_intc 7>, + <&cpu57_intc 7>, + <&cpu58_intc 7>, + <&cpu59_intc 7>; + }; + + clint_mtimer15: timer@70ac0f0000 { + compatible =3D "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer= "; + reg =3D <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu60_intc 7>, + <&cpu61_intc 7>, + <&cpu62_intc 7>, + <&cpu63_intc 7>; + }; + + intc: interrupt-controller@7090000000 { + compatible =3D "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + reg =3D <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended =3D + <&cpu0_intc 0xffffffff>, <&cpu0_intc 9>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>, + <&cpu5_intc 0xffffffff>, <&cpu5_intc 9>, + <&cpu6_intc 0xffffffff>, <&cpu6_intc 9>, + <&cpu7_intc 0xffffffff>, <&cpu7_intc 9>, + <&cpu8_intc 0xffffffff>, <&cpu8_intc 9>, + <&cpu9_intc 0xffffffff>, <&cpu9_intc 9>, + <&cpu10_intc 0xffffffff>, <&cpu10_intc 9>, + <&cpu11_intc 0xffffffff>, <&cpu11_intc 9>, + <&cpu12_intc 0xffffffff>, <&cpu12_intc 9>, + <&cpu13_intc 0xffffffff>, <&cpu13_intc 9>, + <&cpu14_intc 0xffffffff>, <&cpu14_intc 9>, + <&cpu15_intc 0xffffffff>, <&cpu15_intc 9>, + <&cpu16_intc 0xffffffff>, <&cpu16_intc 9>, + <&cpu17_intc 0xffffffff>, <&cpu17_intc 9>, + <&cpu18_intc 0xffffffff>, <&cpu18_intc 9>, + <&cpu19_intc 0xffffffff>, <&cpu19_intc 9>, + <&cpu20_intc 0xffffffff>, <&cpu20_intc 9>, + <&cpu21_intc 0xffffffff>, <&cpu21_intc 9>, + <&cpu22_intc 0xffffffff>, <&cpu22_intc 9>, + <&cpu23_intc 0xffffffff>, <&cpu23_intc 9>, + <&cpu24_intc 0xffffffff>, <&cpu24_intc 9>, + <&cpu25_intc 0xffffffff>, <&cpu25_intc 9>, + <&cpu26_intc 0xffffffff>, <&cpu26_intc 9>, + <&cpu27_intc 0xffffffff>, <&cpu27_intc 9>, + <&cpu28_intc 0xffffffff>, <&cpu28_intc 9>, + <&cpu29_intc 0xffffffff>, <&cpu29_intc 9>, + <&cpu30_intc 0xffffffff>, <&cpu30_intc 9>, + <&cpu31_intc 0xffffffff>, <&cpu31_intc 9>, + <&cpu32_intc 0xffffffff>, <&cpu32_intc 9>, + <&cpu33_intc 0xffffffff>, <&cpu33_intc 9>, + <&cpu34_intc 0xffffffff>, <&cpu34_intc 9>, + <&cpu35_intc 0xffffffff>, <&cpu35_intc 9>, + <&cpu36_intc 0xffffffff>, <&cpu36_intc 9>, + <&cpu37_intc 0xffffffff>, <&cpu37_intc 9>, + <&cpu38_intc 0xffffffff>, <&cpu38_intc 9>, + <&cpu39_intc 0xffffffff>, <&cpu39_intc 9>, + <&cpu40_intc 0xffffffff>, <&cpu40_intc 9>, + <&cpu41_intc 0xffffffff>, <&cpu41_intc 9>, + <&cpu42_intc 0xffffffff>, <&cpu42_intc 9>, + <&cpu43_intc 0xffffffff>, <&cpu43_intc 9>, + <&cpu44_intc 0xffffffff>, <&cpu44_intc 9>, + <&cpu45_intc 0xffffffff>, <&cpu45_intc 9>, + <&cpu46_intc 0xffffffff>, <&cpu46_intc 9>, + <&cpu47_intc 0xffffffff>, <&cpu47_intc 9>, + <&cpu48_intc 0xffffffff>, <&cpu48_intc 9>, + <&cpu49_intc 0xffffffff>, <&cpu49_intc 9>, + <&cpu50_intc 0xffffffff>, <&cpu50_intc 9>, + <&cpu51_intc 0xffffffff>, <&cpu51_intc 9>, + <&cpu52_intc 0xffffffff>, <&cpu52_intc 9>, + <&cpu53_intc 0xffffffff>, <&cpu53_intc 9>, + <&cpu54_intc 0xffffffff>, <&cpu54_intc 9>, + <&cpu55_intc 0xffffffff>, <&cpu55_intc 9>, + <&cpu56_intc 0xffffffff>, <&cpu56_intc 9>, + <&cpu57_intc 0xffffffff>, <&cpu57_intc 9>, + <&cpu58_intc 0xffffffff>, <&cpu58_intc 9>, + <&cpu59_intc 0xffffffff>, <&cpu59_intc 9>, + <&cpu60_intc 0xffffffff>, <&cpu60_intc 9>, + <&cpu61_intc 0xffffffff>, <&cpu61_intc 9>, + <&cpu62_intc 0xffffffff>, <&cpu62_intc 9>, + <&cpu63_intc 0xffffffff>, <&cpu63_intc 9>; + riscv,ndev =3D <224>; + }; + + uart0: serial@7040000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x00000070 0x40000000 0x00000000 0x00001000>; + interrupt-parent =3D <&intc>; + interrupts =3D <112 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency =3D <500000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49A3CE7C4D4 for ; Wed, 4 Oct 2023 15:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243186AbjJDPoj (ORCPT ); Wed, 4 Oct 2023 11:44:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243184AbjJDPoh (ORCPT ); Wed, 4 Oct 2023 11:44:37 -0400 Received: from mail-oo1-xc2c.google.com (mail-oo1-xc2c.google.com [IPv6:2607:f8b0:4864:20::c2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7269DF2; 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charset="utf-8" From: Chen Wang Milk-V Pioneer [1] is a developer motherboard based on SG2042 in a standard mATX form factor. Currently only support booting into console with only uart enabled, other features will be added soon later. Link: https://milkv.io/pioneer [1] Reviewed-by: Guo Ren Acked-by: Chao Wei Signed-off-by: Chen Wang Acked-by: Chen Wang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 +++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f60a280abb15..72030fd727af 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas subdir-y +=3D sifive +subdir-y +=3D sophgo subdir-y +=3D starfive subdir-y +=3D thead =20 diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/soph= go/Makefile new file mode 100644 index 000000000000..5a471b19df22 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2042-milkv-pioneer.dtb + diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/ris= cv/boot/dts/sophgo/sg2042-milkv-pioneer.dts new file mode 100644 index 000000000000..49b4b9c2c101 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +/ { + model =3D "Milk-V Pioneer"; + compatible =3D "milkv,pioneer", "sophgo,sg2042"; + + chosen { + stdout-path =3D "serial0"; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.25.1 From nobody Sat Jan 3 03:54:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E1E6E7C4D4 for ; Wed, 4 Oct 2023 15:44:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243189AbjJDPo7 (ORCPT ); Wed, 4 Oct 2023 11:44:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243183AbjJDPo5 (ORCPT ); Wed, 4 Oct 2023 11:44:57 -0400 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5E5CBF; Wed, 4 Oct 2023 08:44:54 -0700 (PDT) Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6c496719a9aso11881a34.0; Wed, 04 Oct 2023 08:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696434294; x=1697039094; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kwHNGoN1oEuVN/+gC7YBu4Zfb31gkQocRcnObhIezIA=; b=d6nDYOum5YolPH/sYYh3agvMp6vyV8hUndBoS1pTmHF6fKOu9cEF9YGj4McJT17W1v /kMFHJ6oLG/J436NMKR72uY2HqWZ+XQkVFnr0ktWXvEsEscfVGtXaxQFfE5vFsMijnfc ehlEpJ7M2yAWf/eMqCTcWT/NrMnhyRrcPYbVHF1U9NHh4TiG3r0rfaX34JCXwJQhxfm6 LQh0hSbwHj1ryfuBkaX+7ko7wNkCUmSmsxtatRaoM5Vp4awlENDMK+0lZeh+qKdFpW9M HeHhFzx+UdSd3Tugdxujm/EPV2wem3BTwOUq2hDO+sLNiPWyh1d+qJQJ95F8SCFyKIj6 AMJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696434294; x=1697039094; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kwHNGoN1oEuVN/+gC7YBu4Zfb31gkQocRcnObhIezIA=; b=v3o3cvXvAHe0p4cynI+yXc+ZSKXl0GexXGMZlmN4ZkX0j6/gQnGWyctJmZJ6gp+0cK Oki3WDrJ8Tjoo4ONS/XeWMue49of2md7gAd1jeZPUF8iNU4fXezaRs53weMQ56MGFjCS TWbtlR36X8WimVVaddZctR31BzaVepe36ggV1LAYOgWeVuaEnI3kioJqFPZ0eR5TlyDz DdFU24NX8ek/ARhg6VN8at08WCnLJOr8i/L+TUQoMijDlfAks/wN7En9sUyZ6Yr+HETE kQR2tFZKIj3N7CQc7uW+yglih/DQfOGrPmhP7YdnlW63y/9AnkpLeumWd7kIJ1Rm7xfg O0qQ== X-Gm-Message-State: AOJu0YzicAy6q/ntFvy6a44CrYQ3+tQ0yo3uszmfxpNiiKSiXa+Z5Uk+ J32sBIeWngz//8zGs3QXYG0= X-Google-Smtp-Source: AGHT+IHGDDRxpV/qn3OPuFLyzArlhshBtITnJ27A864nZkqqFJtvwGuAVG0g+WparjujNcqwpJR9eg== X-Received: by 2002:a9d:469e:0:b0:6c7:af2e:bf6d with SMTP id z30-20020a9d469e000000b006c7af2ebf6dmr1608528ote.19.1696434294052; Wed, 04 Oct 2023 08:44:54 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id m2-20020a9d6ac2000000b006b96a4287d4sm492050otq.5.2023.10.04.08.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:44:53 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley Subject: [PATCH v4 10/10] riscv: defconfig: enable SOPHGO SoC Date: Wed, 4 Oct 2023 23:44:46 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Chen Wang Enable SOPHGO SoC config in defconfig to allow the default upstream kernel to boot on Milk-V Pioneer board. Acked-by: Chao Wei Acked-by: Conor Dooley Reviewed-by: Guo Ren Signed-off-by: Chen Wang Acked-by: Chen Wang --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..bf737cfa1d2c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=3Dy CONFIG_SOC_STARFIVE=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_SOC_VIRT=3Dy +CONFIG_ARCH_SOPHGO=3Dy CONFIG_SMP=3Dy CONFIG_HOTPLUG_CPU=3Dy CONFIG_PM=3Dy --=20 2.25.1