From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37933E810B1 for ; Wed, 27 Sep 2023 08:58:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbjI0I6b (ORCPT ); Wed, 27 Sep 2023 04:58:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230127AbjI0I6Y (ORCPT ); Wed, 27 Sep 2023 04:58:24 -0400 Received: from mail-oa1-x2c.google.com (mail-oa1-x2c.google.com [IPv6:2001:4860:4864:20::2c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F8A1193; Wed, 27 Sep 2023 01:58:21 -0700 (PDT) Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1dd54aca17cso2559845fac.3; Wed, 27 Sep 2023 01:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805101; x=1696409901; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YZTi49m1tRqik4s4OIHpvu+DZ0pGT5ycjrh8hjwTA/U=; b=aDF7+gdCEH4nyH72m9/EVkkUlDwJY/EfZuQun+GC4CkZFlEkg1y/zFiSBoiZzQuN/e x7aty8NEOpxPUyPUnYsKiE4etNEmOr2Bdx3SZ3drKvv9WRc/mU9qseDcFwddTfjfXf0D XWIhhIoAUydQcw90a/GC1YG0RCC8AIwSLh0AjUBb97lCF1s0U7P+xWvMzMEn9hLPxgs5 iJ0SMoCwfjsFdJaLqKvZtp69YAVQS1TLZhP57QxYQq1xfq9dYoOkN7ntMK8nw3zAqTzL gbzG9mh+RiSuptTWpGISE9WLnvvXM9mLShH3Oa7LZ0RKnlSj4tNiAFkQbkZDnWUYsSeR Ikww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805101; x=1696409901; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YZTi49m1tRqik4s4OIHpvu+DZ0pGT5ycjrh8hjwTA/U=; b=YVYSm2LsOrdjqhX8mz/bLaBXHJ5aKaYKjhV0s3zzxtvHBD3w126U0WEUxNu2/MWWcO JaLiHSsUvXrRdCnmO26r9eOz+YKfTva9Y0kMbFhXX/8ia//uI/cNpyzb8l2YfAiQhumA qrUKEdM+hb2+Bu+5zmUvg9q33HrQGRM0FCJ7gAlpWf6GeBoNjRDiPtKk7a0VwvGTbgZY DLjvQ/6DChx895aoyXfdMLDchPisAnH5fUNQIc5UI0AJ+wJz2akIHFgmdEKTP5cCpy1j pe9vyHoGBQGdQU/U+Of9Icb0MB+TaXydZDec+X2nydsB1B49hB791IbwTGhmi7XDUvMd teyA== X-Gm-Message-State: AOJu0YxplEZEJSNZLKcNpKZcPaebWsrw1p+JbKQwyWQW6aVYI7hTSgXQ vS50h+Ns8mXVbbg7s4mBXxY= X-Google-Smtp-Source: AGHT+IFNIFoEp/iqGlH0vzf3/98sK4WLJfvo5ZvA9UZ3xKUBz6DBslOPOxQslranSCHUMX3oMfyKhQ== X-Received: by 2002:a05:6870:46a5:b0:1dd:651a:7398 with SMTP id a37-20020a05687046a500b001dd651a7398mr1767181oap.2.1695805100614; Wed, 27 Sep 2023 01:58:20 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id v3-20020a056870e28300b001dcde628a6fsm1962325oad.42.2023.09.27.01.58.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 01:58:20 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley , Chen Wang Subject: [PATCH v3 01/11] riscv: Add SOPHGO SOC family Kconfig support Date: Wed, 27 Sep 2023 16:58:12 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V cores. Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Acked-by: Chao Wei Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 6833d01e2e70..d4df7b5d0f16 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -22,6 +22,11 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. =20 +config ARCH_SOPHGO + bool "Sophgo SoCs" + help + This enables support for Sophgo SoC platform hardware. + config ARCH_STARFIVE def_bool SOC_STARFIVE =20 --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FF9CE810A8 for ; Wed, 27 Sep 2023 09:00:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229666AbjI0JAv (ORCPT ); Wed, 27 Sep 2023 05:00:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230376AbjI0JAk (ORCPT ); Wed, 27 Sep 2023 05:00:40 -0400 Received: from mail-oi1-x232.google.com (mail-oi1-x232.google.com [IPv6:2607:f8b0:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DBCE1B3; Wed, 27 Sep 2023 02:00:35 -0700 (PDT) Received: by mail-oi1-x232.google.com with SMTP id 5614622812f47-3ae0135c4deso6226966b6e.3; Wed, 27 Sep 2023 02:00:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805235; x=1696410035; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tiV1ULQG3s0x2nlhHANe2aPzX+bV/lE/JH9vnJWbNSw=; b=WZQlqWb6Qze7sgt7+nLKOCihhdk4Hl9jzQBar+niynpsP0Yg+u2MqalCV8hXS/d4Kd LbqRZvP/cRNEJAVydacNP7M0Pjh2nuMLDqFlr0NIdVrhw5tHdV9StAqY+22Xtdxvk7FP U+h9o16Y0vXOJ1K3pT2P/Sd7zWgRgSM2w2j6b3kzHLoTQh2YDgFFns7FoNO9cS8l870u 9vq+jo3NWDkho3+tMw/Kf+Ip+VTTYDI4azOxoGuX5oRB+96hluYvu4bvm3RXFhcvFCRG untWG534LNq94lgsS7htuSoWyr6m+LPVTfYg4682q9HtTw0BqDe0CMVzng3jjVXoy01f SkZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805235; x=1696410035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tiV1ULQG3s0x2nlhHANe2aPzX+bV/lE/JH9vnJWbNSw=; b=NUdBb4tr7OcgtrobfYFpbQrNXgdQQeVyzYh+21LlzsATGzduvYuWIfiISRZ1Im2SaF 7fPTdtJlYqH3DUypqUfT5C/emOsIYgb5akucn/K6xTIQEGgrn1iGxoV1XCbVmu/ZmpOy If0sqGfCgj2BArQSCvtPY2V/lBROfYyZOJRSOfqijXxAAu9nLfVabS0ZaawuN9062CzZ UBDZjNgMgdKyu+Qe8nwHS8C/zTq7kdeTzifdD4Yhds0DklBYif53DSswwmbkwslz/rVW y6t9HBGAAhBBzV4kMhyX4i4yAjZLChyCELon8Tkwl7p3zecx5aJ0O7hPr6LVfPB98vi/ wbHw== X-Gm-Message-State: AOJu0YwLv4XDvGOTPoPyjt3GKa4G1iwlnSk0oGGiOIqm4lqn7a+H9zP3 nPYWJWVs6Ln8vlKZnBzNpDg= X-Google-Smtp-Source: AGHT+IHRLsiqqvilGXV7akKllvlYz9S+uorAcdH6PSFC8vgoeHy/ik7nsmsja3IemwyAGE0aqJ/3KQ== X-Received: by 2002:a05:6870:819c:b0:1dc:a055:8587 with SMTP id k28-20020a056870819c00b001dca0558587mr1850005oae.6.1695805234798; Wed, 27 Sep 2023 02:00:34 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id kr9-20020a0568719ec900b001dd60c202e6sm766131oac.10.2023.09.27.02.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:00:34 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley , Chen Wang Subject: [PATCH v3 02/11] dt-bindings: vendor-prefixes: add milkv/sophgo Date: Wed, 27 Sep 2023 17:00:27 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add new vendor strings to dt bindings. These new vendor strings are used by - SOPHGO's SG2042 SoC [1] - Milk-V Pioneer board [2], which uses SG2042 chip. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Link: https://milkv.io/pioneer [2] Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Acked-by: Chao Wei Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 573578db9509..fcca9e070a9a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -863,6 +863,8 @@ patternProperties: description: MikroElektronika d.o.o. "^mikrotik,.*": description: MikroTik + "^milkv,.*": + description: MilkV Technology Co., Ltd "^miniand,.*": description: Miniand Tech "^minix,.*": @@ -1273,6 +1275,8 @@ patternProperties: description: Solomon Systech Limited "^sony,.*": description: Sony Corporation + "^sophgo,.*": + description: Sophgo Technology Inc. "^sourceparts,.*": description: Source Parts Inc. "^spansion,.*": --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5527AE810A8 for ; Wed, 27 Sep 2023 09:01:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230370AbjI0JBD (ORCPT ); Wed, 27 Sep 2023 05:01:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230093AbjI0JAz (ORCPT ); Wed, 27 Sep 2023 05:00:55 -0400 Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C1D1E4; Wed, 27 Sep 2023 02:00:51 -0700 (PDT) Received: by mail-oo1-xc34.google.com with SMTP id 006d021491bc7-57b67c84999so5802527eaf.3; Wed, 27 Sep 2023 02:00:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805250; x=1696410050; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7XISMEEuxEHPo83QIpIC+HgJvoMzURdyaENZ58w85qI=; b=CGR+lIq5OSV9XYx14v6wjV/eKN2YfOm6WfMbHNp6of8dCG6vyhAAppv9G5L4WgyHWm 5sfv8W9tWTUQi+Kr0jVMRF8aDs4/wyOtUOO7V6f/vRs9SVJg0QpVhfBb0aM4IrE0bBOL 8hM57H2GUOplNCHcHpVrytVZTtMozalx53mD6bAd3aU+iJqCx+opNzcAh3uoIeaoEFal ieoIDXpBwyC0FweU0C73Ccds1WgYjIgWlKlRrSTG3Hl0DcQ5r4u+lxvH2bLoYZfjsErY x5VR/Nt0pevaaog3ab62b922yxT6y8im5F6xpfINkwSnmo33WDwx5r4d6dXZ1A/z/d7q mxFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805250; x=1696410050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7XISMEEuxEHPo83QIpIC+HgJvoMzURdyaENZ58w85qI=; b=alyGRxWsmQivBhQ7ivOTVZtvjB6jyzysXw3zAmlEzL0PGBtFl45wKCbUQXO5g1OhJS CIwdZjYcEiDyJ099rCgkiGC80jz+F8Ef1c/yquB1c9Yk8Ucnb0e5SUgFru1FHBfT0L+n BgQErZui3ARPwBw0dIazBapUTpf9L8UMsvoCtqpcFrjfjCoxjVBftJWyX4yHnAt/LwuC mpuKDTfDEW1EmuvzcAHtvh5uSxe+zCJGqUFFA8BbwgoQYDYwmjgd+9mvbd3mnfl9fYJ6 7EA7jpzHBuOT0H3C8iTnMORUELdgY0ZzMjNQs/pf0WRPMaqesUhDYcaUR4mKhR9NHQuE emww== X-Gm-Message-State: AOJu0YxKdJ8PKlWut7z2FSKC23denJd6DSX0+5jmM4y+eeDBe22K9jgL rosr0MkVxhU/2RL16BvvpHU= X-Google-Smtp-Source: AGHT+IFUyHthVzniBAXCYOq3vUTRDSWKmjX+zEks2b8BgJUOzB+OHdp/JRDiqWdgmgmIiIaljSSsbw== X-Received: by 2002:a4a:6c58:0:b0:57b:6ab1:87c9 with SMTP id u24-20020a4a6c58000000b0057b6ab187c9mr1523375oof.0.1695805250702; Wed, 27 Sep 2023 02:00:50 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id f128-20020a4a5886000000b0057bb326cad4sm1373103oob.33.2023.09.27.02.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:00:50 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Krzysztof Kozlowski , Chen Wang Subject: [PATCH v3 03/11] dt-bindings: riscv: add sophgo sg2042 bindings Date: Wed, 27 Sep 2023 17:00:42 +0800 Message-Id: <97c14be89af91d47e4d7b2313d7348ca12f393fd.1695804418.git.unicornxw@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the SOPHGO's SG2042 Soc [1] and the Milk-V Pioneer board [2]. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Link: https://milkv.io/pioneer [2] Acked-by: Chao Wei Reviewed-by: Guo Ren Reviewed-by: Krzysztof Kozlowski Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../devicetree/bindings/riscv/sophgo.yaml | 28 +++++++++++++++++++ MAINTAINERS | 6 ++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Document= ation/devicetree/bindings/riscv/sophgo.yaml new file mode 100644 index 000000000000..4e8fd3c6a6ff --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sophgo.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SoC-based boards + +maintainers: + - Chao Wei + - Chen Wang + +description: + Sophgo SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - milkv,pioneer + - const: sophgo,sg2042 + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..9114a14ce991 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20063,6 +20063,12 @@ F: drivers/char/sonypi.c F: drivers/platform/x86/sony-laptop.c F: include/linux/sony-laptop.h =20 +SOPHGO DEVICETREES +M: Chao Wei +M: Chen Wang +S: Maintained +F: Documentation/devicetree/bindings/riscv/sophgo.yaml + SOUND M: Jaroslav Kysela M: Takashi Iwai --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AD87E810A8 for ; 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Wed, 27 Sep 2023 02:01:08 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id ms17-20020a0568706b9100b001dd842cc563sm402554oab.26.2023.09.27.02.01.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:01:08 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley , Chen Wang Subject: [PATCH v3 04/11] dt-bindings: riscv: Add T-HEAD C920 compatibles Date: Wed, 27 Sep 2023 17:01:01 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The C920 is RISC-V CPU cores from T-HEAD Semiconductor. Notably, the C920 core is used in the SOPHGO's SG2042 SoC. Acked-by: Chao Wei Reviewed-by: Guo Ren Reviewed-by: Conor Dooley Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index 38c0b5213736..185a0191bad6 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -47,6 +47,7 @@ properties: - sifive,u74-mc - thead,c906 - thead,c910 + - thead,c920 - const: riscv - items: - enum: --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 276A3E810C3 for ; Wed, 27 Sep 2023 10:40:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230414AbjI0Kk3 (ORCPT ); Wed, 27 Sep 2023 06:40:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230427AbjI0JB3 (ORCPT ); Wed, 27 Sep 2023 05:01:29 -0400 Received: from mail-ot1-x335.google.com (mail-ot1-x335.google.com [IPv6:2607:f8b0:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E70DE1B8; Wed, 27 Sep 2023 02:01:27 -0700 (PDT) Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6c4e38483d2so3663475a34.1; Wed, 27 Sep 2023 02:01:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805287; x=1696410087; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YppGQzKW+2r3xnb53t/LIH/j9u+a8juMyAfNzTVGTww=; b=NldFDpBBn60FCAYIJRrEmfoy5lzUR1VFIEjsWbZZRE5jddU6ZnfJmPg8F8V3dBsNLn 6LGm3eTpQreP5bjnbSmflLfQ2Y+6uI724rbypNuY4funQIjGOwRQIq+j99AuStxa4iDP 91DPD8XVnLscK+GRUlW5nkBauAT2dY8fGyRf8Cf2EIOIkLtCZ/uTulFmNiFI4grd/NbS HkO66aJISrqtR0bRfkdCIursT1KzG5oX9aWvmw80XMwabU4JNXYlKsUpqwAUl66TfUL1 l31X/lNfckTO+rLS27yTNQHR45r9Y9uDnKtxh/91uSfwRgz4ucpx+yiZGQK7v1fpRRdL +Jlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805287; x=1696410087; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YppGQzKW+2r3xnb53t/LIH/j9u+a8juMyAfNzTVGTww=; b=kru+Mmd5SXt4g4c64I2zWtzMk5kXHQ8IcwCazEeGw+VGTbAcJsvoEHSk8TEqsg5kM+ S3hq9/AOzG7Lp7GPf8sfd3+yjmb3Q5XrBkIqm7+ao6Hjy/OMmN/f0RNjLB9Jn99YY8nw JtXc4lnU16PviIHri8Wjyl/mvDPKFfyS4m7oFdH+Z6Q+x8vuFz6jrJ/3n6vu7AoPe0CE SpPkvofAx9rE5gkQzc4tmrd/zqcwjktHF3BwwwG6A0D1bVOAIeQ1nH2Xwvu6o3Hb33Lx 54e84+fX0ATS7boudxfa3ywAdcCda61KkgkwhfXtRKn01oyNjqHxsonTgvPy+HxiJf7Y bstQ== X-Gm-Message-State: AOJu0Yxa4kVTka4uIw2RmLCFNSNaLvZo3WJFmTxuQVgmHL7NR1bxKXIB 97oUueun/bRO+vxI19hZZcu0YSYAXQXqMQ== X-Google-Smtp-Source: AGHT+IES/qcWO76tOeeuoIlprC1dblIRpibZEH/5iy8gCVaskuyWvzti7QClb5q84LqsaWehVwQJ/w== X-Received: by 2002:a9d:4f12:0:b0:6c4:a30c:f3f1 with SMTP id d18-20020a9d4f12000000b006c4a30cf3f1mr1566244otl.19.1695805286685; Wed, 27 Sep 2023 02:01:26 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id w1-20020a9d5381000000b006c4e2f00135sm1086568otg.28.2023.09.27.02.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:01:26 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley , Chen Wang Subject: [PATCH v3 05/11] dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC Date: Wed, 27 Sep 2023 17:01:19 +0800 Message-Id: <8fb6f431928271bf9d5d4bba204729efdd12669a.1695804418.git.unicornxw@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for SOPHGO SG2042 plic. Acked-by: Chao Wei Reviewed-by: Guo Ren Acked-by: Conor Dooley Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index dc1f28e55266..16f9c4760c0f 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic - items: --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E497E810AD for ; Wed, 27 Sep 2023 09:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbjI0JBx (ORCPT ); Wed, 27 Sep 2023 05:01:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229486AbjI0JBr (ORCPT ); Wed, 27 Sep 2023 05:01:47 -0400 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89D9BA3; Wed, 27 Sep 2023 02:01:46 -0700 (PDT) Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6c4b9e09521so5412175a34.3; Wed, 27 Sep 2023 02:01:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805306; x=1696410106; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PXIpE3t2S5hvGBlA4qF3kN7EACJyW+Do/rfIdtRkLUc=; b=Qgbj+kDXSNrOL8+s6qH8JiM/QySkP4ucirf4cglRfmHJ9S8E7oViI4WSsT8CJI080D sts0dsgt+bLb7ej2Y8dn6dWId9Hofltb1y7vpqSu+iM19rf31/9bDWYxY6PLqfcy2/1q e4SMXnNTpH4UN+eEIrJiTfnNsyBHDUuJDX3UG4Gh03ADRwH2NiX44eOqmsXc6hnFshl8 ZXCeAE8IMOVDx1fJ+a8Nw/RPVQK2NGOEa3tj9U004eqQctdrv3KMbg6VSyYytUW2/XVA UsssapRIKFwxktpG+xKM38SwuxFzRf/k0VYWP3M1WxE0wOFFIhIW+EuDE04R3iqYQNsE j+YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805306; x=1696410106; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PXIpE3t2S5hvGBlA4qF3kN7EACJyW+Do/rfIdtRkLUc=; b=ZGj232M1gjT12CEBDy5GFQ5AGk7q7RCcJkp8cxgnlkmjmZ45Et7YsO+B3mHmBMg+cp aMt944K/SLZwTkLWPkAUawQjS4qpzShofwkjAh7Vx1xuuKu6avC4wf4dupsOKsaCVXE5 179DJHWUy35YESqKzp8wF6LbCQBHmtkQoxUHAGe4Wy4P8kMXnm0lcXHx8RH7WH8YgEeg 5Bb54qTKUl/cXQ3IMXze6V1VIj/2YwejZhiNY+sr3rwG5wXwQM0cf4+Y5Nr00D73HVgQ v2ow6DfiwwOL7R9ChGNrSUTOOh8SVEEMr1ZwSWZMg3t1JN2DLloLkTiAY6kNEfA1X30q WKNQ== X-Gm-Message-State: AOJu0YzKkmlZWpqWatIBqtmrTBZkIvsISmDjE5YfnhbUCDRM5qqAB3GN NbMNs/WCsdrNrR/Ks9LtdYIKnVuxiO7AOA== X-Google-Smtp-Source: AGHT+IGIIPx7LpmWuBAwJyMC+B4D+B7f2hNQ3krtTefomBIb8tOVeWEMPZHi106hegZJOgN1jP48zA== X-Received: by 2002:a05:6830:1291:b0:6c4:cdce:5de8 with SMTP id z17-20020a056830129100b006c4cdce5de8mr1517090otp.26.1695805305760; Wed, 27 Sep 2023 02:01:45 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id t7-20020a05683022e700b006b9b0a08fdasm2312157otc.59.2023.09.27.02.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:01:45 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Inochi Amaoto , Chen Wang , Chen Wang Subject: [PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer Date: Wed, 27 Sep 2023 17:01:37 +0800 Message-Id: <6e263430685732a4f354b45396c7422a37440ac8.1695804418.git.unicornxw@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Inochi Amaoto The clint of Sophgo sg2042 is incompatible with the standard sifive clint, as the timer and ipi device on the different address, and can not be handled by the sifive,clint DT. In addition, the timers of sg2042 are mapped by per cluster, which is hard to merge with its ipi device. To avoid conficts caused by using the same clint compatible string when this device is parsed by SBI, add a new vendor specific compatible string to identify the timer of sg2042 soc. Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../timer/sophgo,sg2042-clint-mtimer.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-c= lint-mtimer.yaml diff --git a/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mt= imer.yaml b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mti= mer.yaml new file mode 100644 index 000000000000..5da0947d048a --- /dev/null +++ b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.ya= ml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CLINT Timer + +maintainers: + - Inochi Amaoto + +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mtimer + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + timer@ac000000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + interrupts-extended =3D <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>, + <&cpu4intc 7>; + reg =3D <0xac000000 0x00010000>; + }; +... --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43D95E810AD for ; Wed, 27 Sep 2023 09:02:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230127AbjI0JCO (ORCPT ); Wed, 27 Sep 2023 05:02:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230329AbjI0JCG (ORCPT ); Wed, 27 Sep 2023 05:02:06 -0400 Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A387E4; Wed, 27 Sep 2023 02:02:04 -0700 (PDT) Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-3ae2f8bf865so4995311b6e.2; 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charset="utf-8" From: Inochi Amaoto Like the timer of Sophgo sg2042 clint. The machine-level software interrupt device (mswi) of sg2042 clint have the same problem when dealing with the standard sifive clint. To avoid the same conficts as the timer of sg2042 clint, also add the vendor specific compatible string to identify the mswi of sg2042 clint. Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../sophgo,sg2042-clint-mswi.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= sophgo,sg2042-clint-mswi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,= sg2042-clint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-contro= ller/sophgo,sg2042-clint-mswi.yaml new file mode 100644 index 000000000000..a79c4c3db3b3 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= clint-mswi.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-clin= t-mswi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device + +maintainers: + - Inochi Amaoto + +properties: + compatible: + oneOf: + - items: + - const: sophgo,sg2042-clint-mswi + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 4095 + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@94000000 { + compatible =3D "sophgo,sg2042-clint-mswi"; + interrupts-extended =3D <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>, + <&cpu4intc 3>; + reg =3D <0x94000000 0x00010000>; + }; +... --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B864CE810A8 for ; Wed, 27 Sep 2023 09:02:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229930AbjI0JCb (ORCPT ); Wed, 27 Sep 2023 05:02:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230386AbjI0JCY (ORCPT ); Wed, 27 Sep 2023 05:02:24 -0400 Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 76A4EA3; Wed, 27 Sep 2023 02:02:20 -0700 (PDT) Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1dceaa7aeffso3555726fac.0; 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charset="utf-8" Add two dt-binding files which will be maintained by SOPHGO DEVICETREES. Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 9114a14ce991..3fed8e3d273f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20067,7 +20067,9 @@ SOPHGO DEVICETREES M: Chao Wei M: Chen Wang S: Maintained +F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-cl= int-mswi.yaml F: Documentation/devicetree/bindings/riscv/sophgo.yaml +F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml =20 SOUND M: Jaroslav Kysela --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0C8BE810B1 for ; Wed, 27 Sep 2023 09:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbjI0JCt (ORCPT ); Wed, 27 Sep 2023 05:02:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbjI0JCl (ORCPT ); Wed, 27 Sep 2023 05:02:41 -0400 Received: from mail-oi1-x22c.google.com (mail-oi1-x22c.google.com [IPv6:2607:f8b0:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0828BDE; Wed, 27 Sep 2023 02:02:36 -0700 (PDT) Received: by mail-oi1-x22c.google.com with SMTP id 5614622812f47-3af3ecdf047so717445b6e.0; Wed, 27 Sep 2023 02:02:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805355; x=1696410155; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3UkW0ME77tEdP9jqhtFX+dKSGmkZo+pd7VelBukenYI=; b=XlKWSuXMuiA3uBHerbsHEbM3JtRnObDFD+JnOnFN4b3KckmNgqn9AoyuEPQ48OPkaZ 2HFDXI/kxht6+iaAvU/Le813EnbV9ApF8SCj9/6lH4kjSTGR8dfFNlqCGhPYU68ZFX4z puZNR6qMYfPqQq7EZ746t3WZx4h/UfLtF9f/B/hCPZYA5VadW74ky+Jvf51QF5lKy7QO hiwDMubEswT0P8ACCo3YxSnSNr7TgmZGVoKYvFu0jSbl3i0agEDXyRFNY1v9LKl01pS6 o+YRWlulY2OGDyoBH2Kp5HVPIZgKw4sgHjUBZBVyn0c84Fslb1fNsXhK+aHyuINVzRoJ ZP5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805355; x=1696410155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3UkW0ME77tEdP9jqhtFX+dKSGmkZo+pd7VelBukenYI=; b=BiDwLQ3fh+j/Vymb968OdRs5LY7IFno9TUIoRJMq33PwsN9j1kzm/DqnorMETEpBQm CdWhVItwxEM8ODMFy6aLc/Na/0g1KttN96sZ6ectNelTbKR6cfQMUxj76oC2/YVHLXlw JB7vr8v3wDwOphHIgatkVV6cbtnBzWqe9UNZXzOfEdJWQf4IKlI1i8aTfn2YrSU/aRPV DQYJRxPAATff71/La2Wlne1T3wa8QoTblWKWuyXsi/G9LdfmdivRwOBq//NuCFUFTRAo 9rD6NVW2uN9hL68wxQN3Bi7TncnVw3SdccjQqcPmhCoTdaNGUdGvRJm6B2U6HHNioWKz jGsQ== X-Gm-Message-State: AOJu0Yz/s+dqRFmg5JSg1ZmEqOnTy9REtHiAeL5lvCW+X31rC2DsmaWw g265GzqWQSIeXsUJkizb2VI= X-Google-Smtp-Source: AGHT+IE/99mLMAzQlR4fHjMMV76ZqLqyB7Fu5dHtGFVBvbPxLObYxaS0tObe1MB1bseOGLarW1Amyg== X-Received: by 2002:a05:6808:242:b0:3a8:1727:5af4 with SMTP id m2-20020a056808024200b003a817275af4mr1554414oie.24.1695805354874; Wed, 27 Sep 2023 02:02:34 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id ca15-20020a056830610f00b006b9443ce478sm2177602otb.27.2023.09.27.02.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:02:34 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Inochi Amaoto , Chen Wang Subject: [PATCH v3 09/11] riscv: dts: add initial Sophgo SG2042 SoC device tree Date: Wed, 27 Sep 2023 17:02:26 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Milk-V Pioneer motherboard is powered by SG2042. SG2042 is server grade chip with high performance, low power consumption and high data throughput. Key features: - 64 RISC-V cpu cores - 4 cores per cluster, 16 clusters on chip - More info is available at [1]. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Currently only support booting into console with only uart, other features will be added soon later. Reviewed-by: Guo Ren Acked-by: Chao Wei Co-developed-by: Xiaoguang Xing Signed-off-by: Xiaoguang Xing Co-developed-by: Inochi Amaoto Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- MAINTAINERS | 1 + arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 1880 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 ++++ 3 files changed, 2206 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index 3fed8e3d273f..08f8fabb54b1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20067,6 +20067,7 @@ SOPHGO DEVICETREES M: Chao Wei M: Chen Wang S: Maintained +F: arch/riscv/boot/dts/sophgo/ F: Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-cl= int-mswi.yaml F: Documentation/devicetree/bindings/riscv/sophgo.yaml F: Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/= dts/sophgo/sg2042-cpus.dtsi new file mode 100644 index 000000000000..d2348acea527 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -0,0 +1,1880 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/* + * c920 declares "rv64gcv", but the version of it's v-ext + * is 0.7.1. It's not supported by kernel so we remove "v". + */ +#define ISA_BASE "rv64i" +#define ISA_EXTENSIONS \ + "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", "zihpm" + +/ { + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <50000000>; + + cpu-map { + socket0 { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + core1 { + cpu =3D <&cpu1>; + }; + core2 { + cpu =3D <&cpu2>; + }; + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + core1 { + cpu =3D <&cpu5>; + }; + core2 { + cpu =3D <&cpu6>; + }; + core3 { + cpu =3D <&cpu7>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu16>; + }; + core1 { + cpu =3D <&cpu17>; + }; + core2 { + cpu =3D <&cpu18>; + }; + core3 { + cpu =3D <&cpu19>; + }; + }; + + cluster3 { + core0 { + cpu =3D <&cpu20>; + }; + core1 { + cpu =3D <&cpu21>; + }; + core2 { + cpu =3D <&cpu22>; + }; + core3 { + cpu =3D <&cpu23>; + }; + }; + + cluster4 { + core0 { + cpu =3D <&cpu8>; + }; + core1 { + cpu =3D <&cpu9>; + }; + core2 { + cpu =3D <&cpu10>; + }; + core3 { + cpu =3D <&cpu11>; + }; + }; + + cluster5 { + core0 { + cpu =3D <&cpu12>; + }; + core1 { + cpu =3D <&cpu13>; + }; + core2 { + cpu =3D <&cpu14>; + }; + core3 { + cpu =3D <&cpu15>; + }; + }; + + cluster6 { + core0 { + cpu =3D <&cpu24>; + }; + core1 { + cpu =3D <&cpu25>; + }; + core2 { + cpu =3D <&cpu26>; + }; + core3 { + cpu =3D <&cpu27>; + }; + }; + + cluster7 { + core0 { + cpu =3D <&cpu28>; + }; + core1 { + cpu =3D <&cpu29>; + }; + core2 { + cpu =3D <&cpu30>; + }; + core3 { + cpu =3D <&cpu31>; + }; + }; + + cluster8 { + core0 { + cpu =3D <&cpu32>; + }; + core1 { + cpu =3D <&cpu33>; + }; + core2 { + cpu =3D <&cpu34>; + }; + core3 { + cpu =3D <&cpu35>; + }; + }; + + cluster9 { + core0 { + cpu =3D <&cpu36>; + }; + core1 { + cpu =3D <&cpu37>; + }; + core2 { + cpu =3D <&cpu38>; + }; + core3 { + cpu =3D <&cpu39>; + }; + }; + + cluster10 { + core0 { + cpu =3D <&cpu48>; + }; + core1 { + cpu =3D <&cpu49>; + }; + core2 { + cpu =3D <&cpu50>; + }; + core3 { + cpu =3D <&cpu51>; + }; + }; + + cluster11 { + core0 { + cpu =3D <&cpu52>; + }; + core1 { + cpu =3D <&cpu53>; + }; + core2 { + cpu =3D <&cpu54>; + }; + core3 { + cpu =3D <&cpu55>; + }; + }; + + cluster12 { + core0 { + cpu =3D <&cpu40>; + }; + core1 { + cpu =3D <&cpu41>; + }; + core2 { + cpu =3D <&cpu42>; + }; + core3 { + cpu =3D <&cpu43>; + }; + }; + + cluster13 { + core0 { + cpu =3D <&cpu44>; + }; + core1 { + cpu =3D <&cpu45>; + }; + core2 { + cpu =3D <&cpu46>; + }; + core3 { + cpu =3D <&cpu47>; + }; + }; + + cluster14 { + core0 { + cpu =3D <&cpu56>; + }; + core1 { + cpu =3D <&cpu57>; + }; + core2 { + cpu =3D <&cpu58>; + }; + core3 { + cpu =3D <&cpu59>; + }; + }; + + cluster15 { + core0 { + cpu =3D <&cpu60>; + }; + core1 { + cpu =3D <&cpu61>; + }; + core2 { + cpu =3D <&cpu62>; + }; + core3 { + cpu =3D <&cpu63>; + }; + }; + }; + }; + + cpu0: cpu@0 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <0>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <1>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <2>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <3>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache0>; + mmu-type =3D "riscv,sv39"; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu4: cpu@4 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <4>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu5: cpu@5 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <5>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu6: cpu@6 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <6>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu6_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu7: cpu@7 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <7>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache1>; + mmu-type =3D "riscv,sv39"; + + cpu7_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu8: cpu@8 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <8>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu8_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu9: cpu@9 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <9>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu9_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu10: cpu@10 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <10>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu10_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu11: cpu@11 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <11>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache4>; + mmu-type =3D "riscv,sv39"; + + cpu11_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu12: cpu@12 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <12>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu12_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu13: cpu@13 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <13>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu13_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu14: cpu@14 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <14>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu14_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu15: cpu@15 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <15>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache5>; + mmu-type =3D "riscv,sv39"; + + cpu15_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu16: cpu@16 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <16>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu16_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu17: cpu@17 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <17>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu17_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu18: cpu@18 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <18>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu18_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu19: cpu@19 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <19>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache2>; + mmu-type =3D "riscv,sv39"; + + cpu19_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu20: cpu@20 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <20>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu20_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu21: cpu@21 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <21>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu21_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu22: cpu@22 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <22>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu22_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu23: cpu@23 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <23>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache3>; + mmu-type =3D "riscv,sv39"; + + cpu23_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu24: cpu@24 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <24>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu24_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu25: cpu@25 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <25>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu25_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu26: cpu@26 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <26>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu26_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu27: cpu@27 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <27>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache6>; + mmu-type =3D "riscv,sv39"; + + cpu27_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu28: cpu@28 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <28>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu28_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu29: cpu@29 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <29>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu29_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu30: cpu@30 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <30>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu30_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu31: cpu@31 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <31>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache7>; + mmu-type =3D "riscv,sv39"; + + cpu31_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu32: cpu@32 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <32>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu32_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu33: cpu@33 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <33>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu33_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu34: cpu@34 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <34>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu34_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu35: cpu@35 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <35>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache8>; + mmu-type =3D "riscv,sv39"; + + cpu35_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu36: cpu@36 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <36>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu36_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu37: cpu@37 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <37>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu37_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu38: cpu@38 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <38>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu38_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu39: cpu@39 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <39>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache9>; + mmu-type =3D "riscv,sv39"; + + cpu39_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu40: cpu@40 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <40>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu40_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu41: cpu@41 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <41>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu41_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu42: cpu@42 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <42>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu42_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu43: cpu@43 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <43>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache12>; + mmu-type =3D "riscv,sv39"; + + cpu43_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu44: cpu@44 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <44>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu44_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu45: cpu@45 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <45>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu45_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu46: cpu@46 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <46>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu46_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu47: cpu@47 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <47>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache13>; + mmu-type =3D "riscv,sv39"; + + cpu47_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu48: cpu@48 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <48>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu48_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu49: cpu@49 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <49>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu49_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu50: cpu@50 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <50>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu50_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu51: cpu@51 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <51>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache10>; + mmu-type =3D "riscv,sv39"; + + cpu51_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu52: cpu@52 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <52>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu52_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu53: cpu@53 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <53>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu53_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu54: cpu@54 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <54>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu54_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu55: cpu@55 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <55>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache11>; + mmu-type =3D "riscv,sv39"; + + cpu55_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu56: cpu@56 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <56>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu56_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu57: cpu@57 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <57>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu57_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu58: cpu@58 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <58>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu58_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu59: cpu@59 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <59>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache14>; + mmu-type =3D "riscv,sv39"; + + cpu59_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu60: cpu@60 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <60>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu60_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu61: cpu@61 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <61>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu61_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu62: cpu@62 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <62>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu62_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu63: cpu@63 { + compatible =3D "thead,c920", "riscv"; + device_type =3D "cpu"; + riscv,isa =3D "rv64imafdc"; + riscv,isa-base =3D ISA_BASE; + riscv,isa-extensions =3D ISA_EXTENSIONS; + reg =3D <63>; + i-cache-block-size =3D <64>; + i-cache-size =3D <65536>; + i-cache-sets =3D <512>; + d-cache-block-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_cache15>; + mmu-type =3D "riscv,sv39"; + + cpu63_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + l2_cache0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache2: cache-controller-2 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache3: cache-controller-3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache4: cache-controller-4 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache5: cache-controller-5 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache6: cache-controller-6 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache7: cache-controller-7 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache8: cache-controller-8 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache9: cache-controller-9 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache10: cache-controller-10 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache11: cache-controller-11 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache12: cache-controller-12 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache13: cache-controller-13 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache14: cache-controller-14 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + + l2_cache15: cache-controller-15 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-size =3D <1048576>; + cache-sets =3D <1024>; + cache-unified; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi new file mode 100644 index 000000000000..92935ceac941 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +/dts-v1/; +#include + +#include "sg2042-cpus.dtsi" + +/ { + compatible =3D "sophgo,sg2042"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-noncoherent; + + aliases { + serial0 =3D &uart0; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint_mswi: interrupt-controller@7094000000 { + compatible =3D "sophgo,sg2042-clint-mswi"; + reg =3D <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended =3D <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>, + <&cpu4_intc 3>, + <&cpu5_intc 3>, + <&cpu6_intc 3>, + <&cpu7_intc 3>, + <&cpu8_intc 3>, + <&cpu9_intc 3>, + <&cpu10_intc 3>, + <&cpu11_intc 3>, + <&cpu12_intc 3>, + <&cpu13_intc 3>, + <&cpu14_intc 3>, + <&cpu15_intc 3>, + <&cpu16_intc 3>, + <&cpu17_intc 3>, + <&cpu18_intc 3>, + <&cpu19_intc 3>, + <&cpu20_intc 3>, + <&cpu21_intc 3>, + <&cpu22_intc 3>, + <&cpu23_intc 3>, + <&cpu24_intc 3>, + <&cpu25_intc 3>, + <&cpu26_intc 3>, + <&cpu27_intc 3>, + <&cpu28_intc 3>, + <&cpu29_intc 3>, + <&cpu30_intc 3>, + <&cpu31_intc 3>, + <&cpu32_intc 3>, + <&cpu33_intc 3>, + <&cpu34_intc 3>, + <&cpu35_intc 3>, + <&cpu36_intc 3>, + <&cpu37_intc 3>, + <&cpu38_intc 3>, + <&cpu39_intc 3>, + <&cpu40_intc 3>, + <&cpu41_intc 3>, + <&cpu42_intc 3>, + <&cpu43_intc 3>, + <&cpu44_intc 3>, + <&cpu45_intc 3>, + <&cpu46_intc 3>, + <&cpu47_intc 3>, + <&cpu48_intc 3>, + <&cpu49_intc 3>, + <&cpu50_intc 3>, + <&cpu51_intc 3>, + <&cpu52_intc 3>, + <&cpu53_intc 3>, + <&cpu54_intc 3>, + <&cpu55_intc 3>, + <&cpu56_intc 3>, + <&cpu57_intc 3>, + <&cpu58_intc 3>, + <&cpu59_intc 3>, + <&cpu60_intc 3>, + <&cpu61_intc 3>, + <&cpu62_intc 3>, + <&cpu63_intc 3>; + }; + + clint_mtimer0: timer@70ac000000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac000000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + clint_mtimer1: timer@70ac010000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac010000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu4_intc 7>, + <&cpu5_intc 7>, + <&cpu6_intc 7>, + <&cpu7_intc 7>; + }; + + clint_mtimer2: timer@70ac020000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac020000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu8_intc 7>, + <&cpu9_intc 7>, + <&cpu10_intc 7>, + <&cpu11_intc 7>; + }; + + clint_mtimer3: timer@70ac030000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac030000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu12_intc 7>, + <&cpu13_intc 7>, + <&cpu14_intc 7>, + <&cpu15_intc 7>; + }; + + clint_mtimer4: timer@70ac040000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac040000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu16_intc 7>, + <&cpu17_intc 7>, + <&cpu18_intc 7>, + <&cpu19_intc 7>; + }; + + clint_mtimer5: timer@70ac050000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac050000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu20_intc 7>, + <&cpu21_intc 7>, + <&cpu22_intc 7>, + <&cpu23_intc 7>; + }; + + clint_mtimer6: timer@70ac060000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac060000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu24_intc 7>, + <&cpu25_intc 7>, + <&cpu26_intc 7>, + <&cpu27_intc 7>; + }; + + clint_mtimer7: timer@70ac070000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac070000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu28_intc 7>, + <&cpu29_intc 7>, + <&cpu30_intc 7>, + <&cpu31_intc 7>; + }; + + clint_mtimer8: timer@70ac080000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac080000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu32_intc 7>, + <&cpu33_intc 7>, + <&cpu34_intc 7>, + <&cpu35_intc 7>; + }; + + clint_mtimer9: timer@70ac090000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac090000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu36_intc 7>, + <&cpu37_intc 7>, + <&cpu38_intc 7>, + <&cpu39_intc 7>; + }; + + clint_mtimer10: timer@70ac0a0000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac0a0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu40_intc 7>, + <&cpu41_intc 7>, + <&cpu42_intc 7>, + <&cpu43_intc 7>; + }; + + clint_mtimer11: timer@70ac0b0000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac0b0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu44_intc 7>, + <&cpu45_intc 7>, + <&cpu46_intc 7>, + <&cpu47_intc 7>; + }; + + clint_mtimer12: timer@70ac0c0000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac0c0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu48_intc 7>, + <&cpu49_intc 7>, + <&cpu50_intc 7>, + <&cpu51_intc 7>; + }; + + clint_mtimer13: timer@70ac0d0000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac0d0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu52_intc 7>, + <&cpu53_intc 7>, + <&cpu54_intc 7>, + <&cpu55_intc 7>; + }; + + clint_mtimer14: timer@70ac0e0000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac0e0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu56_intc 7>, + <&cpu57_intc 7>, + <&cpu58_intc 7>, + <&cpu59_intc 7>; + }; + + clint_mtimer15: timer@70ac0f0000 { + compatible =3D "sophgo,sg2042-clint-mtimer"; + reg =3D <0x00000070 0xac0f0000 0x00000000 0x00007ff8>; + interrupts-extended =3D <&cpu60_intc 7>, + <&cpu61_intc 7>, + <&cpu62_intc 7>, + <&cpu63_intc 7>; + }; + + intc: interrupt-controller@7090000000 { + compatible =3D "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + reg =3D <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended =3D + <&cpu0_intc 0xffffffff>, <&cpu0_intc 9>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>, + <&cpu5_intc 0xffffffff>, <&cpu5_intc 9>, + <&cpu6_intc 0xffffffff>, <&cpu6_intc 9>, + <&cpu7_intc 0xffffffff>, <&cpu7_intc 9>, + <&cpu8_intc 0xffffffff>, <&cpu8_intc 9>, + <&cpu9_intc 0xffffffff>, <&cpu9_intc 9>, + <&cpu10_intc 0xffffffff>, <&cpu10_intc 9>, + <&cpu11_intc 0xffffffff>, <&cpu11_intc 9>, + <&cpu12_intc 0xffffffff>, <&cpu12_intc 9>, + <&cpu13_intc 0xffffffff>, <&cpu13_intc 9>, + <&cpu14_intc 0xffffffff>, <&cpu14_intc 9>, + <&cpu15_intc 0xffffffff>, <&cpu15_intc 9>, + <&cpu16_intc 0xffffffff>, <&cpu16_intc 9>, + <&cpu17_intc 0xffffffff>, <&cpu17_intc 9>, + <&cpu18_intc 0xffffffff>, <&cpu18_intc 9>, + <&cpu19_intc 0xffffffff>, <&cpu19_intc 9>, + <&cpu20_intc 0xffffffff>, <&cpu20_intc 9>, + <&cpu21_intc 0xffffffff>, <&cpu21_intc 9>, + <&cpu22_intc 0xffffffff>, <&cpu22_intc 9>, + <&cpu23_intc 0xffffffff>, <&cpu23_intc 9>, + <&cpu24_intc 0xffffffff>, <&cpu24_intc 9>, + <&cpu25_intc 0xffffffff>, <&cpu25_intc 9>, + <&cpu26_intc 0xffffffff>, <&cpu26_intc 9>, + <&cpu27_intc 0xffffffff>, <&cpu27_intc 9>, + <&cpu28_intc 0xffffffff>, <&cpu28_intc 9>, + <&cpu29_intc 0xffffffff>, <&cpu29_intc 9>, + <&cpu30_intc 0xffffffff>, <&cpu30_intc 9>, + <&cpu31_intc 0xffffffff>, <&cpu31_intc 9>, + <&cpu32_intc 0xffffffff>, <&cpu32_intc 9>, + <&cpu33_intc 0xffffffff>, <&cpu33_intc 9>, + <&cpu34_intc 0xffffffff>, <&cpu34_intc 9>, + <&cpu35_intc 0xffffffff>, <&cpu35_intc 9>, + <&cpu36_intc 0xffffffff>, <&cpu36_intc 9>, + <&cpu37_intc 0xffffffff>, <&cpu37_intc 9>, + <&cpu38_intc 0xffffffff>, <&cpu38_intc 9>, + <&cpu39_intc 0xffffffff>, <&cpu39_intc 9>, + <&cpu40_intc 0xffffffff>, <&cpu40_intc 9>, + <&cpu41_intc 0xffffffff>, <&cpu41_intc 9>, + <&cpu42_intc 0xffffffff>, <&cpu42_intc 9>, + <&cpu43_intc 0xffffffff>, <&cpu43_intc 9>, + <&cpu44_intc 0xffffffff>, <&cpu44_intc 9>, + <&cpu45_intc 0xffffffff>, <&cpu45_intc 9>, + <&cpu46_intc 0xffffffff>, <&cpu46_intc 9>, + <&cpu47_intc 0xffffffff>, <&cpu47_intc 9>, + <&cpu48_intc 0xffffffff>, <&cpu48_intc 9>, + <&cpu49_intc 0xffffffff>, <&cpu49_intc 9>, + <&cpu50_intc 0xffffffff>, <&cpu50_intc 9>, + <&cpu51_intc 0xffffffff>, <&cpu51_intc 9>, + <&cpu52_intc 0xffffffff>, <&cpu52_intc 9>, + <&cpu53_intc 0xffffffff>, <&cpu53_intc 9>, + <&cpu54_intc 0xffffffff>, <&cpu54_intc 9>, + <&cpu55_intc 0xffffffff>, <&cpu55_intc 9>, + <&cpu56_intc 0xffffffff>, <&cpu56_intc 9>, + <&cpu57_intc 0xffffffff>, <&cpu57_intc 9>, + <&cpu58_intc 0xffffffff>, <&cpu58_intc 9>, + <&cpu59_intc 0xffffffff>, <&cpu59_intc 9>, + <&cpu60_intc 0xffffffff>, <&cpu60_intc 9>, + <&cpu61_intc 0xffffffff>, <&cpu61_intc 9>, + <&cpu62_intc 0xffffffff>, <&cpu62_intc 9>, + <&cpu63_intc 0xffffffff>, <&cpu63_intc 9>; + riscv,ndev =3D <224>; + }; + + uart0: serial@7040000000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x00000070 0x40000000 0x00000000 0x00001000>; + interrupt-parent =3D <&intc>; + interrupts =3D <112 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency =3D <500000000>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + status =3D "disabled"; + }; + }; +}; --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05ED2E810AD for ; Wed, 27 Sep 2023 09:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230350AbjI0JC7 (ORCPT ); Wed, 27 Sep 2023 05:02:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230344AbjI0JCx (ORCPT ); Wed, 27 Sep 2023 05:02:53 -0400 Received: from mail-ot1-x330.google.com (mail-ot1-x330.google.com [IPv6:2607:f8b0:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A8FEEB; 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charset="utf-8" Milk-V Pioneer [1] is a developer motherboard based on SG2042 in a standard mATX form factor. Currently only support booting into console with only uart enabled, other features will be added soon later. Link: https://milkv.io/pioneer [1] Reviewed-by: Guo Ren Acked-by: Chao Wei Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/sophgo/Makefile | 3 +++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/Makefile create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f60a280abb15..72030fd727af 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -4,6 +4,7 @@ subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas subdir-y +=3D sifive +subdir-y +=3D sophgo subdir-y +=3D starfive subdir-y +=3D thead =20 diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/soph= go/Makefile new file mode 100644 index 000000000000..5a471b19df22 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2042-milkv-pioneer.dtb + diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/ris= cv/boot/dts/sophgo/sg2042-milkv-pioneer.dts new file mode 100644 index 000000000000..49b4b9c2c101 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +/ { + model =3D "Milk-V Pioneer"; + compatible =3D "milkv,pioneer", "sophgo,sg2042"; + + chosen { + stdout-path =3D "serial0"; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.25.1 From nobody Sat Feb 7 21:08:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72DC9E810A8 for ; Wed, 27 Sep 2023 09:03:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230375AbjI0JDN (ORCPT ); Wed, 27 Sep 2023 05:03:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230271AbjI0JDI (ORCPT ); Wed, 27 Sep 2023 05:03:08 -0400 Received: from mail-oi1-x236.google.com (mail-oi1-x236.google.com [IPv6:2607:f8b0:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F4C01B0; Wed, 27 Sep 2023 02:03:06 -0700 (PDT) Received: by mail-oi1-x236.google.com with SMTP id 5614622812f47-3add37de892so5290006b6e.1; Wed, 27 Sep 2023 02:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695805385; x=1696410185; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C7RhJG0eb4h1rNL5PLmu2Fo83S0B+583tqhBhK3d4JI=; b=f0X0x4Mzed5uOuXDb0Op2EPbEZfcYMEKeJgAqanGCDgEardePzCqpoa+SpCypesQmF N+frceqi38Dkk0a91Df2MwJDeT8uRv20MbGJ2KLSi3ZsVfQRldbAVrbVVMWg+BDl8c/z yvJnela3fawd93h54ubNda8ZPe0O6S7VvKmMwKnNTetHdi+idqv/nlWtMly3Xn+USNQb 052sDFCgQC50qNP2CBHf8wXH2nzVLPij+kLObl7GyC0iwQf2wNr+bALn1ZMQRi1I167u X8m37np0/U/fW7XSIRRWQgT7nf1lUsPZ4mc6Jq0Tw7nSlarZXpR+CcKGegK44yHMnfy5 jL0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695805385; x=1696410185; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C7RhJG0eb4h1rNL5PLmu2Fo83S0B+583tqhBhK3d4JI=; b=oJFELmGW/OfOtUN+F9UdoCcHaOh1ZpoEjOaXS9Mkx3cDDieyOIWyUB5SXn6yVQwca9 +OpOhF4U+UzPPKalbiYdcJWfb6x2f5TVFsNZdnZmjvgKsYzXyzix0E2dwmqrEZ/7gY1k h+kxBUh9gSA/Hb04rp/DV38iLBEHiYbSCPAJI7DiRNic+GMX7udtp2zdOi2sgjfQYzi7 Dc6kHOJirgHHZJwq1BeHlexjzK/2erfipdkYUyDGfV+GEDB8XIPLIi88cpAb1UA15Zqq aShRnwrhfpVz2VPt01MuiclqUNpWwf04zSN+g8v+oTmhUCib/dU45asdX+5ykdXupMCb KS4w== X-Gm-Message-State: AOJu0YzI6L74t86edAEf2j24wNcgpToo8mxlPL566v5ZHKh6TrsqABIX ih1kktbjJF/J8JdRoY/oHxQ= X-Google-Smtp-Source: AGHT+IHVTwpCDD+CcCbU7lnn521yLbJzkneYegHXpDLGMd37HYDLDoN+QRnWByfeQG0DJMir+qdcVA== X-Received: by 2002:a05:6808:315:b0:3ab:83fe:e182 with SMTP id i21-20020a056808031500b003ab83fee182mr1543690oie.1.1695805385207; Wed, 27 Sep 2023 02:03:05 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id i14-20020a54408e000000b003ae24b38f99sm1809096oii.2.2023.09.27.02.03.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 02:03:05 -0700 (PDT) From: Chen Wang To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang , Conor Dooley , Chen Wang Subject: [PATCH v3 11/11] riscv: defconfig: enable SOPHGO SoC Date: Wed, 27 Sep 2023 17:02:58 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable SOPHGO SoC config in defconfig to allow the default upstream kernel to boot on Milk-V Pioneer board. Acked-by: Chao Wei Acked-by: Conor Dooley Reviewed-by: Guo Ren Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..bf737cfa1d2c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -32,6 +32,7 @@ CONFIG_SOC_SIFIVE=3Dy CONFIG_SOC_STARFIVE=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_SOC_VIRT=3Dy +CONFIG_ARCH_SOPHGO=3Dy CONFIG_SMP=3Dy CONFIG_HOTPLUG_CPU=3Dy CONFIG_PM=3Dy --=20 2.25.1