From nobody Wed Dec 17 23:49:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92453EB64DA for ; Thu, 20 Jul 2023 18:50:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbjGTSuG (ORCPT ); Thu, 20 Jul 2023 14:50:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229720AbjGTSuC (ORCPT ); Thu, 20 Jul 2023 14:50:02 -0400 Received: from mail-vk1-xa31.google.com (mail-vk1-xa31.google.com [IPv6:2607:f8b0:4864:20::a31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9F9E171B for ; Thu, 20 Jul 2023 11:50:00 -0700 (PDT) Received: by mail-vk1-xa31.google.com with SMTP id 71dfb90a1353d-48138ef0c3eso457411e0c.0 for ; Thu, 20 Jul 2023 11:50:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689879000; x=1690483800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=47VRng0K3KEZnQHzer+QQBEt4eStFdrT5Gpil6rEOTc=; b=hDY9UfenLOhlxmipNDa6S19arCcMFcDXN2mksFWWmKcrGwqXEi+P6qFemmgdGpxpDW Ye5q6R6pTs1WR4uX9Jg1Bpi2btCK1s9qaPSVEXXP96xlQhMOc04dIq335ynBzPEqKVpO qr1FORNrS48wh7aI18u+9QC/eb0rmp4phXMl4DQNURuZy8JdKD7kUM6Nb92ltwcuvwz1 v19Up7vMuB3rOtHLe2JTuijTF0wcVZtYb2WxwgRqvCeioBIquJ0WuhQ8XfolxZFolLg8 +NmO1Ng4nafz6gpViDMTFUPi9n/EBvpc7XMxaKkh3nHp/HX0oVAcU0oD5Ntq1mdSGh+t 4M3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689879000; x=1690483800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=47VRng0K3KEZnQHzer+QQBEt4eStFdrT5Gpil6rEOTc=; b=YPzfvBkh4CPjNKKABwj2XRVBKMMN1xZ0HbvVdcyZtyGgrohnPb5LROgPsVdEpLa3Id kDfVaGRdne7GNWf2sfmlKvKWoPCYihAtJ36Fx0XPwyrSl5EAmDirT2QKK5wI5YFvXXio DrRJ88+8iwQyRo//vByRir/3tuYIIqkcvK3VGMV0com9Gu2ymUtPZAmx2rJSgCqEXJA5 3ciR7UGhzTeC3vX5te65lhc1AZrmCdFWHZ6v2Uv+6O8Wa7tU7/ggyUC5Nvz9t5oAiZpz drGD5aAkUVc1TDhsZwrTALfNx8h3tBITyrcrYb+Y8w5+RZ4i/QgGLrdSppHr3UsEDOs2 yUFQ== X-Gm-Message-State: ABy/qLY7EyHZogHS4ctHSzYA55MNU6D3s9GofoXfHZnQcmsIe9JRgvnh gaCsXp3NZgoJoF6aBzW1wkUu/w== X-Google-Smtp-Source: APBJJlGxMG0odt5XnwWXp50Eu92UKYDu9KmTr2OHhGCYdmNmFXK+GEFxafD5A4keOPMLOdyfTS+CYw== X-Received: by 2002:a1f:4183:0:b0:471:b557:12a with SMTP id o125-20020a1f4183000000b00471b557012amr2556702vka.11.1689878999771; Thu, 20 Jul 2023 11:49:59 -0700 (PDT) Received: from localhost.localdomain (072-189-067-006.res.spectrum.com. [72.189.67.6]) by smtp.gmail.com with ESMTPSA id h7-20020a0561220b6700b0047dbd48bc44sm238059vkf.17.2023.07.20.11.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 11:49:59 -0700 (PDT) From: William Breathitt Gray To: Bartosz Golaszewski , Linus Walleij Cc: Lars-Peter Clausen , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, William Breathitt Gray Subject: [RESEND PATCH 1/2] gpio: 104-dio-48e: Add Counter/Timer support Date: Thu, 20 Jul 2023 14:49:43 -0400 Message-ID: <9b159da19bb78df21c1dc24161188c9b8452720a.1689878150.git.william.gray@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 104-DIO-48E features an 8254 Counter/Timer chip providing three counter/timers which can be used for frequency measurement, frequency output, pulse width modulation, pulse width measurement, event count, etc. The counter/timers use the same addresses as PPI 0 (addresses 0x0 to 0x3), so a raw_spinlock_t is used to synchronize operations between the two regmap mappings to prevent clobbering. Reviewed-by: Linus Walleij Signed-off-by: William Breathitt Gray --- drivers/gpio/Kconfig | 1 + drivers/gpio/gpio-104-dio-48e.c | 127 ++++++++++++++++++++++++++++---- 2 files changed, 112 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e382dfebad7c..49466a148678 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -858,6 +858,7 @@ config GPIO_104_DIO_48E select REGMAP_IRQ select GPIOLIB_IRQCHIP select GPIO_I8255 + select I8254 help Enables GPIO support for the ACCES 104-DIO-48E series (104-DIO-48E, 104-DIO-24E). The base port addresses for the devices may be diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48= e.c index 8ff5f4ff5958..4df9becaf349 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include =20 #include "gpio-i8255.h" @@ -37,6 +39,8 @@ MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line n= umbers"); =20 #define DIO48E_ENABLE_INTERRUPT 0xB #define DIO48E_DISABLE_INTERRUPT DIO48E_ENABLE_INTERRUPT +#define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD +#define DIO48E_DISABLE_COUNTER_TIMER_ADDRESSING DIO48E_ENABLE_COUNTER_TIME= R_ADDRESSING #define DIO48E_CLEAR_INTERRUPT 0xF =20 #define DIO48E_NUM_PPI 2 @@ -75,18 +79,20 @@ static const struct regmap_access_table dio48e_precious= _table =3D { .yes_ranges =3D dio48e_precious_ranges, .n_yes_ranges =3D ARRAY_SIZE(dio48e_precious_ranges), }; -static const struct regmap_config dio48e_regmap_config =3D { - .reg_bits =3D 8, - .reg_stride =3D 1, - .val_bits =3D 8, - .io_port =3D true, - .max_register =3D 0xF, - .wr_table =3D &dio48e_wr_table, - .rd_table =3D &dio48e_rd_table, - .volatile_table =3D &dio48e_volatile_table, - .precious_table =3D &dio48e_precious_table, - .cache_type =3D REGCACHE_FLAT, - .use_raw_spinlock =3D true, + +static const struct regmap_range pit_wr_ranges[] =3D { + regmap_reg_range(0x0, 0x3), +}; +static const struct regmap_range pit_rd_ranges[] =3D { + regmap_reg_range(0x0, 0x2), +}; +static const struct regmap_access_table pit_wr_table =3D { + .yes_ranges =3D pit_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_wr_ranges), +}; +static const struct regmap_access_table pit_rd_table =3D { + .yes_ranges =3D pit_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_rd_ranges), }; =20 /* only bit 3 on each respective Port C supports interrupts */ @@ -102,14 +108,56 @@ static const struct regmap_irq dio48e_regmap_irqs[] = =3D { =20 /** * struct dio48e_gpio - GPIO device private data structure + * @lock: synchronization lock to prevent I/O race conditions * @map: Regmap for the device + * @regs: virtual mapping for device registers + * @flags: IRQ flags saved during locking * @irq_mask: Current IRQ mask state on the device */ struct dio48e_gpio { + raw_spinlock_t lock; struct regmap *map; + void __iomem *regs; + unsigned long flags; unsigned int irq_mask; }; =20 +static void dio48e_regmap_lock(void *lock_arg) __acquires(&dio48egpio->loc= k) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + unsigned long flags; + + raw_spin_lock_irqsave(&dio48egpio->lock, flags); + dio48egpio->flags =3D flags; +} + +static void dio48e_regmap_unlock(void *lock_arg) __releases(&dio48egpio->l= ock) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + + raw_spin_unlock_irqrestore(&dio48egpio->lock, dio48egpio->flags); +} + +static void pit_regmap_lock(void *lock_arg) __acquires(&dio48egpio->lock) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + unsigned long flags; + + raw_spin_lock_irqsave(&dio48egpio->lock, flags); + dio48egpio->flags =3D flags; + + iowrite8(0x00, dio48egpio->regs + DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING); +} + +static void pit_regmap_unlock(void *lock_arg) __releases(&dio48egpio->lock) +{ + struct dio48e_gpio *const dio48egpio =3D lock_arg; + + ioread8(dio48egpio->regs + DIO48E_DISABLE_COUNTER_TIMER_ADDRESSING); + + raw_spin_unlock_irqrestore(&dio48egpio->lock, dio48egpio->flags); +} + static int dio48e_handle_mask_sync(const int index, const unsigned int mask_buf_def, const unsigned int mask_buf, @@ -176,6 +224,9 @@ static int dio48e_probe(struct device *dev, unsigned in= t id) struct i8255_regmap_config config =3D {}; void __iomem *regs; struct regmap *map; + struct regmap_config dio48e_regmap_config; + struct regmap_config pit_regmap_config; + struct i8254_regmap_config pit_config; int err; struct regmap_irq_chip *chip; struct dio48e_gpio *dio48egpio; @@ -187,21 +238,58 @@ static int dio48e_probe(struct device *dev, unsigned = int id) return -EBUSY; } =20 + dio48egpio =3D devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); + if (!dio48egpio) + return -ENOMEM; + regs =3D devm_ioport_map(dev, base[id], DIO48E_EXTENT); if (!regs) return -ENOMEM; =20 + dio48egpio->regs =3D regs; + + raw_spin_lock_init(&dio48egpio->lock); + + dio48e_regmap_config =3D (struct regmap_config) { + .reg_bits =3D 8, + .reg_stride =3D 1, + .val_bits =3D 8, + .lock =3D dio48e_regmap_lock, + .unlock =3D dio48e_regmap_unlock, + .lock_arg =3D dio48egpio, + .io_port =3D true, + .wr_table =3D &dio48e_wr_table, + .rd_table =3D &dio48e_rd_table, + .volatile_table =3D &dio48e_volatile_table, + .precious_table =3D &dio48e_precious_table, + .cache_type =3D REGCACHE_FLAT, + }; + map =3D devm_regmap_init_mmio(dev, regs, &dio48e_regmap_config); if (IS_ERR(map)) return dev_err_probe(dev, PTR_ERR(map), "Unable to initialize register map\n"); =20 - dio48egpio =3D devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL); - if (!dio48egpio) - return -ENOMEM; - dio48egpio->map =3D map; =20 + pit_regmap_config =3D (struct regmap_config) { + .name =3D "i8254", + .reg_bits =3D 8, + .reg_stride =3D 1, + .val_bits =3D 8, + .lock =3D pit_regmap_lock, + .unlock =3D pit_regmap_unlock, + .lock_arg =3D dio48egpio, + .io_port =3D true, + .wr_table =3D &pit_wr_table, + .rd_table =3D &pit_rd_table, + }; + + pit_config.map =3D devm_regmap_init_mmio(dev, regs, &pit_regmap_config); + if (IS_ERR(pit_config.map)) + return dev_err_probe(dev, PTR_ERR(pit_config.map), + "Unable to initialize i8254 register map\n"); + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; @@ -225,6 +313,12 @@ static int dio48e_probe(struct device *dev, unsigned i= nt id) if (err) return dev_err_probe(dev, err, "IRQ registration failed\n"); =20 + pit_config.parent =3D dev; + + err =3D devm_i8254_regmap_register(dev, &pit_config); + if (err) + return err; + config.parent =3D dev; config.map =3D map; config.num_ppi =3D DIO48E_NUM_PPI; @@ -245,3 +339,4 @@ module_isa_driver_with_irq(dio48e_driver, num_dio48e, n= um_irq); MODULE_AUTHOR("William Breathitt Gray "); MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(I8254); --=20 2.41.0 From nobody Wed Dec 17 23:49:44 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B19AC0015E for ; Thu, 20 Jul 2023 18:50:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229763AbjGTSuK (ORCPT ); Thu, 20 Jul 2023 14:50:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229790AbjGTSuG (ORCPT ); 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[72.189.67.6]) by smtp.gmail.com with ESMTPSA id h7-20020a0561220b6700b0047dbd48bc44sm238059vkf.17.2023.07.20.11.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 11:50:00 -0700 (PDT) From: William Breathitt Gray To: Bartosz Golaszewski , Linus Walleij Cc: Lars-Peter Clausen , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, William Breathitt Gray Subject: [RESEND PATCH 2/2] iio: addac: stx104: Add 8254 Counter/Timer support Date: Thu, 20 Jul 2023 14:49:44 -0400 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The STX104 features an 8254 Counter/Timer chip providing three counter/timers which can be used for frequency measurement, frequency output, pulse width modulation, pulse width measurement, event count, etc. The STX104 provides a register bank selection to bank select between the 8254 Bank and the Indexed Register Array Bank; the Indexed Register Array is not utilized by this driver, so the 8254 Bank is selected unconditionally. Signed-off-by: William Breathitt Gray --- drivers/iio/addac/Kconfig | 1 + drivers/iio/addac/stx104.c | 61 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig index 877f9124803c..b2623881f0ec 100644 --- a/drivers/iio/addac/Kconfig +++ b/drivers/iio/addac/Kconfig @@ -38,6 +38,7 @@ config STX104 select REGMAP_MMIO select GPIOLIB select GPIO_REGMAP + select I8254 help Say yes here to build support for the Apex Embedded Systems STX104 integrated analog PC/104 card. diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c index d1f7ce033b46..6946a65512ca 100644 --- a/drivers/iio/addac/stx104.c +++ b/drivers/iio/addac/stx104.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -55,6 +56,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base= addresses"); #define STX104_ADC_STATUS (STX104_AIO_BASE + 0x8) #define STX104_ADC_CONTROL (STX104_AIO_BASE + 0x9) #define STX104_ADC_CONFIGURATION (STX104_AIO_BASE + 0x11) +#define STX104_I8254_BASE (STX104_AIO_BASE + 0x12) =20 #define STX104_AIO_DATA_STRIDE 2 #define STX104_DAC_OFFSET(_channel) (STX104_DAC_BASE + STX104_AIO_DATA_STR= IDE * (_channel)) @@ -77,6 +79,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base= addresses"); /* ADC Configuration */ #define STX104_GAIN GENMASK(1, 0) #define STX104_ADBU BIT(2) +#define STX104_RBK GENMASK(7, 4) #define STX104_BIPOLAR 0 #define STX104_GAIN_X1 0 #define STX104_GAIN_X2 1 @@ -168,6 +171,32 @@ static const struct regmap_config dio_regmap_config = =3D { .io_port =3D true, }; =20 +static const struct regmap_range pit_wr_ranges[] =3D { + regmap_reg_range(0x0, 0x3), +}; +static const struct regmap_range pit_rd_ranges[] =3D { + regmap_reg_range(0x0, 0x2), +}; +static const struct regmap_access_table pit_wr_table =3D { + .yes_ranges =3D pit_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_wr_ranges), +}; +static const struct regmap_access_table pit_rd_table =3D { + .yes_ranges =3D pit_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_rd_ranges), +}; + +static const struct regmap_config pit_regmap_config =3D { + .name =3D "i8254", + .reg_bits =3D 8, + .reg_stride =3D 1, + .reg_base =3D STX104_I8254_BASE, + .val_bits =3D 8, + .io_port =3D true, + .wr_table =3D &pit_wr_table, + .rd_table =3D &pit_rd_table, +}; + static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { @@ -339,6 +368,21 @@ static const char *stx104_names[STX104_NGPIO] =3D { "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3" }; =20 +static int bank_select_i8254(struct regmap *map) +{ + const u8 select_i8254[] =3D { 0x3, 0xB, 0xA }; + size_t i; + int err; + + for (i =3D 0; i < ARRAY_SIZE(select_i8254); i++) { + err =3D regmap_write_bits(map, STX104_ADC_CONFIGURATION, STX104_RBK, sel= ect_i8254[i]); + if (err) + return err; + } + + return 0; +} + static int stx104_init_hw(struct stx104_iio *const priv) { int err; @@ -361,7 +405,7 @@ static int stx104_init_hw(struct stx104_iio *const priv) if (err) return err; =20 - return 0; + return bank_select_i8254(priv->aio_ctl_map); } =20 static int stx104_probe(struct device *dev, unsigned int id) @@ -369,6 +413,7 @@ static int stx104_probe(struct device *dev, unsigned in= t id) struct iio_dev *indio_dev; struct stx104_iio *priv; struct gpio_regmap_config gpio_config; + struct i8254_regmap_config pit_config; void __iomem *stx104_base; struct regmap *aio_ctl_map; struct regmap *aio_data_map; @@ -406,6 +451,11 @@ static int stx104_probe(struct device *dev, unsigned i= nt id) return dev_err_probe(dev, PTR_ERR(dio_map), "Unable to initialize dio register map\n"); =20 + pit_config.map =3D devm_regmap_init_mmio(dev, stx104_base, &pit_regmap_co= nfig); + if (IS_ERR(pit_config.map)) + return dev_err_probe(dev, PTR_ERR(pit_config.map), + "Unable to initialize i8254 register map\n"); + priv =3D iio_priv(indio_dev); priv->aio_ctl_map =3D aio_ctl_map; priv->aio_data_map =3D aio_data_map; @@ -449,7 +499,13 @@ static int stx104_probe(struct device *dev, unsigned i= nt id) .drvdata =3D dio_map, }; =20 - return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); + err =3D PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); + if (err) + return err; + + pit_config.parent =3D dev; + + return devm_i8254_regmap_register(dev, &pit_config); } =20 static struct isa_driver stx104_driver =3D { @@ -464,3 +520,4 @@ module_isa_driver(stx104_driver, num_stx104); MODULE_AUTHOR("William Breathitt Gray "); MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(I8254); --=20 2.41.0