From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D474C001DD for ; Thu, 13 Jul 2023 02:17:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233523AbjGMCRy (ORCPT ); Wed, 12 Jul 2023 22:17:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233527AbjGMCRq (ORCPT ); Wed, 12 Jul 2023 22:17:46 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C380211C; Wed, 12 Jul 2023 19:17:39 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlth-0005VH-1B; Thu, 13 Jul 2023 02:17:37 +0000 Date: Thu, 13 Jul 2023 03:17:24 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 1/9] dt-bindings: net: mediatek,net: add missing mediatek,mt7621-eth Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the Ethernet controller found in the MediaTek MT7621 MIPS SoC family which is supported by the mtk_eth_soc driver. Fixes: 889bcbdeee57 ("net: ethernet: mediatek: support MT7621 SoC ethernet = hardware") Signed-off-by: Daniel Golle Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/net/mediatek,net.yaml | 27 ++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Docu= mentation/devicetree/bindings/net/mediatek,net.yaml index acb2b2ac4fe1e..38aa3d97ee234 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -19,6 +19,7 @@ properties: enum: - mediatek,mt2701-eth - mediatek,mt7623-eth + - mediatek,mt7621-eth - mediatek,mt7622-eth - mediatek,mt7629-eth - mediatek,mt7981-eth @@ -32,7 +33,7 @@ properties: clock-names: true =20 interrupts: - minItems: 3 + minItems: 1 maxItems: 4 =20 power-domains: @@ -131,6 +132,30 @@ allOf: =20 mediatek,wed-pcie: false =20 + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt7621-eth + then: + properties: + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 2 + + clock-names: + items: + - const: ethif + - const: fe + + mediatek,wed: false + + mediatek,wed-pcie: false + - if: properties: compatible: --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87CBCEB64DD for ; Thu, 13 Jul 2023 02:18:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233312AbjGMCST (ORCPT ); Wed, 12 Jul 2023 22:18:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233614AbjGMCSO (ORCPT ); Wed, 12 Jul 2023 22:18:14 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D67B9213E; Wed, 12 Jul 2023 19:18:10 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJluC-0005W8-2s; Thu, 13 Jul 2023 02:18:09 +0000 Date: Thu, 13 Jul 2023 03:17:55 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 2/9] dt-bindings: net: mediatek,net: add mt7988-eth binding Message-ID: <6c2e9caddfb9427444307d8443f1b231e500787b.1689012506.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce DT bindings for the MT7988 SoC to mediatek,net.yaml. The MT7988 SoC got 3 Ethernet MACs operating at a maximum of 10 Gigabit/sec supported by 2 packet processor engines for offloading tasks. The first MAC is hard-wired to a built-in switch which exposes four 1000Base-T PHYs as user ports. It also comes with built-in 2500Base-T PHY which can be used with the 2nd GMAC. The 2nd and 3rd GMAC can be connected to external PHYs or provide SFP(+) cages attached via SGMII, 1000Base-X, 2500Base-X, USXGMII, 5GBase-R or 10GBase-KR. Signed-off-by: Daniel Golle --- .../devicetree/bindings/net/mediatek,net.yaml | 111 ++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Docu= mentation/devicetree/bindings/net/mediatek,net.yaml index 38aa3d97ee234..59f074e56fe2a 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -24,6 +24,7 @@ properties: - mediatek,mt7629-eth - mediatek,mt7981-eth - mediatek,mt7986-eth + - mediatek,mt7988-eth - ralink,rt5350-eth =20 reg: @@ -71,6 +72,22 @@ properties: A list of phandle to the syscon node that handles the SGMII setup wh= ich is required for those SoCs equipped with SGMII. =20 + mediatek,toprgu + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the mediatek toprgu controller used to provide various cl= ocks + and reset to the system. + + mediatek,usxgmiisys: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 2 + maxItems: 2 + items: + maxItems: 1 + description: + A list of phandle to the syscon node that handles the USXGMII setup = which is required for + those SoCs equipped with USXGMII. + mediatek,wed: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 2 @@ -85,6 +102,21 @@ properties: description: Phandle to the mediatek wed-pcie controller. =20 + mediatek,xfi_pextp: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 2 + maxItems: 2 + items: + maxItems: 1 + description: + A list of phandle to the syscon node that handles the XFI setup whic= h is required for + those SoCs equipped with XFI. + + mediatek,xfi_pll: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the XFI PLL unit. + dma-coherent: true =20 mdio-bus: @@ -315,6 +347,85 @@ allOf: minItems: 2 maxItems: 2 =20 + - if: + properties: + compatible: + contains: + const: mediatek,mt7988-eth + then: + properties: + interrupts: + minItems: 4 + + clocks: + minItems: 34 + maxItems: 34 + + clock-names: + items: + - const: crypto + - const: fe + - const: gp2 + - const: gp1 + - const: gp3 + - const: ethwarp_wocpu2 + - const: ethwarp_wocpu1 + - const: ethwarp_wocpu0 + - const: esw + - const: netsys0 + - const: netsys1 + - const: sgmii_tx250m + - const: sgmii_rx250m + - const: sgmii2_tx250m + - const: sgmii2_rx250m + - const: top_usxgmii0_sel + - const: top_usxgmii1_sel + - const: top_sgm0_sel + - const: top_sgm1_sel + - const: top_xfi_phy0_xtal_sel + - const: top_xfi_phy1_xtal_sel + - const: top_eth_gmii_sel + - const: top_eth_refck_50m_sel + - const: top_eth_sys_200m_sel + - const: top_eth_sys_sel + - const: top_eth_xgmii_sel + - const: top_eth_mii_sel + - const: top_netsys_sel + - const: top_netsys_500m_sel + - const: top_netsys_pao_2x_sel + - const: top_netsys_sync_250m_sel + - const: top_netsys_ppefb_250m_sel + - const: top_netsys_warp_sel + - const: wocpu1 + - const: wocpu0 + - const: xgp1 + - const: xgp2 + - const: xgp3 + + mediatek,sgmiisys: + minItems: 2 + maxItems: 2 + + mediatek,usxgmiisys: + minItems: 2 + maxItems: 2 + + mediatek,xfi_pextp: + minItems: 2 + maxItems: 2 + + mediatek,xfi_pll: + minItems: 1 + maxItems: 1 + + mediatek,infracfg + minItems: 1 + maxItems: 1 + + mediatek,toprgu + minItems: 1 + maxItems: 1 + patternProperties: "^mac@[0-1]$": type: object --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23496C001B0 for ; Thu, 13 Jul 2023 02:19:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233463AbjGMCTB (ORCPT ); Wed, 12 Jul 2023 22:19:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233266AbjGMCS6 (ORCPT ); Wed, 12 Jul 2023 22:18:58 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1626C2127; Wed, 12 Jul 2023 19:18:38 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlue-0005Wn-06; Thu, 13 Jul 2023 02:18:36 +0000 Date: Thu, 13 Jul 2023 03:18:23 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 3/9] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V1 capability bit Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi Introduce MTK_NETSYS_V1 bit in the device capabilities for MT7621/MT7622/MT7623/MT7628/MT7629 SoCs. Use !MTK_NETSYS_V1 instead of MTK_NETSYS_V2 in the driver codebase. This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 28 ++++++------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 ++++++++++++--------- 2 files changed, 40 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 834c644b67db5..7014e0d108b27 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -659,7 +659,7 @@ static void mtk_set_queue_speed(struct mtk_eth *eth, un= signed int idx, FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | MTK_QTX_SCH_LEAKY_BUCKET_SIZE; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) val |=3D MTK_QTX_SCH_LEAKY_BUCKET_EN; =20 if (IS_ENABLED(CONFIG_SOC_MT7621)) { @@ -1037,7 +1037,7 @@ static bool mtk_rx_get_desc(struct mtk_eth *eth, stru= ct mtk_rx_dma_v2 *rxd, rxd->rxd1 =3D READ_ONCE(dma_rxd->rxd1); rxd->rxd3 =3D READ_ONCE(dma_rxd->rxd3); rxd->rxd4 =3D READ_ONCE(dma_rxd->rxd4); - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { rxd->rxd5 =3D READ_ONCE(dma_rxd->rxd5); rxd->rxd6 =3D READ_ONCE(dma_rxd->rxd6); } @@ -1095,7 +1095,7 @@ static int mtk_init_fq_dma(struct mtk_eth *eth) =20 txd->txd3 =3D TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); txd->txd4 =3D 0; - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { txd->txd5 =3D 0; txd->txd6 =3D 0; txd->txd7 =3D 0; @@ -1286,7 +1286,7 @@ static void mtk_tx_set_dma_desc(struct net_device *de= v, void *txd, struct mtk_mac *mac =3D netdev_priv(dev); struct mtk_eth *eth =3D mac->hw; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) mtk_tx_set_dma_desc_v2(dev, txd, info); else mtk_tx_set_dma_desc_v1(dev, txd, info); @@ -1935,7 +1935,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, break; =20 /* find out which mac the packet come from. values start at 1 */ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) mac =3D RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) @@ -2031,7 +2031,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, skb->dev =3D netdev; bytes +=3D skb->len; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { reason =3D FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); hash =3D trxd.rxd5 & MTK_RXD5_FOE_ENTRY; if (hash !=3D MTK_RXD5_FOE_ENTRY) @@ -2367,7 +2367,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) txd->txd2 =3D next_ptr; txd->txd3 =3D TX_DMA_LS0 | TX_DMA_OWNER_CPU; txd->txd4 =3D 0; - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V1)) { txd->txd5 =3D 0; txd->txd6 =3D 0; txd->txd7 =3D 0; @@ -2420,7 +2420,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth) FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | MTK_QTX_SCH_LEAKY_BUCKET_SIZE; - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) val |=3D MTK_QTX_SCH_LEAKY_BUCKET_EN; mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); ofs +=3D MTK_QTX_OFFSET; @@ -2556,7 +2556,7 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring= _no, int rx_flag) =20 rxd->rxd3 =3D 0; rxd->rxd4 =3D 0; - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { rxd->rxd5 =3D 0; rxd->rxd6 =3D 0; rxd->rxd7 =3D 0; @@ -3104,7 +3104,7 @@ static int mtk_start_dma(struct mtk_eth *eth) MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) val |=3D MTK_MUTLI_CNT | MTK_RESV_BUF | MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; @@ -3516,7 +3516,7 @@ static void mtk_hw_reset(struct mtk_eth *eth) { u32 val; =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); val =3D RSTCTRL_PPE0_V2; } else { @@ -3528,7 +3528,7 @@ static void mtk_hw_reset(struct mtk_eth *eth) =20 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0x3ffffff); } @@ -3724,7 +3724,7 @@ static int mtk_hw_init(struct mtk_eth *eth, bool rese= t) else mtk_hw_reset(eth); =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { /* Set FE to PDMAv2 if necessary */ val =3D mtk_r32(eth, MTK_FE_GLO_MISC); mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); @@ -3761,7 +3761,7 @@ static int mtk_hw_init(struct mtk_eth *eth, bool rese= t) */ val =3D mtk_r32(eth, MTK_CDMQ_IG_CTRL); mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { val =3D mtk_r32(eth, MTK_CDMP_IG_CTRL); mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); =20 diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index 707445f6bcb1b..c74c3918113a5 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -820,6 +820,7 @@ enum mkt_eth_capabilities { MTK_SHARED_INT_BIT, MTK_TRGMII_MT7621_CLK_BIT, MTK_QDMA_BIT, + MTK_NETSYS_V1_BIT, MTK_NETSYS_V2_BIT, MTK_SOC_MT7628_BIT, MTK_RSTCTRL_PPE1_BIT, @@ -855,6 +856,7 @@ enum mkt_eth_capabilities { #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) #define MTK_QDMA BIT(MTK_QDMA_BIT) +#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) @@ -911,25 +913,30 @@ enum mkt_eth_capabilities { =20 #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) =3D=3D (_x)) =20 -#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ - MTK_GMAC2_RGMII | MTK_SHARED_INT | \ - MTK_TRGMII_MT7621_CLK | MTK_QDMA) - -#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | MTK_GMAC2_RGMII = | \ - MTK_GMAC2_SGMII | MTK_GDM1_ESW | \ - MTK_MUX_GDM1_TO_GMAC1_ESW | \ - MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_QDMA) - -#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | MTK_GMAC2_RGMII= | \ - MTK_QDMA) - -#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628) - -#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY = | \ - MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW | \ - MTK_MUX_GMAC2_GMAC0_TO_GEPHY | \ - MTK_MUX_U3_GMAC2_TO_QPHY | \ - MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA) +#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ + MTK_GMAC2_RGMII | MTK_SHARED_INT | \ + MTK_TRGMII_MT7621_CLK | MTK_QDMA | \ + MTK_NETSYS_V1) + +#define MT7622_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_SGMII | \ + MTK_GMAC2_RGMII | MTK_GMAC2_SGMII | \ + MTK_GDM1_ESW | MTK_MUX_GDM1_TO_GMAC1_ESW |\ + MTK_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | \ + MTK_QDMA | MTK_NETSYS_V1) + +#define MT7623_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \ + MTK_GMAC2_RGMII | MTK_QDMA | \ + MTK_NETSYS_V1) + +#define MT7628_CAPS (MTK_SHARED_INT | MTK_SOC_MT7628 | \ + MTK_NETSYS_V1) + +#define MT7629_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ + MTK_GMAC2_GEPHY | MTK_GDM1_ESW | \ + MTK_MUX_GMAC2_GMAC0_TO_GEPHY | MTK_QDMA | \ + MTK_MUX_U3_GMAC2_TO_QPHY | MTK_NETSYS_V1 |\ + MTK_MUX_GDM1_TO_GMAC1_ESW | \ + MTK_MUX_GMAC12_TO_GEPHY_SGMII) =20 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY = | \ MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E601C001DD for ; Thu, 13 Jul 2023 02:19:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233502AbjGMCTQ (ORCPT ); Wed, 12 Jul 2023 22:19:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233497AbjGMCTN (ORCPT ); Wed, 12 Jul 2023 22:19:13 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F89D2120; Wed, 12 Jul 2023 19:19:06 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlv6-0005XJ-1Y; Thu, 13 Jul 2023 02:19:05 +0000 Date: Thu, 13 Jul 2023 03:18:52 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 4/9] net: ethernet: mtk_eth_soc: increase MAX_DEVS to 3 Message-ID: <2cc8012ec538106c6bcf22a40b647ec342e687a8.1689012506.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi This is a preliminary patch to add MT7988 SoC support since it runs 3 macs instead of 2. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 6 +++++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 7014e0d108b27..7f191e4337dd8 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -4030,8 +4030,12 @@ static void mtk_sgmii_destroy(struct mtk_eth *eth) { int i; =20 - for (i =3D 0; i < MTK_MAX_DEVS; i++) + for (i =3D 0; i < MTK_MAX_DEVS; i++) { + if (!eth->sgmii_pcs[i]) + continue; + mtk_pcs_lynxi_destroy(eth->sgmii_pcs[i]); + } } =20 static int mtk_cleanup(struct mtk_eth *eth) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index c74c3918113a5..b18ce4430d437 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -1049,8 +1049,8 @@ struct mtk_soc_data { =20 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) =20 -/* currently no SoC has more than 2 macs */ -#define MTK_MAX_DEVS 2 +/* currently no SoC has more than 3 macs */ +#define MTK_MAX_DEVS 3 =20 /* struct mtk_eth - This is the main datasructure for holding the state * of the driver --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E00D9C001B0 for ; Thu, 13 Jul 2023 02:19:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233556AbjGMCT4 (ORCPT ); Wed, 12 Jul 2023 22:19:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233538AbjGMCTy (ORCPT ); Wed, 12 Jul 2023 22:19:54 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB38A2685; Wed, 12 Jul 2023 19:19:33 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlvX-0005Y3-0t; Thu, 13 Jul 2023 02:19:31 +0000 Date: Thu, 13 Jul 2023 03:19:18 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 5/9] net: ethernet: mtk_eth_soc: rely on MTK_MAX_DEVS and remove MTK_MAC_COUNT Message-ID: <57e3be6406efeb082ca4552aefc7bf509471ecf7.1689012506.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi Get rid of MTK_MAC_COUNT since it is a duplicated of MTK_MAX_DEVS. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 49 ++++++++++++--------- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 - 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index 7f191e4337dd8..c001e877167c0 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -963,7 +963,7 @@ static void mtk_stats_update(struct mtk_eth *eth) { int i; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { if (!eth->mac[i] || !eth->mac[i]->hw_stats) continue; if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) { @@ -1468,7 +1468,7 @@ static int mtk_queue_stopped(struct mtk_eth *eth) { int i; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; if (netif_queue_stopped(eth->netdev[i])) @@ -1482,7 +1482,7 @@ static void mtk_wake_queue(struct mtk_eth *eth) { int i; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; netif_tx_wake_all_queues(eth->netdev[i]); @@ -1941,7 +1941,7 @@ static int mtk_poll_rx(struct napi_struct *napi, int = budget, !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) mac =3D RX_DMA_GET_SPORT(trxd.rxd4) - 1; =20 - if (unlikely(mac < 0 || mac >=3D MTK_MAC_COUNT || + if (unlikely(mac < 0 || mac >=3D MTK_MAX_DEVS || !eth->netdev[mac])) goto release_desc; =20 @@ -2978,7 +2978,7 @@ static void mtk_dma_free(struct mtk_eth *eth) const struct mtk_soc_data *soc =3D eth->soc; int i; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) + for (i =3D 0; i < MTK_MAX_DEVS; i++) if (eth->netdev[i]) netdev_reset_queue(eth->netdev[i]); if (eth->scratch_ring) { @@ -3132,8 +3132,13 @@ static void mtk_gdm_config(struct mtk_eth *eth, u32 = config) if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) return; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { - u32 val =3D mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); + for (i =3D 0; i < MTK_MAX_DEVS; i++) { + u32 val; + + if (!eth->netdev[i]) + continue; + + val =3D mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); =20 /* default setup the forward port to send frame to PDMA */ val &=3D ~0xffff; @@ -3143,7 +3148,7 @@ static void mtk_gdm_config(struct mtk_eth *eth, u32 c= onfig) =20 val |=3D config; =20 - if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) + if (netdev_uses_dsa(eth->netdev[i])) val |=3D MTK_GDMA_SPECIAL_TAG; =20 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); @@ -3745,15 +3750,15 @@ static int mtk_hw_init(struct mtk_eth *eth, bool re= set) * up with the more appropriate value when mtk_mac_config call is being * invoked. */ - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { struct net_device *dev =3D eth->netdev[i]; =20 - mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); - if (dev) { - struct mtk_mac *mac =3D netdev_priv(dev); + if (!dev) + continue; =20 - mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); - } + mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); + mtk_set_mcr_max_rx(netdev_priv(dev), + dev->mtu + MTK_RX_ETH_HLEN); } =20 /* Indicates CDM to parse the MTK special tag from CPU @@ -3950,7 +3955,7 @@ static void mtk_pending_work(struct work_struct *work) mtk_prepare_for_reset(eth); =20 /* stop all devices to make sure that dma is properly shut down */ - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i] || !netif_running(eth->netdev[i])) continue; =20 @@ -3966,8 +3971,8 @@ static void mtk_pending_work(struct work_struct *work) mtk_hw_init(eth, true); =20 /* restart DMA and enable IRQs */ - for (i =3D 0; i < MTK_MAC_COUNT; i++) { - if (!test_bit(i, &restart)) + for (i =3D 0; i < MTK_MAX_DEVS; i++) { + if (!eth->netdev[i] || !test_bit(i, &restart)) continue; =20 if (mtk_open(eth->netdev[i])) { @@ -3994,7 +3999,7 @@ static int mtk_free_dev(struct mtk_eth *eth) { int i; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; free_netdev(eth->netdev[i]); @@ -4013,7 +4018,7 @@ static int mtk_unreg_dev(struct mtk_eth *eth) { int i; =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { struct mtk_mac *mac; if (!eth->netdev[i]) continue; @@ -4320,7 +4325,7 @@ static int mtk_add_mac(struct mtk_eth *eth, struct de= vice_node *np) } =20 id =3D be32_to_cpup(_id); - if (id >=3D MTK_MAC_COUNT) { + if (id >=3D MTK_MAX_DEVS) { dev_err(eth->dev, "%d is not a valid mac id\n", id); return -EINVAL; } @@ -4465,7 +4470,7 @@ void mtk_eth_set_dma_device(struct mtk_eth *eth, stru= ct device *dma_dev) =20 rtnl_lock(); =20 - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { dev =3D eth->netdev[i]; =20 if (!dev || !(dev->flags & IFF_UP)) @@ -4772,7 +4777,7 @@ static int mtk_remove(struct platform_device *pdev) int i; =20 /* stop all devices to make sure that dma is properly shut down */ - for (i =3D 0; i < MTK_MAC_COUNT; i++) { + for (i =3D 0; i < MTK_MAX_DEVS; i++) { if (!eth->netdev[i]) continue; mtk_stop(eth->netdev[i]); diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index b18ce4430d437..03510302df9e4 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -33,7 +33,6 @@ #define MTK_TX_DMA_BUF_LEN_V2 0xffff #define MTK_QDMA_RING_SIZE 2048 #define MTK_DMA_SIZE 512 -#define MTK_MAC_COUNT 2 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) #define MTK_DMA_DUMMY_DESC 0xffffffff --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA88DC001DF for ; Thu, 13 Jul 2023 02:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233464AbjGMCUN (ORCPT ); Wed, 12 Jul 2023 22:20:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233497AbjGMCUJ (ORCPT ); Wed, 12 Jul 2023 22:20:09 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 529DB2117; Wed, 12 Jul 2023 19:20:04 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlw2-0005Yg-0W; Thu, 13 Jul 2023 02:20:02 +0000 Date: Thu, 13 Jul 2023 03:19:49 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 6/9] net: ethernet: mtk_eth_soc: add MTK_NETSYS_V3 capability bit Message-ID: <6dc1e0ad7e8138835c959fc83a6c1564e8488c59.1689012506.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi Introduce MTK_NETSYS_V3 bit in the device capabilities. This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 106 ++++++++++++++------ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 45 +++++++-- 2 files changed, 114 insertions(+), 37 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index c001e877167c0..c47353f4af541 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -943,17 +943,32 @@ void mtk_stats_update_mac(struct mtk_mac *mac) mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); hw_stats->rx_flow_control_packets +=3D mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); - hw_stats->tx_skip +=3D - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); - hw_stats->tx_collisions +=3D - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); - hw_stats->tx_bytes +=3D - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); - stats =3D mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); - if (stats) - hw_stats->tx_bytes +=3D (stats << 32); - hw_stats->tx_packets +=3D - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); + + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { + hw_stats->tx_skip +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); + hw_stats->tx_collisions +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); + hw_stats->tx_bytes +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); + stats =3D mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); + if (stats) + hw_stats->tx_bytes +=3D (stats << 32); + hw_stats->tx_packets +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); + } else { + hw_stats->tx_skip +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); + hw_stats->tx_collisions +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); + hw_stats->tx_bytes +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); + stats =3D mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); + if (stats) + hw_stats->tx_bytes +=3D (stats << 32); + hw_stats->tx_packets +=3D + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); + } } =20 u64_stats_update_end(&hw_stats->syncp); @@ -1257,7 +1272,10 @@ static void mtk_tx_set_dma_desc_v2(struct net_device= *dev, void *txd, data |=3D TX_DMA_LS0; WRITE_ONCE(desc->txd3, data); =20 - data =3D (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ + if (mac->id =3D=3D MTK_GMAC3_ID) + data =3D PSE_GDM3_PORT; + else + data =3D (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ data |=3D TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); WRITE_ONCE(desc->txd4, data); =20 @@ -1268,6 +1286,9 @@ static void mtk_tx_set_dma_desc_v2(struct net_device = *dev, void *txd, /* tx checksum offload */ if (info->csum) data |=3D TX_DMA_CHKSUM_V2; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && + netdev_uses_dsa(dev)) + data |=3D TX_DMA_SPTAG_V3; } WRITE_ONCE(desc->txd5, data); =20 @@ -1333,8 +1354,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net= _device *dev, mtk_tx_set_dma_desc(dev, itxd, &txd_info); =20 itx_buf->flags |=3D MTK_TX_FLAGS_SINGLE0; - itx_buf->flags |=3D (!mac->id) ? MTK_TX_FLAGS_FPORT0 : - MTK_TX_FLAGS_FPORT1; + itx_buf->mac_id =3D mac->id; setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, k++); =20 @@ -1382,8 +1402,7 @@ static int mtk_tx_map(struct sk_buff *skb, struct net= _device *dev, memset(tx_buf, 0, sizeof(*tx_buf)); tx_buf->data =3D (void *)MTK_DMA_DUMMY_DESC; tx_buf->flags |=3D MTK_TX_FLAGS_PAGE0; - tx_buf->flags |=3D (!mac->id) ? MTK_TX_FLAGS_FPORT0 : - MTK_TX_FLAGS_FPORT1; + tx_buf->mac_id =3D mac->id; =20 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, txd_info.size, k++); @@ -1685,7 +1704,7 @@ static int mtk_xdp_frame_map(struct mtk_eth *eth, str= uct net_device *dev, } mtk_tx_set_dma_desc(dev, txd, txd_info); =20 - tx_buf->flags |=3D !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; + tx_buf->mac_id =3D mac->id; tx_buf->type =3D dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; tx_buf->data =3D (void *)MTK_DMA_DUMMY_DESC; =20 @@ -1935,11 +1954,24 @@ static int mtk_poll_rx(struct napi_struct *napi, in= t budget, break; =20 /* find out which mac the packet come from. values start at 1 */ - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) - mac =3D RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1)) { + u32 val =3D RX_DMA_GET_SPORT_V2(trxd.rxd5); + + switch (val) { + case PSE_GDM1_PORT: + case PSE_GDM2_PORT: + mac =3D val - 1; + break; + case PSE_GDM3_PORT: + mac =3D MTK_GMAC3_ID; + break; + default: + break; + } + } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { mac =3D RX_DMA_GET_SPORT(trxd.rxd4) - 1; + } =20 if (unlikely(mac < 0 || mac >=3D MTK_MAX_DEVS || !eth->netdev[mac])) @@ -2161,7 +2193,6 @@ static int mtk_poll_tx_qdma(struct mtk_eth *eth, int = budget, =20 while ((cpu !=3D dma) && budget) { u32 next_cpu =3D desc->txd2; - int mac =3D 0; =20 desc =3D mtk_qdma_phys_to_virt(ring, desc->txd2); if ((desc->txd3 & TX_DMA_OWNER_CPU) =3D=3D 0) @@ -2169,15 +2200,13 @@ static int mtk_poll_tx_qdma(struct mtk_eth *eth, in= t budget, =20 tx_buf =3D mtk_desc_to_tx_buf(ring, desc, eth->soc->txrx.txd_size); - if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) - mac =3D 1; - if (!tx_buf->data) break; =20 if (tx_buf->data !=3D (void *)MTK_DMA_DUMMY_DESC) { if (tx_buf->type =3D=3D MTK_TYPE_SKB) - mtk_poll_tx_done(eth, state, mac, tx_buf->data); + mtk_poll_tx_done(eth, state, tx_buf->mac_id, + tx_buf->data); =20 budget--; } @@ -3788,7 +3817,24 @@ static int mtk_hw_init(struct mtk_eth *eth, bool res= et) mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); =20 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) { + /* PSE should not drop port1, port8 and port9 packets */ + mtk_w32(eth, 0x00000302, PSE_DROP_CFG); + + /* GDM and CDM Threshold */ + mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); + mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); + + /* Disable GDM1 RX CRC stripping */ + mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); + + /* PSE GDM3 MIB counter has incorrect hw default values, + * so the driver ought to read clear the values beforehand + * in case ethtool retrieve wrong mib values. + */ + for (i =3D 0; i < 0x80; i +=3D 0x4) + mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); + } else if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { /* PSE should not drop port8 and port9 packets from WDMA Tx */ mtk_w32(eth, 0x00000300, PSE_DROP_CFG); =20 @@ -4362,7 +4408,11 @@ static int mtk_add_mac(struct mtk_eth *eth, struct d= evice_node *np) } spin_lock_init(&mac->hw_stats->stats_lock); u64_stats_init(&mac->hw_stats->syncp); - mac->hw_stats->reg_offset =3D id * MTK_STAT_OFFSET; + + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) + mac->hw_stats->reg_offset =3D id * 0x80; + else + mac->hw_stats->reg_offset =3D id * 0x40; =20 /* phylink create */ err =3D of_get_phy_mode(np, &phy_mode); diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index 03510302df9e4..f8a447d859cd2 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -122,6 +122,7 @@ #define MTK_GDMA_ICS_EN BIT(22) #define MTK_GDMA_TCS_EN BIT(21) #define MTK_GDMA_UCS_EN BIT(20) +#define MTK_GDMA_STRP_CRC BIT(16) #define MTK_GDMA_TO_PDMA 0x0 #define MTK_GDMA_DROP_ALL 0x7777 =20 @@ -287,8 +288,6 @@ /* QDMA Interrupt grouping registers */ #define MTK_RLS_DONE_INT BIT(0) =20 -#define MTK_STAT_OFFSET 0x40 - /* QDMA TX NUM */ #define QID_BITS_V2(x) (((x) & 0x3f) << 16) #define MTK_QDMA_GMAC2_QID 8 @@ -301,6 +300,8 @@ #define TX_DMA_CHKSUM_V2 (0x7 << 28) #define TX_DMA_TSO_V2 BIT(31) =20 +#define TX_DMA_SPTAG_V3 BIT(27) + /* QDMA V2 descriptor txd4 */ #define TX_DMA_FPORT_SHIFT_V2 8 #define TX_DMA_FPORT_MASK_V2 0xf @@ -634,12 +635,6 @@ enum mtk_tx_flags { */ MTK_TX_FLAGS_SINGLE0 =3D 0x01, MTK_TX_FLAGS_PAGE0 =3D 0x02, - - /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted - * SKB out instead of looking up through hardware TX descriptor. - */ - MTK_TX_FLAGS_FPORT0 =3D 0x04, - MTK_TX_FLAGS_FPORT1 =3D 0x08, }; =20 /* This enum allows us to identify how the clock is defined on the array o= f the @@ -725,6 +720,35 @@ enum mtk_dev_state { MTK_RESETTING }; =20 +/* PSE Port Definition */ +enum mtk_pse_port { + PSE_ADMA_PORT =3D 0, + PSE_GDM1_PORT, + PSE_GDM2_PORT, + PSE_PPE0_PORT, + PSE_PPE1_PORT, + PSE_QDMA_TX_PORT, + PSE_QDMA_RX_PORT, + PSE_DROP_PORT, + PSE_WDMA0_PORT, + PSE_WDMA1_PORT, + PSE_TDMA_PORT, + PSE_NONE_PORT, + PSE_PPE2_PORT, + PSE_WDMA2_PORT, + PSE_EIP197_PORT, + PSE_GDM3_PORT, + PSE_PORT_MAX +}; + +/* GMAC Identifier */ +enum mtk_gmac_id { + MTK_GMAC1_ID =3D 0, + MTK_GMAC2_ID, + MTK_GMAC3_ID, + MTK_GMAC_ID_MAX +}; + enum mtk_tx_buf_type { MTK_TYPE_SKB, MTK_TYPE_XDP_TX, @@ -743,7 +767,8 @@ struct mtk_tx_buf { enum mtk_tx_buf_type type; void *data; =20 - u32 flags; + u16 mac_id; + u16 flags; DEFINE_DMA_UNMAP_ADDR(dma_addr0); DEFINE_DMA_UNMAP_LEN(dma_len0); DEFINE_DMA_UNMAP_ADDR(dma_addr1); @@ -821,6 +846,7 @@ enum mkt_eth_capabilities { MTK_QDMA_BIT, MTK_NETSYS_V1_BIT, MTK_NETSYS_V2_BIT, + MTK_NETSYS_V3_BIT, MTK_SOC_MT7628_BIT, MTK_RSTCTRL_PPE1_BIT, MTK_U3_COPHY_V2_BIT, @@ -857,6 +883,7 @@ enum mkt_eth_capabilities { #define MTK_QDMA BIT(MTK_QDMA_BIT) #define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) +#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CACDAEB64DD for ; Thu, 13 Jul 2023 02:20:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233570AbjGMCUs (ORCPT ); Wed, 12 Jul 2023 22:20:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233367AbjGMCUq (ORCPT ); Wed, 12 Jul 2023 22:20:46 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E271E1FF7; Wed, 12 Jul 2023 19:20:32 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlwU-0005ZO-2o; Thu, 13 Jul 2023 02:20:31 +0000 Date: Thu, 13 Jul 2023 03:20:17 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 7/9] net: ethernet: mtk_eth_soc: convert caps in mtk_soc_data struct to u64 Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi This is a preliminary patch to introduce support for MT7988 SoC. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_path.c | 22 +++---- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 62 ++++++++++---------- 2 files changed, 42 insertions(+), 42 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/eth= ernet/mediatek/mtk_eth_path.c index 317e447f49916..34ac492e047cb 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -15,10 +15,10 @@ struct mtk_eth_muxc { const char *name; int cap_bit; - int (*set_path)(struct mtk_eth *eth, int path); + int (*set_path)(struct mtk_eth *eth, u64 path); }; =20 -static const char *mtk_eth_path_name(int path) +static const char *mtk_eth_path_name(u64 path) { switch (path) { case MTK_ETH_PATH_GMAC1_RGMII: @@ -40,7 +40,7 @@ static const char *mtk_eth_path_name(int path) } } =20 -static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path) +static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) { bool updated =3D true; u32 val, mask, set; @@ -71,7 +71,7 @@ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth,= int path) return 0; } =20 -static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path) +static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path) { unsigned int val =3D 0; bool updated =3D true; @@ -94,7 +94,7 @@ static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *e= th, int path) return 0; } =20 -static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path) +static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path) { unsigned int val =3D 0, mask =3D 0, reg =3D 0; bool updated =3D true; @@ -125,7 +125,7 @@ static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth= , int path) return 0; } =20 -static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int pat= h) +static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 pat= h) { unsigned int val =3D 0; bool updated =3D true; @@ -163,7 +163,7 @@ static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mt= k_eth *eth, int path) return 0; } =20 -static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path) +static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) { unsigned int val =3D 0; bool updated =3D true; @@ -218,7 +218,7 @@ static const struct mtk_eth_muxc mtk_eth_muxc[] =3D { }, }; =20 -static int mtk_eth_mux_setup(struct mtk_eth *eth, int path) +static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path) { int i, err =3D 0; =20 @@ -249,7 +249,7 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, int p= ath) =20 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) { - int path; + u64 path; =20 path =3D (mac_id =3D=3D 0) ? MTK_ETH_PATH_GMAC1_SGMII : MTK_ETH_PATH_GMAC2_SGMII; @@ -260,7 +260,7 @@ int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int = mac_id) =20 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) { - int path =3D 0; + u64 path =3D 0; =20 if (mac_id =3D=3D 1) path =3D MTK_ETH_PATH_GMAC2_GEPHY; @@ -274,7 +274,7 @@ int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int = mac_id) =20 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) { - int path; + u64 path; =20 path =3D (mac_id =3D=3D 0) ? MTK_ETH_PATH_GMAC1_RGMII : MTK_ETH_PATH_GMAC2_RGMII; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index f8a447d859cd2..a927625efe023 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -869,44 +869,44 @@ enum mkt_eth_capabilities { }; =20 /* Supported hardware group on SoCs */ -#define MTK_RGMII BIT(MTK_RGMII_BIT) -#define MTK_TRGMII BIT(MTK_TRGMII_BIT) -#define MTK_SGMII BIT(MTK_SGMII_BIT) -#define MTK_ESW BIT(MTK_ESW_BIT) -#define MTK_GEPHY BIT(MTK_GEPHY_BIT) -#define MTK_MUX BIT(MTK_MUX_BIT) -#define MTK_INFRA BIT(MTK_INFRA_BIT) -#define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) -#define MTK_HWLRO BIT(MTK_HWLRO_BIT) -#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) -#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) -#define MTK_QDMA BIT(MTK_QDMA_BIT) -#define MTK_NETSYS_V1 BIT(MTK_NETSYS_V1_BIT) -#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) -#define MTK_NETSYS_V3 BIT(MTK_NETSYS_V3_BIT) -#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) -#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) -#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) +#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) +#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) +#define MTK_ESW BIT_ULL(MTK_ESW_BIT) +#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) +#define MTK_MUX BIT_ULL(MTK_MUX_BIT) +#define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) +#define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) +#define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) +#define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) +#define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) +#define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) +#define MTK_NETSYS_V1 BIT_ULL(MTK_NETSYS_V1_BIT) +#define MTK_NETSYS_V2 BIT_ULL(MTK_NETSYS_V2_BIT) +#define MTK_NETSYS_V3 BIT_ULL(MTK_NETSYS_V3_BIT) +#define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) +#define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) +#define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) =20 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ - BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ - BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) + BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ - BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) + BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ - BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ - BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) + BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) =20 /* Supported path present on SoCs */ -#define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) -#define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) -#define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) -#define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) -#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) -#define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) -#define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) +#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) +#define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) +#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) +#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) +#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) +#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) +#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) =20 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) @@ -1055,7 +1055,7 @@ struct mtk_reg_map { struct mtk_soc_data { const struct mtk_reg_map *reg_map; u32 ana_rgc3; - u32 caps; + u64 caps; u32 required_clks; bool required_pctl; u8 offload_version; --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99B22EB64DD for ; Thu, 13 Jul 2023 02:21:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233575AbjGMCVH (ORCPT ); Wed, 12 Jul 2023 22:21:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233256AbjGMCVE (ORCPT ); Wed, 12 Jul 2023 22:21:04 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0862AE74; Wed, 12 Jul 2023 19:20:57 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlws-0005a5-2I; Thu, 13 Jul 2023 02:20:55 +0000 Date: Thu, 13 Jul 2023 03:20:41 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 8/9] net: ethernet: mtk_eth_soc: convert clock bitmap to u64 Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The to-be-added MT7988 SoC adds many new clocks which need to be controlled by the Ethernet driver, which will result in their total number exceeding 32. Prepare by converting clock bitmaps into 64-bit types. Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 96 +++++++++++---------- 1 file changed, 49 insertions(+), 47 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index a927625efe023..66d30344b688c 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -666,54 +666,56 @@ enum mtk_clks_map { MTK_CLK_MAX }; =20 -#define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ - BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ - BIT(MTK_CLK_TRGPLL)) -#define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ - BIT(MTK_CLK_GP2) | \ - BIT(MTK_CLK_SGMII_TX_250M) | \ - BIT(MTK_CLK_SGMII_RX_250M) | \ - BIT(MTK_CLK_SGMII_CDR_REF) | \ - BIT(MTK_CLK_SGMII_CDR_FB) | \ - BIT(MTK_CLK_SGMII_CK) | \ - BIT(MTK_CLK_ETH2PLL)) +#define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) = | \ + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ + BIT_ULL(MTK_CLK_TRGPLL)) +#define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) = | \ + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ + BIT_ULL(MTK_CLK_GP2) | \ + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ + BIT_ULL(MTK_CLK_SGMII_CK) | \ + BIT_ULL(MTK_CLK_ETH2PLL)) #define MT7621_CLKS_BITMAP (0) #define MT7628_CLKS_BITMAP (0) -#define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ - BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ - BIT(MTK_CLK_SGMII_TX_250M) | \ - BIT(MTK_CLK_SGMII_RX_250M) | \ - BIT(MTK_CLK_SGMII_CDR_REF) | \ - BIT(MTK_CLK_SGMII_CDR_FB) | \ - BIT(MTK_CLK_SGMII2_TX_250M) | \ - BIT(MTK_CLK_SGMII2_RX_250M) | \ - BIT(MTK_CLK_SGMII2_CDR_REF) | \ - BIT(MTK_CLK_SGMII2_CDR_FB) | \ - BIT(MTK_CLK_SGMII_CK) | \ - BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) -#define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_C= LK_GP1) | \ - BIT(MTK_CLK_WOCPU0) | \ - BIT(MTK_CLK_SGMII_TX_250M) | \ - BIT(MTK_CLK_SGMII_RX_250M) | \ - BIT(MTK_CLK_SGMII_CDR_REF) | \ - BIT(MTK_CLK_SGMII_CDR_FB) | \ - BIT(MTK_CLK_SGMII2_TX_250M) | \ - BIT(MTK_CLK_SGMII2_RX_250M) | \ - BIT(MTK_CLK_SGMII2_CDR_REF) | \ - BIT(MTK_CLK_SGMII2_CDR_FB) | \ - BIT(MTK_CLK_SGMII_CK)) -#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_C= LK_GP1) | \ - BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ - BIT(MTK_CLK_SGMII_TX_250M) | \ - BIT(MTK_CLK_SGMII_RX_250M) | \ - BIT(MTK_CLK_SGMII_CDR_REF) | \ - BIT(MTK_CLK_SGMII_CDR_FB) | \ - BIT(MTK_CLK_SGMII2_TX_250M) | \ - BIT(MTK_CLK_SGMII2_RX_250M) | \ - BIT(MTK_CLK_SGMII2_CDR_REF) | \ - BIT(MTK_CLK_SGMII2_CDR_FB)) +#define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) = | \ + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ + BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ + BIT_ULL(MTK_CLK_SGMII_CK) | \ + BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) +#define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ + BIT_ULL(MTK_CLK_GP1) | \ + BIT_ULL(MTK_CLK_WOCPU0) | \ + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ + BIT_ULL(MTK_CLK_SGMII_CK)) +#define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ + BIT_ULL(MTK_CLK_GP1) | \ + BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ + BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) =20 enum mtk_dev_state { MTK_HW_INIT, @@ -1056,7 +1058,7 @@ struct mtk_soc_data { const struct mtk_reg_map *reg_map; u32 ana_rgc3; u64 caps; - u32 required_clks; + u64 required_clks; bool required_pctl; u8 offload_version; u8 hash_offset; --=20 2.41.0 From nobody Fri Sep 20 13:36:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6D1BC001B0 for ; Thu, 13 Jul 2023 02:21:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233577AbjGMCVk (ORCPT ); Wed, 12 Jul 2023 22:21:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232753AbjGMCVh (ORCPT ); Wed, 12 Jul 2023 22:21:37 -0400 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B131226B7; Wed, 12 Jul 2023 19:21:20 -0700 (PDT) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1qJlxG-0005aw-1x; Thu, 13 Jul 2023 02:21:19 +0000 Date: Thu, 13 Jul 2023 03:21:05 +0100 From: Daniel Golle To: netdev@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Russell King , =?iso-8859-1?Q?Bj=F8rn?= Mork , Florian Fainelli , Greg Ungerer Subject: [PATCH v2 net-next 9/9] net: ethernet: mtk_eth_soc: add basic support for MT7988 SoC Message-ID: <1bcf797afee57f0136d6f9f5233b1d57dc6a383f.1689012506.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lorenzo Bianconi Introduce support for ethernet chip available in MT7988 SoC to mtk_eth_soc driver. As a first step support only the first GMAC which is hard-wired to the internal DSA switch having 4 built-in gigabit Ethernet PHYs. Signed-off-by: Lorenzo Bianconi Signed-off-by: Daniel Golle --- drivers/net/ethernet/mediatek/mtk_eth_path.c | 14 +- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 201 +++++++++++++++++-- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 86 +++++++- 3 files changed, 273 insertions(+), 28 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/eth= ernet/mediatek/mtk_eth_path.c index 34ac492e047cb..cc84b30ace412 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -43,7 +43,7 @@ static const char *mtk_eth_path_name(u64 path) static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) { bool updated =3D true; - u32 val, mask, set; + u32 mask, set, reg; =20 switch (path) { case MTK_ETH_PATH_GMAC1_SGMII: @@ -59,11 +59,13 @@ static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *et= h, u64 path) break; } =20 - if (updated) { - val =3D mtk_r32(eth, MTK_MAC_MISC); - val =3D (val & mask) | set; - mtk_w32(eth, val, MTK_MAC_MISC); - } + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) + reg =3D MTK_MAC_MISC_V3; + else + reg =3D MTK_MAC_MISC; + + if (updated) + mtk_m32(eth, mask, set, reg); =20 dev_dbg(eth->dev, "path %s in %s updated =3D %d\n", mtk_eth_path_name(path), __func__, updated); diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.c index c47353f4af541..5a3463c05cfb5 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -152,6 +152,54 @@ static const struct mtk_reg_map mt7986_reg_map =3D { .pse_oq_sta =3D 0x01a0, }; =20 +static const struct mtk_reg_map mt7988_reg_map =3D { + .tx_irq_mask =3D 0x461c, + .tx_irq_status =3D 0x4618, + .pdma =3D { + .rx_ptr =3D 0x6900, + .rx_cnt_cfg =3D 0x6904, + .pcrx_ptr =3D 0x6908, + .glo_cfg =3D 0x6a04, + .rst_idx =3D 0x6a08, + .delay_irq =3D 0x6a0c, + .irq_status =3D 0x6a20, + .irq_mask =3D 0x6a28, + .adma_rx_dbg0 =3D 0x6a38, + .int_grp =3D 0x6a50, + }, + .qdma =3D { + .qtx_cfg =3D 0x4400, + .qtx_sch =3D 0x4404, + .rx_ptr =3D 0x4500, + .rx_cnt_cfg =3D 0x4504, + .qcrx_ptr =3D 0x4508, + .glo_cfg =3D 0x4604, + .rst_idx =3D 0x4608, + .delay_irq =3D 0x460c, + .fc_th =3D 0x4610, + .int_grp =3D 0x4620, + .hred =3D 0x4644, + .ctx_ptr =3D 0x4700, + .dtx_ptr =3D 0x4704, + .crx_ptr =3D 0x4710, + .drx_ptr =3D 0x4714, + .fq_head =3D 0x4720, + .fq_tail =3D 0x4724, + .fq_count =3D 0x4728, + .fq_blen =3D 0x472c, + .tx_sch_rate =3D 0x4798, + }, + .gdm1_cnt =3D 0x1c00, + .gdma_to_ppe =3D 0x3333, + .ppe_base =3D 0x2200, + .wdma_base =3D { + [0] =3D 0x4800, + [1] =3D 0x4c00, + }, + .pse_iq_sta =3D 0x0180, + .pse_oq_sta =3D 0x01a0, +}; + /* strings used by ethtool */ static const struct mtk_ethtool_stats { char str[ETH_GSTRING_LEN]; @@ -179,10 +227,54 @@ static const struct mtk_ethtool_stats { }; =20 static const char * const mtk_clks_source_name[] =3D { - "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", - "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" + "ethif", + "sgmiitop", + "esw", + "gp0", + "gp1", + "gp2", + "gp3", + "xgp1", + "xgp2", + "xgp3", + "crypto", + "fe", + "trgpll", + "sgmii_tx250m", + "sgmii_rx250m", + "sgmii_cdr_ref", + "sgmii_cdr_fb", + "sgmii2_tx250m", + "sgmii2_rx250m", + "sgmii2_cdr_ref", + "sgmii2_cdr_fb", + "sgmii_ck", + "eth2pll", + "wocpu0", + "wocpu1", + "netsys0", + "netsys1", + "ethwarp_wocpu2", + "ethwarp_wocpu1", + "ethwarp_wocpu0", + "top_usxgmii0_sel", + "top_usxgmii1_sel", + "top_sgm0_sel", + "top_sgm1_sel", + "top_xfi_phy0_xtal_sel", + "top_xfi_phy1_xtal_sel", + "top_eth_gmii_sel", + "top_eth_refck_50m_sel", + "top_eth_sys_200m_sel", + "top_eth_sys_sel", + "top_eth_xgmii_sel", + "top_eth_mii_sel", + "top_netsys_sel", + "top_netsys_500m_sel", + "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel", }; =20 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) @@ -195,7 +287,7 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg) return __raw_readl(eth->base + reg); } =20 -static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) { u32 val; =20 @@ -425,6 +517,19 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, mtk_w32(eth, tck, TRGMII_TCK_CTRL); } =20 +static void mtk_setup_bridge_switch(struct mtk_eth *eth) +{ + /* Force Port1 XGMAC Link Up */ + mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), + MTK_XGMAC_STS(MTK_GMAC1_ID)); + + /* Adjust GSW bridge IPG to 11 */ + mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, + (GSW_IPG_11 << GSWTX_IPG_SHIFT) | + (GSW_IPG_11 << GSWRX_IPG_SHIFT), + MTK_GSW_CFG); +} + static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *confi= g, phy_interface_t interface) { @@ -484,6 +589,8 @@ static void mtk_mac_config(struct phylink_config *confi= g, unsigned int mode, goto init_err; } break; + case PHY_INTERFACE_MODE_INTERNAL: + break; default: goto err_phy; } @@ -562,6 +669,15 @@ static void mtk_mac_config(struct phylink_config *conf= ig, unsigned int mode, return; } =20 + /* Setup gmac */ + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3) && + mac->interface =3D=3D PHY_INTERFACE_MODE_INTERNAL) { + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); + + mtk_setup_bridge_switch(eth); + } + return; =20 err_phy: @@ -807,11 +923,16 @@ static int mtk_mdio_init(struct mtk_eth *eth) } divider =3D min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); =20 + /* Configure MDC Turbo Mode */ + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) + mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); + /* Configure MDC Divider */ - val =3D mtk_r32(eth, MTK_PPSC); - val &=3D ~PPSC_MDC_CFG; - val |=3D FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; - mtk_w32(eth, val, MTK_PPSC); + val =3D FIELD_PREP(PPSC_MDC_CFG, divider); + if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V1) || + MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) + val |=3D PPSC_MDC_TURBO; + mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); =20 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); =20 @@ -1272,10 +1393,19 @@ static void mtk_tx_set_dma_desc_v2(struct net_devic= e *dev, void *txd, data |=3D TX_DMA_LS0; WRITE_ONCE(desc->txd3, data); =20 - if (mac->id =3D=3D MTK_GMAC3_ID) - data =3D PSE_GDM3_PORT; - else - data =3D (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ + /* set forward port */ + switch (mac->id) { + case MTK_GMAC1_ID: + data =3D PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; + break; + case MTK_GMAC2_ID: + data =3D PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; + break; + case MTK_GMAC3_ID: + data =3D PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; + break; + } + data |=3D TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); WRITE_ONCE(desc->txd4, data); =20 @@ -4462,6 +4592,17 @@ static int mtk_add_mac(struct mtk_eth *eth, struct d= evice_node *np) mac->phylink_config.supported_interfaces); } =20 + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_NETSYS_V3_BIT) && + MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && + id =3D=3D MTK_GMAC1_ID) { + mac->phylink_config.mac_capabilities =3D MAC_ASYM_PAUSE | + MAC_SYM_PAUSE | + MAC_10000FD; + phy_interface_zero(mac->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + mac->phylink_config.supported_interfaces); + } + phylink =3D phylink_create(&mac->phylink_config, of_fwnode_handle(mac->of_node), phy_mode, &mtk_phylink_ops); @@ -4981,6 +5122,23 @@ static const struct mtk_soc_data mt7986_data =3D { }, }; =20 +static const struct mtk_soc_data mt7988_data =3D { + .reg_map =3D &mt7988_reg_map, + .ana_rgc3 =3D 0x128, + .caps =3D MT7988_CAPS, + .hw_features =3D MTK_HW_FEATURES, + .required_clks =3D MT7988_CLKS_BITMAP, + .required_pctl =3D false, + .txrx =3D { + .txd_size =3D sizeof(struct mtk_tx_dma_v2), + .rxd_size =3D sizeof(struct mtk_rx_dma_v2), + .rx_irq_done_mask =3D MTK_RX_DONE_INT_V2, + .rx_dma_l4_valid =3D RX_DMA_L4_VALID_V2, + .dma_max_len =3D MTK_TX_DMA_BUF_LEN_V2, + .dma_len_offset =3D 8, + }, +}; + static const struct mtk_soc_data rt5350_data =3D { .reg_map =3D &mt7628_reg_map, .caps =3D MT7628_CAPS, @@ -4998,14 +5156,15 @@ static const struct mtk_soc_data rt5350_data =3D { }; =20 const struct of_device_id of_mtk_match[] =3D { - { .compatible =3D "mediatek,mt2701-eth", .data =3D &mt2701_data}, - { .compatible =3D "mediatek,mt7621-eth", .data =3D &mt7621_data}, - { .compatible =3D "mediatek,mt7622-eth", .data =3D &mt7622_data}, - { .compatible =3D "mediatek,mt7623-eth", .data =3D &mt7623_data}, - { .compatible =3D "mediatek,mt7629-eth", .data =3D &mt7629_data}, - { .compatible =3D "mediatek,mt7981-eth", .data =3D &mt7981_data}, - { .compatible =3D "mediatek,mt7986-eth", .data =3D &mt7986_data}, - { .compatible =3D "ralink,rt5350-eth", .data =3D &rt5350_data}, + { .compatible =3D "mediatek,mt2701-eth", .data =3D &mt2701_data }, + { .compatible =3D "mediatek,mt7621-eth", .data =3D &mt7621_data }, + { .compatible =3D "mediatek,mt7622-eth", .data =3D &mt7622_data }, + { .compatible =3D "mediatek,mt7623-eth", .data =3D &mt7623_data }, + { .compatible =3D "mediatek,mt7629-eth", .data =3D &mt7629_data }, + { .compatible =3D "mediatek,mt7981-eth", .data =3D &mt7981_data }, + { .compatible =3D "mediatek,mt7986-eth", .data =3D &mt7986_data }, + { .compatible =3D "mediatek,mt7988-eth", .data =3D &mt7988_data }, + { .compatible =3D "ralink,rt5350-eth", .data =3D &rt5350_data }, {}, }; MODULE_DEVICE_TABLE(of, of_mtk_match); diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethe= rnet/mediatek/mtk_eth_soc.h index 66d30344b688c..37a2295e1be9b 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -117,7 +117,8 @@ #define MTK_CDMP_EG_CTRL 0x404 =20 /* GDM Exgress Control Register */ -#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) +#define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x =3D (x); (_x =3D=3D MTK_GMAC3_= ID) ? \ + 0x540 : 0x500 + (_x * 0x1000); }) #define MTK_GDMA_SPECIAL_TAG BIT(24) #define MTK_GDMA_ICS_EN BIT(22) #define MTK_GDMA_TCS_EN BIT(21) @@ -126,6 +127,11 @@ #define MTK_GDMA_TO_PDMA 0x0 #define MTK_GDMA_DROP_ALL 0x7777 =20 +/* GDM Egress Control Register */ +#define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x =3D (x); (_x =3D=3D MTK_GMAC3_= ID) ? \ + 0x544 : 0x504 + (_x * 0x1000); }) +#define MTK_GDMA_XGDM_SEL BIT(31) + /* Unicast Filter MAC Address Register - Low */ #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) =20 @@ -389,7 +395,26 @@ #define PHY_IAC_TIMEOUT HZ =20 #define MTK_MAC_MISC 0x1000c +#define MTK_MAC_MISC_V3 0x10010 #define MTK_MUX_TO_ESW BIT(0) +#define MISC_MDC_TURBO BIT(4) + +/* XMAC status registers */ +#define MTK_XGMAC_STS(x) (((x) =3D=3D MTK_GMAC3_ID) ? 0x1001C : 0x1000C) +#define MTK_XGMAC_FORCE_LINK(x) (((x) =3D=3D MTK_GMAC2_ID) ? BIT(31) : BIT= (15)) +#define MTK_USXGMII_PCS_LINK BIT(8) +#define MTK_XGMAC_RX_FC BIT(5) +#define MTK_XGMAC_TX_FC BIT(4) +#define MTK_USXGMII_PCS_MODE GENMASK(3, 1) +#define MTK_XGMAC_LINK_STS BIT(0) + +/* GSW bridge registers */ +#define MTK_GSW_CFG (0x10080) +#define GSWTX_IPG_MASK GENMASK(19, 16) +#define GSWTX_IPG_SHIFT 16 +#define GSWRX_IPG_MASK GENMASK(3, 0) +#define GSWRX_IPG_SHIFT 0 +#define GSW_IPG_11 11 =20 /* Mac control registers */ #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) @@ -647,6 +672,11 @@ enum mtk_clks_map { MTK_CLK_GP0, MTK_CLK_GP1, MTK_CLK_GP2, + MTK_CLK_GP3, + MTK_CLK_XGP1, + MTK_CLK_XGP2, + MTK_CLK_XGP3, + MTK_CLK_CRYPTO, MTK_CLK_FE, MTK_CLK_TRGPLL, MTK_CLK_SGMII_TX_250M, @@ -663,6 +693,27 @@ enum mtk_clks_map { MTK_CLK_WOCPU1, MTK_CLK_NETSYS0, MTK_CLK_NETSYS1, + MTK_CLK_ETHWARP_WOCPU2, + MTK_CLK_ETHWARP_WOCPU1, + MTK_CLK_ETHWARP_WOCPU0, + MTK_CLK_TOP_USXGMII_SBUS_0_SEL, + MTK_CLK_TOP_USXGMII_SBUS_1_SEL, + MTK_CLK_TOP_SGM_0_SEL, + MTK_CLK_TOP_SGM_1_SEL, + MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, + MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, + MTK_CLK_TOP_ETH_GMII_SEL, + MTK_CLK_TOP_ETH_REFCK_50M_SEL, + MTK_CLK_TOP_ETH_SYS_200M_SEL, + MTK_CLK_TOP_ETH_SYS_SEL, + MTK_CLK_TOP_ETH_XGMII_SEL, + MTK_CLK_TOP_ETH_MII_SEL, + MTK_CLK_TOP_NETSYS_SEL, + MTK_CLK_TOP_NETSYS_500M_SEL, + MTK_CLK_TOP_NETSYS_PAO_2X_SEL, + MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, + MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, + MTK_CLK_TOP_NETSYS_WARP_SEL, MTK_CLK_MAX }; =20 @@ -716,6 +767,36 @@ enum mtk_clks_map { BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) +#define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ + BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ + BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ + BIT_ULL(MTK_CLK_CRYPTO) | \ + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ + BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ + BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ + BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ + BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ + BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ + BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ + BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ + BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ + BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ + BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ + BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ + BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ + BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ + BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ + BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ + BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ + BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ + BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ + BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) =20 enum mtk_dev_state { MTK_HW_INIT, @@ -975,6 +1056,8 @@ enum mkt_eth_capabilities { MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) =20 +#define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_NETSYS_V3 | MTK_RSTCTR= L_PPE1) + struct mtk_tx_dma_desc_info { dma_addr_t addr; u32 size; @@ -1302,6 +1385,7 @@ void mtk_stats_update_mac(struct mtk_mac *mac); =20 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); u32 mtk_r32(struct mtk_eth *eth, unsigned reg); +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg); =20 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); --=20 2.41.0