From nobody Fri Sep 20 20:28:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 344EFC77B7C for ; Thu, 20 Apr 2023 12:36:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231765AbjDTMgN (ORCPT ); Thu, 20 Apr 2023 08:36:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231715AbjDTMgD (ORCPT ); Thu, 20 Apr 2023 08:36:03 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 71B356EB9; Thu, 20 Apr 2023 05:35:58 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1ppTW0-0005Vz-2e; Thu, 20 Apr 2023 14:35:56 +0200 Date: Thu, 20 Apr 2023 13:35:51 +0100 From: Daniel Golle To: devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Matthias Brugger , AngeloGioacchino Del Regno , John Crispin Subject: [PATCH v2 1/2] dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible Message-ID: <2662c29ec80458852bb8c9041656bca46e2662dd.1681992038.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string for the PWM unit found of the MediaTek MT7981 SoC. This is in preparation to adding support in the pwm-mediatek.c driver. Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- No changes since v1. Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml= b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml index 8e176ba7a525f..0fbe8a6469eb2 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt7623-pwm - mediatek,mt7628-pwm - mediatek,mt7629-pwm + - mediatek,mt7981-pwm - mediatek,mt7986-pwm - mediatek,mt8183-pwm - mediatek,mt8365-pwm --=20 2.40.0 From nobody Fri Sep 20 20:28:51 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DC83C77B76 for ; Thu, 20 Apr 2023 12:36:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231532AbjDTMgr (ORCPT ); Thu, 20 Apr 2023 08:36:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231394AbjDTMgp (ORCPT ); Thu, 20 Apr 2023 08:36:45 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42AC92D43; Thu, 20 Apr 2023 05:36:31 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96) (envelope-from ) id 1ppTWX-0005XF-2E; Thu, 20 Apr 2023 14:36:29 +0200 Date: Thu, 20 Apr 2023 13:36:23 +0100 From: Daniel Golle To: linux-pwm@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Matthias Brugger , AngeloGioacchino Del Regno , John Crispin Subject: [PATCH v2 2/2] pwm: mediatek: Add support for MT7981 Message-ID: <7c6e31c844642c199f223f4229a04a37b57a34f3.1681992038.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PWM unit on MT7981 uses different register offsets than previous MediaTek PWM units. Add support for these new offsets and add support for PWM on MT7981 which has 3 PWM channels, one of them is typically used for a temperature controlled fan. Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno --- Changes since v1: * use pointer to reg_offset instead of u8 reg_ver and if-else drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 5b5eeaff35da6..7a51d210a8778 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -38,6 +38,7 @@ struct pwm_mediatek_of_data { unsigned int num_pwms; bool pwm45_fixup; bool has_ck_26m_sel; + const unsigned int *reg_offset; }; =20 /** @@ -59,10 +60,14 @@ struct pwm_mediatek_chip { const struct pwm_mediatek_of_data *soc; }; =20 -static const unsigned int pwm_mediatek_reg_offset[] =3D { +static const unsigned int mtk_pwm_reg_offset_v1[] =3D { 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 }; =20 +static const unsigned int mtk_pwm_reg_offset_v2[] =3D { + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240 +}; + static inline struct pwm_mediatek_chip * to_pwm_mediatek_chip(struct pwm_chip *chip) { @@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(struct pwm_media= tek_chip *chip, unsigned int num, unsigned int offset, u32 value) { - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); + writel(value, chip->regs + chip->soc->reg_offset[num] + offset); } =20 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *p= wm, @@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data mt2712_pwm_d= ata =3D { .num_pwms =3D 8, .pwm45_fixup =3D false, .has_ck_26m_sel =3D false, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt6795_pwm_data =3D { .num_pwms =3D 7, .pwm45_fixup =3D false, .has_ck_26m_sel =3D false, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7622_pwm_data =3D { .num_pwms =3D 6, .pwm45_fixup =3D false, .has_ck_26m_sel =3D true, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7623_pwm_data =3D { .num_pwms =3D 5, .pwm45_fixup =3D true, .has_ck_26m_sel =3D false, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7628_pwm_data =3D { .num_pwms =3D 4, .pwm45_fixup =3D true, .has_ck_26m_sel =3D false, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt7629_pwm_data =3D { .num_pwms =3D 1, .pwm45_fixup =3D false, .has_ck_26m_sel =3D false, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 -static const struct pwm_mediatek_of_data mt8183_pwm_data =3D { - .num_pwms =3D 4, +static const struct pwm_mediatek_of_data mt7981_pwm_data =3D { + .num_pwms =3D 3, .pwm45_fixup =3D false, .has_ck_26m_sel =3D true, + .reg_offset =3D mtk_pwm_reg_offset_v2, }; =20 -static const struct pwm_mediatek_of_data mt8365_pwm_data =3D { - .num_pwms =3D 3, +static const struct pwm_mediatek_of_data mt7986_pwm_data =3D { + .num_pwms =3D 2, .pwm45_fixup =3D false, .has_ck_26m_sel =3D true, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 -static const struct pwm_mediatek_of_data mt7986_pwm_data =3D { - .num_pwms =3D 2, +static const struct pwm_mediatek_of_data mt8183_pwm_data =3D { + .num_pwms =3D 4, + .pwm45_fixup =3D false, + .has_ck_26m_sel =3D true, + .reg_offset =3D mtk_pwm_reg_offset_v1, +}; + +static const struct pwm_mediatek_of_data mt8365_pwm_data =3D { + .num_pwms =3D 3, .pwm45_fixup =3D false, .has_ck_26m_sel =3D true, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct pwm_mediatek_of_data mt8516_pwm_data =3D { .num_pwms =3D 5, .pwm45_fixup =3D false, .has_ck_26m_sel =3D true, + .reg_offset =3D mtk_pwm_reg_offset_v1, }; =20 static const struct of_device_id pwm_mediatek_of_match[] =3D { @@ -348,6 +370,7 @@ static const struct of_device_id pwm_mediatek_of_match[= ] =3D { { .compatible =3D "mediatek,mt7623-pwm", .data =3D &mt7623_pwm_data }, { .compatible =3D "mediatek,mt7628-pwm", .data =3D &mt7628_pwm_data }, { .compatible =3D "mediatek,mt7629-pwm", .data =3D &mt7629_pwm_data }, + { .compatible =3D "mediatek,mt7981-pwm", .data =3D &mt7981_pwm_data }, { .compatible =3D "mediatek,mt7986-pwm", .data =3D &mt7986_pwm_data }, { .compatible =3D "mediatek,mt8183-pwm", .data =3D &mt8183_pwm_data }, { .compatible =3D "mediatek,mt8365-pwm", .data =3D &mt8365_pwm_data }, --=20 2.40.0