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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id g80-20020a0ddd53000000b00545a08184b0sm3942619ywe.64.2023.04.05.08.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 08:45:51 -0700 (PDT) From: William Breathitt Gray To: Linus Walleij , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Mark Brown , William Breathitt Gray , techsupport@winsystems.com, pdemetrotion@winsystems.com, quarium@gmail.com, jhentges@accesio.com, jay.dolan@accesio.com Subject: [PATCH v6 1/3] regmap: Pass irq_drv_data as a parameter for set_type_config() Date: Wed, 5 Apr 2023 11:45:42 -0400 Message-Id: <20e15cd3afae80922b7e0577c7741df86b3390c5.1680708357.git.william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow the struct regmap_irq_chip set_type_config() callback to access irq_drv_data by passing it as a parameter. Signed-off-by: William Breathitt Gray Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- Changes in v6: - Wrap lines to 80 characters rather than 100 Changes in v5: - Wrap lines to 100 characters rather than 80 Changes in v4: none Changes in v3: - Drop map from set_type_config() parameter list; regmap can be passed by irq_drv_data instead Changes in v2: none drivers/base/regmap/regmap-irq.c | 8 +++++--- include/linux/regmap.h | 6 ++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-= irq.c index ff6b585b9049..362926d155a4 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -328,8 +328,8 @@ static int regmap_irq_set_type(struct irq_data *data, u= nsigned int type) } =20 if (d->chip->set_type_config) { - ret =3D d->chip->set_type_config(d->config_buf, type, - irq_data, reg); + ret =3D d->chip->set_type_config(d->config_buf, type, irq_data, + reg, d->chip->irq_drv_data); if (ret) return ret; } @@ -653,13 +653,15 @@ EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); * @type: The requested IRQ type. * @irq_data: The IRQ being configured. * @idx: Index of the irq's config registers within each array `buf[i]` + * @irq_drv_data: Driver specific IRQ data * * This is a &struct regmap_irq_chip->set_type_config callback suitable for * chips with one config register. Register values are updated according to * the &struct regmap_irq_type data associated with an IRQ. */ int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int typ= e, - const struct regmap_irq *irq_data, int idx) + const struct regmap_irq *irq_data, + int idx, void *irq_drv_data) { const struct regmap_irq_type *t =3D &irq_data->type; =20 diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 8d9d601da782..18311c12c44a 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1651,7 +1651,8 @@ struct regmap_irq_chip { int (*set_type_virt)(unsigned int **buf, unsigned int type, unsigned long hwirq, int reg); int (*set_type_config)(unsigned int **buf, unsigned int type, - const struct regmap_irq *irq_data, int idx); + const struct regmap_irq *irq_data, int idx, + void *irq_drv_data); unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, unsigned int base, int index); void *irq_drv_data; @@ -1660,7 +1661,8 @@ struct regmap_irq_chip { unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *da= ta, unsigned int base, int index); int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int typ= e, - const struct regmap_irq *irq_data, int idx); + const struct regmap_irq *irq_data, + int idx, void *irq_drv_data); =20 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, int irq_base, const struct regmap_irq_chip *chip, --=20 2.39.2 From nobody Wed Feb 11 06:53:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F52CC761A6 for ; Wed, 5 Apr 2023 15:46:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238987AbjDEPqJ (ORCPT ); Wed, 5 Apr 2023 11:46:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238989AbjDEPqD (ORCPT ); Wed, 5 Apr 2023 11:46:03 -0400 Received: from mail-yw1-x112d.google.com (mail-yw1-x112d.google.com [IPv6:2607:f8b0:4864:20::112d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65D434C20 for ; Wed, 5 Apr 2023 08:45:54 -0700 (PDT) Received: by mail-yw1-x112d.google.com with SMTP id 00721157ae682-54bfa5e698eso18165767b3.13 for ; Wed, 05 Apr 2023 08:45:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680709553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CsoHYyi39hnlLl/jW75wIYI+lV5K1+6WfvoU3ehDI5E=; b=AtAYoJtvNB3SWI41TIZdIeJioxPONet3BVECPIemCEgkVK3tC1pQ9XEB9cL210J5DU bW6qHhxOv5l1C2TutFEB/PV0YFELWFjBn2SZSK9vjsqdWZRD2fbJkm12nVznj6msvVWu h/r48Jp1CVUuYL7y7UPfb1R0WpwYasxtNRPTBJ2PUKSRPhX7xsSk9/HqVLu/5QGgmekU 1jjvgqfwv6FKbj7IRcQWfiwmdnKjIqQrEIemAlcBqpxeIlPr6PrhEd9Ou1JPC6S3Lcwe bulk9rsf5h3yhseVtOrP7WqAvhmqs38CT6dLHP5uh7g0z9Z98EIWqjHCFaTgLk0+mgff 5uqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680709553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CsoHYyi39hnlLl/jW75wIYI+lV5K1+6WfvoU3ehDI5E=; b=jsTfQZtmGVpmRLtleYtUHATQptVRvgVVduBk66EbSYnnbf4m4maYuCrXtTuwsP6kwE FJQOkYqoHFyw+oO7DIfVZ4ipnVkHyy5T4XF63yhKyYYiiiwveicsh980Cp2KXIftLJ7D 9ElZ4GRz6mbbOrFRP8p0hbuiUE3e8A4VPbpDzWuGbg2QAV/WkSX7lz8EUQCzH4O4UsgX raTBQUYWH9W5f3lhMpR4wE7Q4/73P6txm+KpxJyTZ6qtai3NlB250PiC9mmIJ8d3IKJJ j0Y1p/xm1NR3tSwhhVdPG7qTvZQcHSgbRElPD7Exig/E6bJYAlbHi16rtYD1PYQVb3s5 x0vg== X-Gm-Message-State: AAQBX9eXpTPbXX6ODw6qrqRES9ZpRmCWd1JVlf/Q1D9wJnMSn3snZT7K lQhYhngl9zSV81tv/PYYZ4vsSg== X-Google-Smtp-Source: AKy350aXqFGmSsKI1Du4zg/qdbSTWIGKWPIebJMB6FmXgLIRwxdY45ap6vix4GOIIIVM2PFnpx3iPg== X-Received: by 2002:a0d:e401:0:b0:546:3229:cc04 with SMTP id n1-20020a0de401000000b005463229cc04mr5905533ywe.52.1680709553219; Wed, 05 Apr 2023 08:45:53 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id g80-20020a0ddd53000000b00545a08184b0sm3942619ywe.64.2023.04.05.08.45.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 08:45:52 -0700 (PDT) From: William Breathitt Gray To: Linus Walleij , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Mark Brown , William Breathitt Gray , Arnaud de Turckheim , John Hentges , Jay Dolan , Michael Walle Subject: [PATCH v6 2/3] gpio: pcie-idio-24: Migrate to the regmap API Date: Wed, 5 Apr 2023 11:45:43 -0400 Message-Id: <3091e387b1d2eac011a1d84e493663aa2acf982e.1680708357.git.william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. For the PCIe-IDIO-24 series of devices, the following BARs are available: BAR[0]: memory mapped PEX8311 BAR[1]: I/O mapped PEX8311 BAR[2]: I/O mapped card registers There are 24 FET Output lines, 24 Isolated Input lines, and 8 TTL/CMOS lines (which may be configured for either output or input). The GPIO lines are exposed by the following card registers: Base +0x0-0x2 (Read/Write): FET Outputs Base +0xB (Read/Write): TTL/CMOS Base +0x4-0x6 (Read): Isolated Inputs Base +0x7 (Read): TTL/CMOS In order for the device to support interrupts, the PLX PEX8311 internal PCI wire interrupt and local interrupt input must first be enabled. The following card registers for Change-Of-State may be used: Base +0x8-0xA (Read): COS Status Inputs Base +0x8-0xA (Write): COS Clear Inputs Base +0xB (Read): COS Status TTL/CMOS Base +0xB (Write): COS Clear TTL/CMOS Base +0xE (Read/Write): COS Enable The COS Enable register is used to enable/disable interrupts and configure the interrupt levels; each bit maps to a group of eight inputs as described below: Bit 0: IRQ EN Rising Edge IN0-7 Bit 1: IRQ EN Rising Edge IN8-15 Bit 2: IRQ EN Rising Edge IN16-23 Bit 3: IRQ EN Rising Edge TTL0-7 Bit 4: IRQ EN Falling Edge IN0-7 Bit 5: IRQ EN Falling Edge IN8-15 Bit 6: IRQ EN Falling Edge IN16-23 Bit 7: IRQ EN Falling Edge TTL0-7 An interrupt is asserted when a change-of-state matching the interrupt level configuration respective for a particular group of eight inputs with enabled COS is detected. The COS Status registers may be read to determine which inputs have changed; if interrupts were enabled, an IRQ will be generated for the set bits in these registers. Writing the value read from the COS Status register back to the respective COS Clear register will clear just those interrupts. Reviewed-by: Michael Walle Signed-off-by: William Breathitt Gray Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- Changes in v6: - Remove regmap_config max_register lines as superfluous - Enable use_raw_spinlock to prevent deadlocks when running -rt kernels - Rename exit_early label to the more descriptive exit_unlock - Check regmap_update_bit() ret value before goto exit_unlock Changes in v5: - Refactor for map parameter removal from handle_mask_sync() - Cleanups and line wrappings to 100 characters rather than 80 - Adjust to change mutex lock to raw_spin_lock_t - Remove pex8311_intcsr table configurations as superfluous - Adjust to set pex8311_intcsr_regmap_config reg_base to PLX_PEX8311_PCI_LCS_INTCSR Changes in v4: - Allocate idio24gpio before using it in idio_24_probe() Changes in v3: - Adjust idio_24_set_type_config() for parameter list - Add mutex to prevent clobbering the COS_ENABLE register when masking IRQ and setting their type configuration Changes in v2: - Simplify PCIe-IDIO-24 register offset defines to remove superfluous arithmetic - Check for NULL pointer after chip->irq_drv_data allocation - Set gpio_regmap drvdata and use gpio_regmap_get_drvdata() to get the regmap in idio_24_reg_map_xlate() drivers/gpio/Kconfig | 3 + drivers/gpio/gpio-pcie-idio-24.c | 677 +++++++++++-------------------- 2 files changed, 250 insertions(+), 430 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 68f58b0ba79f..79359f663b3d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1587,7 +1587,10 @@ config GPIO_PCI_IDIO_16 =20 config GPIO_PCIE_IDIO_24 tristate "ACCES PCIe-IDIO-24 GPIO support" + select REGMAP_IRQ + select REGMAP_MMIO select GPIOLIB_IRQCHIP + select GPIO_REGMAP help Enables GPIO support for the ACCES PCIe-IDIO-24 family (PCIe-IDIO-24, PCIe-IDI-24, PCIe-IDO-24, PCIe-IDIO-12). An interrupt is generated diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio= -24.c index 463c0613abb9..2efd1b1a0805 100644 --- a/drivers/gpio/gpio-pcie-idio-24.c +++ b/drivers/gpio/gpio-pcie-idio-24.c @@ -6,16 +6,15 @@ * This driver supports the following ACCES devices: PCIe-IDIO-24, * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12. */ -#include -#include +#include #include -#include -#include -#include -#include +#include +#include +#include #include #include #include +#include #include #include =20 @@ -59,422 +58,224 @@ #define PLX_PEX8311_PCI_LCS_INTCSR 0x68 #define INTCSR_INTERNAL_PCI_WIRE BIT(8) #define INTCSR_LOCAL_INPUT BIT(11) +#define IDIO_24_ENABLE_IRQ (INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOC= AL_INPUT) + +#define IDIO_24_OUT_BASE 0x0 +#define IDIO_24_TTLCMOS_OUT_REG 0x3 +#define IDIO_24_IN_BASE 0x4 +#define IDIO_24_TTLCMOS_IN_REG 0x7 +#define IDIO_24_COS_STATUS_BASE 0x8 +#define IDIO_24_CONTROL_REG 0xC +#define IDIO_24_COS_ENABLE 0xE +#define IDIO_24_SOFT_RESET 0xF + +#define CONTROL_REG_OUT_MODE BIT(1) + +#define COS_ENABLE_RISING BIT(1) +#define COS_ENABLE_FALLING BIT(4) +#define COS_ENABLE_BOTH (COS_ENABLE_RISING | COS_ENABLE_FALLING) + +static const struct regmap_config pex8311_intcsr_regmap_config =3D { + .name =3D "pex8311_intcsr", + .reg_bits =3D 32, + .reg_stride =3D 1, + .reg_base =3D PLX_PEX8311_PCI_LCS_INTCSR, + .val_bits =3D 32, + .io_port =3D true, +}; =20 -/** - * struct idio_24_gpio_reg - GPIO device registers structure - * @out0_7: Read: FET Outputs 0-7 - * Write: FET Outputs 0-7 - * @out8_15: Read: FET Outputs 8-15 - * Write: FET Outputs 8-15 - * @out16_23: Read: FET Outputs 16-23 - * Write: FET Outputs 16-23 - * @ttl_out0_7: Read: TTL/CMOS Outputs 0-7 - * Write: TTL/CMOS Outputs 0-7 - * @in0_7: Read: Isolated Inputs 0-7 - * Write: Reserved - * @in8_15: Read: Isolated Inputs 8-15 - * Write: Reserved - * @in16_23: Read: Isolated Inputs 16-23 - * Write: Reserved - * @ttl_in0_7: Read: TTL/CMOS Inputs 0-7 - * Write: Reserved - * @cos0_7: Read: COS Status Inputs 0-7 - * Write: COS Clear Inputs 0-7 - * @cos8_15: Read: COS Status Inputs 8-15 - * Write: COS Clear Inputs 8-15 - * @cos16_23: Read: COS Status Inputs 16-23 - * Write: COS Clear Inputs 16-23 - * @cos_ttl0_7: Read: COS Status TTL/CMOS 0-7 - * Write: COS Clear TTL/CMOS 0-7 - * @ctl: Read: Control Register - * Write: Control Register - * @reserved: Read: Reserved - * Write: Reserved - * @cos_enable: Read: COS Enable - * Write: COS Enable - * @soft_reset: Read: IRQ Output Pin Status - * Write: Software Board Reset - */ -struct idio_24_gpio_reg { - u8 out0_7; - u8 out8_15; - u8 out16_23; - u8 ttl_out0_7; - u8 in0_7; - u8 in8_15; - u8 in16_23; - u8 ttl_in0_7; - u8 cos0_7; - u8 cos8_15; - u8 cos16_23; - u8 cos_ttl0_7; - u8 ctl; - u8 reserved; - u8 cos_enable; - u8 soft_reset; +static const struct regmap_range idio_24_wr_ranges[] =3D { + regmap_reg_range(0x0, 0x3), regmap_reg_range(0x8, 0xC), + regmap_reg_range(0xE, 0xF), +}; +static const struct regmap_range idio_24_rd_ranges[] =3D { + regmap_reg_range(0x0, 0xC), regmap_reg_range(0xE, 0xF), +}; +static const struct regmap_range idio_24_volatile_ranges[] =3D { + regmap_reg_range(0x4, 0xB), regmap_reg_range(0xF, 0xF), +}; +static const struct regmap_access_table idio_24_wr_table =3D { + .yes_ranges =3D idio_24_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(idio_24_wr_ranges), +}; +static const struct regmap_access_table idio_24_rd_table =3D { + .yes_ranges =3D idio_24_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(idio_24_rd_ranges), +}; +static const struct regmap_access_table idio_24_volatile_table =3D { + .yes_ranges =3D idio_24_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(idio_24_volatile_ranges), +}; + +static const struct regmap_config idio_24_regmap_config =3D { + .reg_bits =3D 8, + .reg_stride =3D 1, + .val_bits =3D 8, + .io_port =3D true, + .wr_table =3D &idio_24_wr_table, + .rd_table =3D &idio_24_rd_table, + .volatile_table =3D &idio_24_volatile_table, + .cache_type =3D REGCACHE_FLAT, + .use_raw_spinlock =3D true, +}; + +#define IDIO_24_NGPIO_PER_REG 8 +#define IDIO_24_REGMAP_IRQ(_id) \ + [24 + _id] =3D { \ + .reg_offset =3D (_id) / IDIO_24_NGPIO_PER_REG, \ + .mask =3D BIT((_id) % IDIO_24_NGPIO_PER_REG), \ + .type =3D { .types_supported =3D IRQ_TYPE_EDGE_BOTH }, \ + } +#define IDIO_24_IIN_IRQ(_id) IDIO_24_REGMAP_IRQ(_id) +#define IDIO_24_TTL_IRQ(_id) IDIO_24_REGMAP_IRQ(24 + _id) + +static const struct regmap_irq idio_24_regmap_irqs[] =3D { + IDIO_24_IIN_IRQ(0), IDIO_24_IIN_IRQ(1), IDIO_24_IIN_IRQ(2), /* IIN 0-2 */ + IDIO_24_IIN_IRQ(3), IDIO_24_IIN_IRQ(4), IDIO_24_IIN_IRQ(5), /* IIN 3-5 */ + IDIO_24_IIN_IRQ(6), IDIO_24_IIN_IRQ(7), IDIO_24_IIN_IRQ(8), /* IIN 6-8 */ + IDIO_24_IIN_IRQ(9), IDIO_24_IIN_IRQ(10), IDIO_24_IIN_IRQ(11), /* IIN 9-11= */ + IDIO_24_IIN_IRQ(12), IDIO_24_IIN_IRQ(13), IDIO_24_IIN_IRQ(14), /* IIN 12-= 14 */ + IDIO_24_IIN_IRQ(15), IDIO_24_IIN_IRQ(16), IDIO_24_IIN_IRQ(17), /* IIN 15-= 17 */ + IDIO_24_IIN_IRQ(18), IDIO_24_IIN_IRQ(19), IDIO_24_IIN_IRQ(20), /* IIN 18-= 20 */ + IDIO_24_IIN_IRQ(21), IDIO_24_IIN_IRQ(22), IDIO_24_IIN_IRQ(23), /* IIN 21-= 23 */ + IDIO_24_TTL_IRQ(0), IDIO_24_TTL_IRQ(1), IDIO_24_TTL_IRQ(2), /* TTL 0-2 */ + IDIO_24_TTL_IRQ(3), IDIO_24_TTL_IRQ(4), IDIO_24_TTL_IRQ(5), /* TTL 3-5 */ + IDIO_24_TTL_IRQ(6), IDIO_24_TTL_IRQ(7), /* TTL 6-7 */ }; =20 /** * struct idio_24_gpio - GPIO device private data structure - * @chip: instance of the gpio_chip + * @map: regmap for the device * @lock: synchronization lock to prevent I/O race conditions - * @reg: I/O address offset for the GPIO device registers - * @irq_mask: I/O bits affected by interrupts + * @irq_type: type configuration for IRQs */ struct idio_24_gpio { - struct gpio_chip chip; + struct regmap *map; raw_spinlock_t lock; - __u8 __iomem *plx; - struct idio_24_gpio_reg __iomem *reg; - unsigned long irq_mask; + u8 irq_type; }; =20 -static int idio_24_gpio_get_direction(struct gpio_chip *chip, - unsigned int offset) -{ - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - const unsigned long out_mode_mask =3D BIT(1); - - /* FET Outputs */ - if (offset < 24) - return GPIO_LINE_DIRECTION_OUT; - - /* Isolated Inputs */ - if (offset < 48) - return GPIO_LINE_DIRECTION_IN; - - /* TTL/CMOS I/O */ - /* OUT MODE =3D 1 when TTL/CMOS Output Mode is set */ - if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int idio_24_gpio_direction_input(struct gpio_chip *chip, - unsigned int offset) -{ - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - unsigned long flags; - unsigned int ctl_state; - const unsigned long out_mode_mask =3D BIT(1); - - /* TTL/CMOS I/O */ - if (offset > 47) { - raw_spin_lock_irqsave(&idio24gpio->lock, flags); - - /* Clear TTL/CMOS Output Mode */ - ctl_state =3D ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask; - iowrite8(ctl_state, &idio24gpio->reg->ctl); - - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); - } - - return 0; -} - -static int idio_24_gpio_direction_output(struct gpio_chip *chip, - unsigned int offset, int value) -{ - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - unsigned long flags; - unsigned int ctl_state; - const unsigned long out_mode_mask =3D BIT(1); - - /* TTL/CMOS I/O */ - if (offset > 47) { - raw_spin_lock_irqsave(&idio24gpio->lock, flags); - - /* Set TTL/CMOS Output Mode */ - ctl_state =3D ioread8(&idio24gpio->reg->ctl) | out_mode_mask; - iowrite8(ctl_state, &idio24gpio->reg->ctl); - - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); - } - - chip->set(chip, offset, value); - return 0; -} - -static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset) +static int idio_24_handle_mask_sync(const int index, const unsigned int ma= sk_buf_def, + const unsigned int mask_buf, void *const irq_drv_data) { - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - const unsigned long offset_mask =3D BIT(offset % 8); - const unsigned long out_mode_mask =3D BIT(1); - - /* FET Outputs */ - if (offset < 8) - return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask); + const unsigned int type_mask =3D COS_ENABLE_BOTH << index; + struct idio_24_gpio *const idio24gpio =3D irq_drv_data; + u8 type; + int ret; =20 - if (offset < 16) - return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask); - - if (offset < 24) - return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask); - - /* Isolated Inputs */ - if (offset < 32) - return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask); - - if (offset < 40) - return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask); - - if (offset < 48) - return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask); + raw_spin_lock(&idio24gpio->lock); =20 - /* TTL/CMOS Outputs */ - if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) - return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask); + /* if all are masked, then disable interrupts, else set to type */ + type =3D (mask_buf =3D=3D mask_buf_def) ? ~type_mask : idio24gpio->irq_ty= pe; =20 - /* TTL/CMOS Inputs */ - return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask); -} + ret =3D regmap_update_bits(idio24gpio->map, IDIO_24_COS_ENABLE, type_mask= , type); =20 -static int idio_24_gpio_get_multiple(struct gpio_chip *chip, - unsigned long *mask, unsigned long *bits) -{ - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - unsigned long offset; - unsigned long gpio_mask; - void __iomem *ports[] =3D { - &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15, - &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7, - &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23, - }; - size_t index; - unsigned long port_state; - const unsigned long out_mode_mask =3D BIT(1); - - /* clear bits array to a clean slate */ - bitmap_zero(bits, chip->ngpio); - - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { - index =3D offset / 8; - - /* read bits from current gpio port (port 6 is TTL GPIO) */ - if (index < 6) - port_state =3D ioread8(ports[index]); - else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) - port_state =3D ioread8(&idio24gpio->reg->ttl_out0_7); - else - port_state =3D ioread8(&idio24gpio->reg->ttl_in0_7); - - port_state &=3D gpio_mask; - - bitmap_set_value8(bits, port_state, offset); - } + raw_spin_unlock(&idio24gpio->lock); =20 - return 0; + return ret; } =20 -static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static int idio_24_set_type_config(unsigned int **const buf, const unsigne= d int type, + const struct regmap_irq *const irq_data, const int idx, + void *const irq_drv_data) { - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - const unsigned long out_mode_mask =3D BIT(1); - void __iomem *base; - const unsigned int mask =3D BIT(offset % 8); - unsigned long flags; - unsigned int out_state; - - /* Isolated Inputs */ - if (offset > 23 && offset < 48) - return; - - /* TTL/CMOS Inputs */ - if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask)) - return; - - /* TTL/CMOS Outputs */ - if (offset > 47) - base =3D &idio24gpio->reg->ttl_out0_7; - /* FET Outputs */ - else if (offset > 15) - base =3D &idio24gpio->reg->out16_23; - else if (offset > 7) - base =3D &idio24gpio->reg->out8_15; - else - base =3D &idio24gpio->reg->out0_7; - - raw_spin_lock_irqsave(&idio24gpio->lock, flags); - - if (value) - out_state =3D ioread8(base) | mask; - else - out_state =3D ioread8(base) & ~mask; - - iowrite8(out_state, base); - - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); -} - -static void idio_24_gpio_set_multiple(struct gpio_chip *chip, - unsigned long *mask, unsigned long *bits) -{ - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - unsigned long offset; - unsigned long gpio_mask; - void __iomem *ports[] =3D { - &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15, - &idio24gpio->reg->out16_23 - }; - size_t index; - unsigned long bitmask; - unsigned long flags; - unsigned long out_state; - const unsigned long out_mode_mask =3D BIT(1); - - for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { - index =3D offset / 8; - - bitmask =3D bitmap_get_value8(bits, offset) & gpio_mask; - - raw_spin_lock_irqsave(&idio24gpio->lock, flags); - - /* read bits from current gpio port (port 6 is TTL GPIO) */ - if (index < 6) { - out_state =3D ioread8(ports[index]); - } else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) { - out_state =3D ioread8(&idio24gpio->reg->ttl_out0_7); - } else { - /* skip TTL GPIO if set for input */ - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); - continue; - } - - /* set requested bit states */ - out_state &=3D ~gpio_mask; - out_state |=3D bitmask; - - /* write bits for current gpio port (port 6 is TTL GPIO) */ - if (index < 6) - iowrite8(out_state, ports[index]); - else - iowrite8(out_state, &idio24gpio->reg->ttl_out0_7); - - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); + const unsigned int offset =3D irq_data->reg_offset; + const unsigned int rising =3D COS_ENABLE_RISING << offset; + const unsigned int falling =3D COS_ENABLE_FALLING << offset; + const unsigned int mask =3D COS_ENABLE_BOTH << offset; + struct idio_24_gpio *const idio24gpio =3D irq_drv_data; + unsigned int new; + unsigned int cos_enable; + int ret; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + new =3D rising; + break; + case IRQ_TYPE_EDGE_FALLING: + new =3D falling; + break; + case IRQ_TYPE_EDGE_BOTH: + new =3D mask; + break; + default: + return -EINVAL; } -} - -static void idio_24_irq_ack(struct irq_data *data) -{ -} =20 -static void idio_24_irq_mask(struct irq_data *data) -{ - struct gpio_chip *const chip =3D irq_data_get_irq_chip_data(data); - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - unsigned long flags; - const unsigned long bit_offset =3D irqd_to_hwirq(data) - 24; - unsigned char new_irq_mask; - const unsigned long bank_offset =3D bit_offset / 8; - unsigned char cos_enable_state; - - raw_spin_lock_irqsave(&idio24gpio->lock, flags); - - idio24gpio->irq_mask &=3D ~BIT(bit_offset); - new_irq_mask =3D idio24gpio->irq_mask >> bank_offset * 8; + raw_spin_lock(&idio24gpio->lock); =20 - if (!new_irq_mask) { - cos_enable_state =3D ioread8(&idio24gpio->reg->cos_enable); + /* replace old bitmap with new bitmap */ + idio24gpio->irq_type =3D (idio24gpio->irq_type & ~mask) | (new & mask); =20 - /* Disable Rising Edge detection */ - cos_enable_state &=3D ~BIT(bank_offset); - /* Disable Falling Edge detection */ - cos_enable_state &=3D ~BIT(bank_offset + 4); + ret =3D regmap_read(idio24gpio->map, IDIO_24_COS_ENABLE, &cos_enable); + if (ret) + goto exit_unlock; =20 - iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable); + /* if COS is currently enabled then update the edge type */ + if (cos_enable & mask) { + ret =3D regmap_update_bits(idio24gpio->map, IDIO_24_COS_ENABLE, mask, + idio24gpio->irq_type); + if (ret) + goto exit_unlock; } =20 - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); +exit_unlock: + raw_spin_unlock(&idio24gpio->lock); =20 - gpiochip_disable_irq(chip, irqd_to_hwirq(data)); + return ret; } =20 -static void idio_24_irq_unmask(struct irq_data *data) +static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, const un= signed int base, + const unsigned int offset, unsigned int *const reg, + unsigned int *const mask) { - struct gpio_chip *const chip =3D irq_data_get_irq_chip_data(data); - struct idio_24_gpio *const idio24gpio =3D gpiochip_get_data(chip); - unsigned long flags; - unsigned char prev_irq_mask; - const unsigned long bit_offset =3D irqd_to_hwirq(data) - 24; - const unsigned long bank_offset =3D bit_offset / 8; - unsigned char cos_enable_state; - - gpiochip_enable_irq(chip, irqd_to_hwirq(data)); - - raw_spin_lock_irqsave(&idio24gpio->lock, flags); + const unsigned int out_stride =3D offset / IDIO_24_NGPIO_PER_REG; + const unsigned int in_stride =3D (offset - 24) / IDIO_24_NGPIO_PER_REG; + struct regmap *const map =3D gpio_regmap_get_drvdata(gpio); + int err; + unsigned int ctrl_reg; =20 - prev_irq_mask =3D idio24gpio->irq_mask >> bank_offset * 8; - idio24gpio->irq_mask |=3D BIT(bit_offset); + switch (base) { + case IDIO_24_OUT_BASE: + *mask =3D BIT(offset % IDIO_24_NGPIO_PER_REG); =20 - if (!prev_irq_mask) { - cos_enable_state =3D ioread8(&idio24gpio->reg->cos_enable); + /* FET Outputs */ + if (offset < 24) { + *reg =3D IDIO_24_OUT_BASE + out_stride; + return 0; + } =20 - /* Enable Rising Edge detection */ - cos_enable_state |=3D BIT(bank_offset); - /* Enable Falling Edge detection */ - cos_enable_state |=3D BIT(bank_offset + 4); + /* Isolated Inputs */ + if (offset < 48) { + *reg =3D IDIO_24_IN_BASE + in_stride; + return 0; + } =20 - iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable); - } + err =3D regmap_read(map, IDIO_24_CONTROL_REG, &ctrl_reg); + if (err) + return err; =20 - raw_spin_unlock_irqrestore(&idio24gpio->lock, flags); -} + /* TTL/CMOS Outputs */ + if (ctrl_reg & CONTROL_REG_OUT_MODE) { + *reg =3D IDIO_24_TTLCMOS_OUT_REG; + return 0; + } =20 -static int idio_24_irq_set_type(struct irq_data *data, unsigned int flow_t= ype) -{ - /* The only valid irq types are none and both-edges */ - if (flow_type !=3D IRQ_TYPE_NONE && - (flow_type & IRQ_TYPE_EDGE_BOTH) !=3D IRQ_TYPE_EDGE_BOTH) + /* TTL/CMOS Inputs */ + *reg =3D IDIO_24_TTLCMOS_IN_REG; + return 0; + case IDIO_24_CONTROL_REG: + /* We can only set direction for TTL/CMOS lines */ + if (offset < 48) + return -EOPNOTSUPP; + + *reg =3D IDIO_24_CONTROL_REG; + *mask =3D CONTROL_REG_OUT_MODE; + return 0; + default: + /* Should never reach this path */ return -EINVAL; - - return 0; -} - -static const struct irq_chip idio_24_irqchip =3D { - .name =3D "pcie-idio-24", - .irq_ack =3D idio_24_irq_ack, - .irq_mask =3D idio_24_irq_mask, - .irq_unmask =3D idio_24_irq_unmask, - .irq_set_type =3D idio_24_irq_set_type, - .flags =3D IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, -}; - -static irqreturn_t idio_24_irq_handler(int irq, void *dev_id) -{ - struct idio_24_gpio *const idio24gpio =3D dev_id; - unsigned long irq_status; - struct gpio_chip *const chip =3D &idio24gpio->chip; - unsigned long irq_mask; - int gpio; - - raw_spin_lock(&idio24gpio->lock); - - /* Read Change-Of-State status */ - irq_status =3D ioread32(&idio24gpio->reg->cos0_7); - - raw_spin_unlock(&idio24gpio->lock); - - /* Make sure our device generated IRQ */ - if (!irq_status) - return IRQ_NONE; - - /* Handle only unmasked IRQ */ - irq_mask =3D idio24gpio->irq_mask & irq_status; - - for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24) - generic_handle_domain_irq(chip->irq.domain, gpio + 24); - - raw_spin_lock(&idio24gpio->lock); - - /* Clear Change-Of-State status */ - iowrite32(irq_status, &idio24gpio->reg->cos0_7); - - raw_spin_unlock(&idio24gpio->lock); - - return IRQ_HANDLED; + } } =20 #define IDIO_24_NGPIO 56 @@ -496,11 +297,12 @@ static int idio_24_probe(struct pci_dev *pdev, const = struct pci_device_id *id) const size_t pci_plx_bar_index =3D 1; const size_t pci_bar_index =3D 2; const char *const name =3D pci_name(pdev); - struct gpio_irq_chip *girq; - - idio24gpio =3D devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL); - if (!idio24gpio) - return -ENOMEM; + struct gpio_regmap_config gpio_config =3D {}; + void __iomem *pex8311_regs; + void __iomem *idio_24_regs; + struct regmap *intcsr_map; + struct regmap_irq_chip *chip; + struct regmap_irq_chip_data *chip_data; =20 err =3D pcim_enable_device(pdev); if (err) { @@ -514,57 +316,72 @@ static int idio_24_probe(struct pci_dev *pdev, const = struct pci_device_id *id) return err; } =20 - idio24gpio->plx =3D pcim_iomap_table(pdev)[pci_plx_bar_index]; - idio24gpio->reg =3D pcim_iomap_table(pdev)[pci_bar_index]; - - idio24gpio->chip.label =3D name; - idio24gpio->chip.parent =3D dev; - idio24gpio->chip.owner =3D THIS_MODULE; - idio24gpio->chip.base =3D -1; - idio24gpio->chip.ngpio =3D IDIO_24_NGPIO; - idio24gpio->chip.names =3D idio_24_names; - idio24gpio->chip.get_direction =3D idio_24_gpio_get_direction; - idio24gpio->chip.direction_input =3D idio_24_gpio_direction_input; - idio24gpio->chip.direction_output =3D idio_24_gpio_direction_output; - idio24gpio->chip.get =3D idio_24_gpio_get; - idio24gpio->chip.get_multiple =3D idio_24_gpio_get_multiple; - idio24gpio->chip.set =3D idio_24_gpio_set; - idio24gpio->chip.set_multiple =3D idio_24_gpio_set_multiple; - - girq =3D &idio24gpio->chip.irq; - gpio_irq_chip_set_chip(girq, &idio_24_irqchip); - /* This will let us handle the parent IRQ in the driver */ - girq->parent_handler =3D NULL; - girq->num_parents =3D 0; - girq->parents =3D NULL; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_edge_irq; + pex8311_regs =3D pcim_iomap_table(pdev)[pci_plx_bar_index]; + idio_24_regs =3D pcim_iomap_table(pdev)[pci_bar_index]; + + intcsr_map =3D devm_regmap_init_mmio(dev, pex8311_regs, &pex8311_intcsr_r= egmap_config); + if (IS_ERR(intcsr_map)) + return dev_err_probe(dev, PTR_ERR(intcsr_map), + "Unable to initialize PEX8311 register map\n"); + + idio24gpio =3D devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL); + if (!idio24gpio) + return -ENOMEM; + + idio24gpio->map =3D devm_regmap_init_mmio(dev, idio_24_regs, &idio_24_reg= map_config); + if (IS_ERR(idio24gpio->map)) + return dev_err_probe(dev, PTR_ERR(idio24gpio->map), + "Unable to initialize register map\n"); =20 raw_spin_lock_init(&idio24gpio->lock); =20 + /* Initialize all IRQ type configuration to IRQ_TYPE_EDGE_BOTH */ + idio24gpio->irq_type =3D GENMASK(7, 0); + + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->name =3D name; + chip->status_base =3D IDIO_24_COS_STATUS_BASE; + chip->mask_base =3D IDIO_24_COS_ENABLE; + chip->ack_base =3D IDIO_24_COS_STATUS_BASE; + chip->num_regs =3D 4; + chip->irqs =3D idio_24_regmap_irqs; + chip->num_irqs =3D ARRAY_SIZE(idio_24_regmap_irqs); + chip->handle_mask_sync =3D idio_24_handle_mask_sync; + chip->set_type_config =3D idio_24_set_type_config; + chip->irq_drv_data =3D idio24gpio; + /* Software board reset */ - iowrite8(0, &idio24gpio->reg->soft_reset); + err =3D regmap_write(idio24gpio->map, IDIO_24_SOFT_RESET, 0); + if (err) + return err; /* * enable PLX PEX8311 internal PCI wire interrupt and local interrupt * input */ - iowrite8((INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT) >> 8, - idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1); - - err =3D devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio); - if (err) { - dev_err(dev, "GPIO registering failed (%d)\n", err); + err =3D regmap_update_bits(intcsr_map, 0x0, IDIO_24_ENABLE_IRQ, IDIO_24_E= NABLE_IRQ); + if (err) return err; - } - - err =3D devm_request_irq(dev, pdev->irq, idio_24_irq_handler, IRQF_SHARED, - name, idio24gpio); - if (err) { - dev_err(dev, "IRQ handler registering failed (%d)\n", err); - return err; - } =20 - return 0; + err =3D devm_regmap_add_irq_chip(dev, idio24gpio->map, pdev->irq, 0, 0, c= hip, &chip_data); + if (err) + return dev_err_probe(dev, err, "IRQ registration failed\n"); + + gpio_config.parent =3D dev; + gpio_config.regmap =3D idio24gpio->map; + gpio_config.ngpio =3D IDIO_24_NGPIO; + gpio_config.names =3D idio_24_names; + gpio_config.reg_dat_base =3D GPIO_REGMAP_ADDR(IDIO_24_OUT_BASE); + gpio_config.reg_set_base =3D GPIO_REGMAP_ADDR(IDIO_24_OUT_BASE); + gpio_config.reg_dir_out_base =3D GPIO_REGMAP_ADDR(IDIO_24_CONTROL_REG); + gpio_config.ngpio_per_reg =3D IDIO_24_NGPIO_PER_REG; + gpio_config.irq_domain =3D regmap_irq_get_domain(chip_data); + gpio_config.reg_mask_xlate =3D idio_24_reg_mask_xlate; + gpio_config.drvdata =3D idio24gpio->map; + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); } =20 static const struct pci_device_id idio_24_pci_dev_id[] =3D { --=20 2.39.2 From nobody Wed Feb 11 06:53:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21387C76188 for ; Wed, 5 Apr 2023 15:46:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239031AbjDEPqO (ORCPT ); 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id g80-20020a0ddd53000000b00545a08184b0sm3942619ywe.64.2023.04.05.08.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 08:45:53 -0700 (PDT) From: William Breathitt Gray To: Linus Walleij , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Shevchenko , Mark Brown , William Breathitt Gray , techsupport@winsystems.com, Paul Demetrotion , Michael Walle Subject: [PATCH v6 3/3] gpio: ws16c48: Migrate to the regmap API Date: Wed, 5 Apr 2023 11:45:44 -0400 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The regmap API supports IO port accessors so we can take advantage of regmap abstractions rather than handling access to the device registers directly in the driver. The WinSystems WS16C48 provides the following registers: Offset 0x0-0x5: Port 0-5 I/O Offset 0x6: Int_Pending Offset 0x7: Page/Lock Offset 0x8-0xA (Page 1): Pol_0-Pol_2 Offset 0x8-0xA (Page 2): Enab_0-Enab_2 Offset 0x8-0xA (Page 3): Int_ID0-Int_ID2 Port 0-5 I/O provides access to 48 lines of digital I/O across six registers, each bit position corresponding to the respective line. Writing a 1 to a respective bit position causes that output pin to sink current, while writing a 0 to the same bit position causes that output pin to go to a high-impedance state and allows it to be used an input. Reads on a port report the inverted state (0 =3D high, 1 =3D low) of an I/O pin when used in input mode. Interrupts are supported on Port 0-2. Int_Pending is a read-only register that reports the combined state of the INT_ID0 through INT_ID2 registers; an interrupt pending is indicated when any of the low three bits are set. The Page/Lock register provides the following bits: Bit 0-5: Port 0-5 I/O Lock Bit 6-7: Page 0-3 Selection For Bits 0-5, writing a 1 to a respective bit position locks the output state of the corresponding I/O port. Writing the page number to Bits 6-7 selects that respective register page for use. Pol_0-Pol_2 are accessible when Page 1 is selected. Writing a 1 to a respective bit position selects the rising edge detection interrupts for that input line, while writing a 0 to the same bit position selects the falling edge detection interrupts. Enab_0-Enab_2 are accessible when Page 2 is selected. Writing a 1 to a respective bit position enables interrupts for that input line, while writing a 0 to that same bit position clears and disables interrupts for that input line. Int_ID0-Int_ID2 are accessible when Page 3 is selected. A respective bit when read as a 1 indicates that an edge of the polarity set in the corresponding polarity register was detected for the corresponding input line. Writing any value to this register clears all pending interrupts for the register. Suggested-by: Andy Shevchenko Reviewed-by: Michael Walle Signed-off-by: William Breathitt Gray Reviewed-by: Andy Shevchenko Reviewed-by: Linus Walleij --- Changes in v6: - Remove regmap_config max_register line as superfluous - Enable use_raw_spinlock to prevent deadlocks when running -rt kernels - Rename exit_early label to the more descriptive exit_unlock - Add sparse annotations for lock acquire/release in ws16c48_handle_pre_irq() and ws16c48_handle_post_irq() - Explicitly add 0 to WS16C48_ENAB in ws16c48_irq_init_hw() for sake of symmetry to match the other WS16C48_ENAB operations=20 Changes in v5: - Refactor for map parameter removal from handle_mask_sync() - Cleanups and lines to 100 characters rather than 80 - Rename PAGE_FIELD_PAGE_* defines to POL_PAGE, ENAB_PAGE, and INT_ID_PAGE - Adjust to change spinlock_t lock to raw_spin_lock Changes in v4: none drivers/gpio/Kconfig | 3 + drivers/gpio/gpio-ws16c48.c | 552 ++++++++++++------------------------ 2 files changed, 188 insertions(+), 367 deletions(-) diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 79359f663b3d..2f6098034753 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -983,7 +983,10 @@ config GPIO_WINBOND config GPIO_WS16C48 tristate "WinSystems WS16C48 GPIO support" select ISA_BUS_API + select REGMAP_IRQ + select REGMAP_MMIO select GPIOLIB_IRQCHIP + select GPIO_REGMAP help Enables GPIO support for the WinSystems WS16C48. The base port addresses for the devices may be configured via the base module diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c index e73885a4dc32..701847508e94 100644 --- a/drivers/gpio/gpio-ws16c48.c +++ b/drivers/gpio/gpio-ws16c48.c @@ -3,19 +3,18 @@ * GPIO driver for the WinSystems WS16C48 * Copyright (C) 2016 William Breathitt Gray */ -#include +#include +#include #include -#include -#include -#include -#include -#include -#include +#include +#include +#include #include #include #include #include #include +#include #include =20 #define WS16C48_EXTENT 10 @@ -31,371 +30,178 @@ static unsigned int num_irq; module_param_hw_array(irq, uint, irq, &num_irq, 0); MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers"); =20 -/** - * struct ws16c48_reg - device register structure - * @port: Port 0 through 5 I/O - * @int_pending: Interrupt Pending - * @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0) - * @pol_enab_int_id: Interrupt polarity, enable, and ID - */ -struct ws16c48_reg { - u8 port[6]; - u8 int_pending; - u8 page_lock; - u8 pol_enab_int_id[3]; +#define WS16C48_DAT_BASE 0x0 +#define WS16C48_PAGE_LOCK 0x7 +#define WS16C48_PAGE_BASE 0x8 +#define WS16C48_POL WS16C48_PAGE_BASE +#define WS16C48_ENAB WS16C48_PAGE_BASE +#define WS16C48_INT_ID WS16C48_PAGE_BASE + +#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6) +#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD) +#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD) +#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD) + +static const struct regmap_range ws16c48_wr_ranges[] =3D { + regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA), +}; +static const struct regmap_range ws16c48_rd_ranges[] =3D { + regmap_reg_range(0x0, 0xA), +}; +static const struct regmap_range ws16c48_volatile_ranges[] =3D { + regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA), +}; +static const struct regmap_access_table ws16c48_wr_table =3D { + .yes_ranges =3D ws16c48_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ws16c48_wr_ranges), +}; +static const struct regmap_access_table ws16c48_rd_table =3D { + .yes_ranges =3D ws16c48_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ws16c48_rd_ranges), +}; +static const struct regmap_access_table ws16c48_volatile_table =3D { + .yes_ranges =3D ws16c48_volatile_ranges, + .n_yes_ranges =3D ARRAY_SIZE(ws16c48_volatile_ranges), +}; +static const struct regmap_config ws16c48_regmap_config =3D { + .reg_bits =3D 8, + .reg_stride =3D 1, + .val_bits =3D 8, + .io_port =3D true, + .wr_table =3D &ws16c48_wr_table, + .rd_table =3D &ws16c48_rd_table, + .volatile_table =3D &ws16c48_volatile_table, + .cache_type =3D REGCACHE_FLAT, + .use_raw_spinlock =3D true, +}; + +#define WS16C48_NGPIO_PER_REG 8 +#define WS16C48_REGMAP_IRQ(_id) \ + [_id] =3D { \ + .reg_offset =3D (_id) / WS16C48_NGPIO_PER_REG, \ + .mask =3D BIT((_id) % WS16C48_NGPIO_PER_REG), \ + .type =3D { \ + .type_reg_offset =3D (_id) / WS16C48_NGPIO_PER_REG, \ + .types_supported =3D IRQ_TYPE_EDGE_BOTH, \ + }, \ + } + +/* Only the first 24 lines (Port 0-2) support interrupts */ +#define WS16C48_NUM_IRQS 24 +static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] =3D { + WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0= -2 */ + WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3= -5 */ + WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6= -8 */ + WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /*= 9-11 */ + WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /= * 12-14 */ + WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /= * 15-17 */ + WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /= * 18-20 */ + WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /= * 21-23 */ }; =20 /** * struct ws16c48_gpio - GPIO device private data structure - * @chip: instance of the gpio_chip - * @io_state: bit I/O state (whether bit is set to input or output) - * @out_state: output bits state + * @map: regmap for the device * @lock: synchronization lock to prevent I/O race conditions * @irq_mask: I/O bits affected by interrupts - * @flow_mask: IRQ flow type mask for the respective I/O bits - * @reg: I/O address offset for the device registers */ struct ws16c48_gpio { - struct gpio_chip chip; - unsigned char io_state[6]; - unsigned char out_state[6]; + struct regmap *map; raw_spinlock_t lock; - unsigned long irq_mask; - unsigned long flow_mask; - struct ws16c48_reg __iomem *reg; + u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG]; }; =20 -static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned off= set) +static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws= 16c48gpio->lock) { - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned port =3D offset / 8; - const unsigned mask =3D BIT(offset % 8); + struct ws16c48_gpio *const ws16c48gpio =3D irq_drv_data; =20 - if (ws16c48gpio->io_state[port] & mask) - return GPIO_LINE_DIRECTION_IN; - - return GPIO_LINE_DIRECTION_OUT; -} - -static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned o= ffset) -{ - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned port =3D offset / 8; - const unsigned mask =3D BIT(offset % 8); - unsigned long flags; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); - - ws16c48gpio->io_state[port] |=3D mask; - ws16c48gpio->out_state[port] &=3D ~mask; - iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + /* Lock to prevent Page/Lock register change while we handle IRQ */ + raw_spin_lock(&ws16c48gpio->lock); =20 return 0; } =20 -static int ws16c48_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) +static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&w= s16c48gpio->lock) { - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned port =3D offset / 8; - const unsigned mask =3D BIT(offset % 8); - unsigned long flags; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); + struct ws16c48_gpio *const ws16c48gpio =3D irq_drv_data; =20 - ws16c48gpio->io_state[port] &=3D ~mask; - if (value) - ws16c48gpio->out_state[port] |=3D mask; - else - ws16c48gpio->out_state[port] &=3D ~mask; - iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock(&ws16c48gpio->lock); =20 return 0; } =20 -static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset) -{ - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned port =3D offset / 8; - const unsigned mask =3D BIT(offset % 8); - unsigned long flags; - unsigned port_state; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); - - /* ensure that GPIO is set for input */ - if (!(ws16c48gpio->io_state[port] & mask)) { - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); - return -EINVAL; - } - - port_state =3D ioread8(ws16c48gpio->reg->port + port); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); - - return !!(port_state & mask); -} - -static int ws16c48_gpio_get_multiple(struct gpio_chip *chip, - unsigned long *mask, unsigned long *bits) -{ - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - unsigned long offset; - unsigned long gpio_mask; - size_t index; - u8 __iomem *port_addr; - unsigned long port_state; - - /* clear bits array to a clean slate */ - bitmap_zero(bits, chip->ngpio); - - for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { - index =3D offset / 8; - port_addr =3D ws16c48gpio->reg->port + index; - port_state =3D ioread8(port_addr) & gpio_mask; - - bitmap_set_value8(bits, port_state, offset); - } - - return 0; -} - -static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int = value) -{ - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned port =3D offset / 8; - const unsigned mask =3D BIT(offset % 8); - unsigned long flags; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); - - /* ensure that GPIO is set for output */ - if (ws16c48gpio->io_state[port] & mask) { - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); - return; - } - - if (value) - ws16c48gpio->out_state[port] |=3D mask; - else - ws16c48gpio->out_state[port] &=3D ~mask; - iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); -} - -static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, - unsigned long *mask, unsigned long *bits) -{ - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - unsigned long offset; - unsigned long gpio_mask; - size_t index; - u8 __iomem *port_addr; - unsigned long bitmask; - unsigned long flags; - - for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { - index =3D offset / 8; - port_addr =3D ws16c48gpio->reg->port + index; - - /* mask out GPIO configured for input */ - gpio_mask &=3D ~ws16c48gpio->io_state[index]; - bitmask =3D bitmap_get_value8(bits, offset) & gpio_mask; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); - - /* update output state data and set device gpio register */ - ws16c48gpio->out_state[index] &=3D ~gpio_mask; - ws16c48gpio->out_state[index] |=3D bitmask; - iowrite8(ws16c48gpio->out_state[index], port_addr); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); - } -} - -static void ws16c48_irq_ack(struct irq_data *data) +static int ws16c48_handle_mask_sync(const int index, const unsigned int ma= sk_buf_def, + const unsigned int mask_buf, void *const irq_drv_data) { - struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned long offset =3D irqd_to_hwirq(data); - const unsigned port =3D offset / 8; - const unsigned mask =3D BIT(offset % 8); + struct ws16c48_gpio *const ws16c48gpio =3D irq_drv_data; unsigned long flags; - unsigned port_state; - - /* only the first 3 ports support interrupts */ - if (port > 2) - return; + int ret =3D 0; =20 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); =20 - port_state =3D ws16c48gpio->irq_mask >> (8*port); + /* exit early if no change since the last mask sync */ + if (mask_buf =3D=3D ws16c48gpio->irq_mask[index]) + goto exit_unlock; + ws16c48gpio->irq_mask[index] =3D mask_buf; =20 - /* Select Register Page 2; Unlock all I/O ports */ - iowrite8(0x80, &ws16c48gpio->reg->page_lock); + ret =3D regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE); + if (ret) + goto exit_unlock; =20 - /* Clear pending interrupt */ - iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port); - iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port); + /* Update ENAB register (inverted mask) */ + ret =3D regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf); + if (ret) + goto exit_unlock; =20 - /* Select Register Page 3; Unlock all I/O ports */ - iowrite8(0xC0, &ws16c48gpio->reg->page_lock); + ret =3D regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE); + if (ret) + goto exit_unlock; =20 +exit_unlock: raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); -} - -static void ws16c48_irq_mask(struct irq_data *data) -{ - struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned long offset =3D irqd_to_hwirq(data); - const unsigned long mask =3D BIT(offset); - const unsigned port =3D offset / 8; - unsigned long flags; - unsigned long port_state; - - /* only the first 3 ports support interrupts */ - if (port > 2) - return; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); =20 - ws16c48gpio->irq_mask &=3D ~mask; - gpiochip_disable_irq(chip, offset); - port_state =3D ws16c48gpio->irq_mask >> (8 * port); - - /* Select Register Page 2; Unlock all I/O ports */ - iowrite8(0x80, &ws16c48gpio->reg->page_lock); - - /* Disable interrupt */ - iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); - - /* Select Register Page 3; Unlock all I/O ports */ - iowrite8(0xC0, &ws16c48gpio->reg->page_lock); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + return ret; } =20 -static void ws16c48_irq_unmask(struct irq_data *data) +static int ws16c48_set_type_config(unsigned int **const buf, const unsigne= d int type, + const struct regmap_irq *const irq_data, const int idx, + void *const irq_drv_data) { - struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned long offset =3D irqd_to_hwirq(data); - const unsigned long mask =3D BIT(offset); - const unsigned port =3D offset / 8; + struct ws16c48_gpio *const ws16c48gpio =3D irq_drv_data; + unsigned int polarity; unsigned long flags; - unsigned long port_state; - - /* only the first 3 ports support interrupts */ - if (port > 2) - return; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); - - gpiochip_enable_irq(chip, offset); - ws16c48gpio->irq_mask |=3D mask; - port_state =3D ws16c48gpio->irq_mask >> (8 * port); - - /* Select Register Page 2; Unlock all I/O ports */ - iowrite8(0x80, &ws16c48gpio->reg->page_lock); - - /* Enable interrupt */ - iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); - - /* Select Register Page 3; Unlock all I/O ports */ - iowrite8(0xC0, &ws16c48gpio->reg->page_lock); - - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); -} + int ret; =20 -static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) -{ - struct gpio_chip *chip =3D irq_data_get_irq_chip_data(data); - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); - const unsigned long offset =3D irqd_to_hwirq(data); - const unsigned long mask =3D BIT(offset); - const unsigned port =3D offset / 8; - unsigned long flags; - unsigned long port_state; - - /* only the first 3 ports support interrupts */ - if (port > 2) - return -EINVAL; - - raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); - - switch (flow_type) { - case IRQ_TYPE_NONE: - break; + switch (type) { case IRQ_TYPE_EDGE_RISING: - ws16c48gpio->flow_mask |=3D mask; + polarity =3D irq_data->mask; break; case IRQ_TYPE_EDGE_FALLING: - ws16c48gpio->flow_mask &=3D ~mask; + polarity =3D 0; break; default: - raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return -EINVAL; } =20 - port_state =3D ws16c48gpio->flow_mask >> (8 * port); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); =20 - /* Select Register Page 1; Unlock all I/O ports */ - iowrite8(0x40, &ws16c48gpio->reg->page_lock); + ret =3D regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE); + if (ret) + goto exit_unlock; =20 /* Set interrupt polarity */ - iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port); + ret =3D regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data-= >mask, polarity); + if (ret) + goto exit_unlock; =20 - /* Select Register Page 3; Unlock all I/O ports */ - iowrite8(0xC0, &ws16c48gpio->reg->page_lock); + ret =3D regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE); + if (ret) + goto exit_unlock; =20 +exit_unlock: raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); =20 - return 0; -} - -static const struct irq_chip ws16c48_irqchip =3D { - .name =3D "ws16c48", - .irq_ack =3D ws16c48_irq_ack, - .irq_mask =3D ws16c48_irq_mask, - .irq_unmask =3D ws16c48_irq_unmask, - .irq_set_type =3D ws16c48_irq_set_type, - .flags =3D IRQCHIP_IMMUTABLE, - GPIOCHIP_IRQ_RESOURCE_HELPERS, -}; - -static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id) -{ - struct ws16c48_gpio *const ws16c48gpio =3D dev_id; - struct gpio_chip *const chip =3D &ws16c48gpio->chip; - struct ws16c48_reg __iomem *const reg =3D ws16c48gpio->reg; - unsigned long int_pending; - unsigned long port; - unsigned long int_id; - unsigned long gpio; - - int_pending =3D ioread8(®->int_pending) & 0x7; - if (!int_pending) - return IRQ_NONE; - - /* loop until all pending interrupts are handled */ - do { - for_each_set_bit(port, &int_pending, 3) { - int_id =3D ioread8(reg->pol_enab_int_id + port); - for_each_set_bit(gpio, &int_id, 8) - generic_handle_domain_irq(chip->irq.domain, - gpio + 8*port); - } - - int_pending =3D ioread8(®->int_pending) & 0x7; - } while (int_pending); - - return IRQ_HANDLED; + return ret; } =20 #define WS16C48_NGPIO 48 @@ -414,30 +220,37 @@ static const char *ws16c48_names[WS16C48_NGPIO] =3D { "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7" }; =20 -static int ws16c48_irq_init_hw(struct gpio_chip *gc) +static int ws16c48_irq_init_hw(struct regmap *const map) { - struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(gc); + int err; =20 - /* Select Register Page 2; Unlock all I/O ports */ - iowrite8(0x80, &ws16c48gpio->reg->page_lock); + err =3D regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE); + if (err) + return err; =20 /* Disable interrupts for all lines */ - iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]); - iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]); - iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]); - - /* Select Register Page 3; Unlock all I/O ports */ - iowrite8(0xC0, &ws16c48gpio->reg->page_lock); + err =3D regmap_write(map, WS16C48_ENAB + 0, 0x00); + if (err) + return err; + err =3D regmap_write(map, WS16C48_ENAB + 1, 0x00); + if (err) + return err; + err =3D regmap_write(map, WS16C48_ENAB + 2, 0x00); + if (err) + return err; =20 - return 0; + return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE); } =20 static int ws16c48_probe(struct device *dev, unsigned int id) { struct ws16c48_gpio *ws16c48gpio; const char *const name =3D dev_name(dev); - struct gpio_irq_chip *girq; int err; + struct gpio_regmap_config gpio_config =3D {}; + void __iomem *regs; + struct regmap_irq_chip *chip; + struct regmap_irq_chip_data *chip_data; =20 ws16c48gpio =3D devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL); if (!ws16c48gpio) @@ -449,50 +262,55 @@ static int ws16c48_probe(struct device *dev, unsigned= int id) return -EBUSY; } =20 - ws16c48gpio->reg =3D devm_ioport_map(dev, base[id], WS16C48_EXTENT); - if (!ws16c48gpio->reg) + regs =3D devm_ioport_map(dev, base[id], WS16C48_EXTENT); + if (!regs) return -ENOMEM; =20 - ws16c48gpio->chip.label =3D name; - ws16c48gpio->chip.parent =3D dev; - ws16c48gpio->chip.owner =3D THIS_MODULE; - ws16c48gpio->chip.base =3D -1; - ws16c48gpio->chip.ngpio =3D WS16C48_NGPIO; - ws16c48gpio->chip.names =3D ws16c48_names; - ws16c48gpio->chip.get_direction =3D ws16c48_gpio_get_direction; - ws16c48gpio->chip.direction_input =3D ws16c48_gpio_direction_input; - ws16c48gpio->chip.direction_output =3D ws16c48_gpio_direction_output; - ws16c48gpio->chip.get =3D ws16c48_gpio_get; - ws16c48gpio->chip.get_multiple =3D ws16c48_gpio_get_multiple; - ws16c48gpio->chip.set =3D ws16c48_gpio_set; - ws16c48gpio->chip.set_multiple =3D ws16c48_gpio_set_multiple; - - girq =3D &ws16c48gpio->chip.irq; - gpio_irq_chip_set_chip(girq, &ws16c48_irqchip); - /* This will let us handle the parent IRQ in the driver */ - girq->parent_handler =3D NULL; - girq->num_parents =3D 0; - girq->parents =3D NULL; - girq->default_type =3D IRQ_TYPE_NONE; - girq->handler =3D handle_edge_irq; - girq->init_hw =3D ws16c48_irq_init_hw; + ws16c48gpio->map =3D devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_con= fig); + if (IS_ERR(ws16c48gpio->map)) + return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map), + "Unable to initialize register map\n"); =20 - raw_spin_lock_init(&ws16c48gpio->lock); + chip =3D devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; =20 - err =3D devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio); - if (err) { - dev_err(dev, "GPIO registering failed (%d)\n", err); - return err; - } + chip->name =3D name; + chip->status_base =3D WS16C48_INT_ID; + chip->mask_base =3D WS16C48_ENAB; + chip->ack_base =3D WS16C48_INT_ID; + chip->num_regs =3D 3; + chip->irqs =3D ws16c48_regmap_irqs; + chip->num_irqs =3D ARRAY_SIZE(ws16c48_regmap_irqs); + chip->handle_pre_irq =3D ws16c48_handle_pre_irq; + chip->handle_post_irq =3D ws16c48_handle_post_irq; + chip->handle_mask_sync =3D ws16c48_handle_mask_sync; + chip->set_type_config =3D ws16c48_set_type_config; + chip->irq_drv_data =3D ws16c48gpio; =20 - err =3D devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED, - name, ws16c48gpio); - if (err) { - dev_err(dev, "IRQ handler registering failed (%d)\n", err); + raw_spin_lock_init(&ws16c48gpio->lock); + + /* Initialize to prevent spurious interrupts before we're ready */ + err =3D ws16c48_irq_init_hw(ws16c48gpio->map); + if (err) return err; - } =20 - return 0; + err =3D devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, ch= ip, &chip_data); + if (err) + return dev_err_probe(dev, err, "IRQ registration failed\n"); + + gpio_config.parent =3D dev; + gpio_config.regmap =3D ws16c48gpio->map; + gpio_config.ngpio =3D WS16C48_NGPIO; + gpio_config.names =3D ws16c48_names; + gpio_config.reg_dat_base =3D GPIO_REGMAP_ADDR(WS16C48_DAT_BASE); + gpio_config.reg_set_base =3D GPIO_REGMAP_ADDR(WS16C48_DAT_BASE); + /* Setting a GPIO to 0 allows it to be used as an input */ + gpio_config.reg_dir_out_base =3D GPIO_REGMAP_ADDR(WS16C48_DAT_BASE); + gpio_config.ngpio_per_reg =3D WS16C48_NGPIO_PER_REG; + gpio_config.irq_domain =3D regmap_irq_get_domain(chip_data); + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); } =20 static struct isa_driver ws16c48_driver =3D { --=20 2.39.2