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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id f67-20020a37d246000000b00745daadd210sm3709162qkj.71.2023.03.18.08.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Mar 2023 08:00:03 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: Johannes Berg , Jonathan Cameron , Andy Shevchenko , Andrew Morton , linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH 1/4] counter: 104-quad-8: Utilize bitfield access macros Date: Sat, 18 Mar 2023 10:59:48 -0400 Message-Id: <15356da19de83d92b532515ee12b5caa32b35711.1679149542.git.william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 104-QUAD-8 features several registers with various bitfields. Utilize bitfield access macros such as FIELD_PREP to make the code easier to read and the intent clearer. Suggested-by: Jonathan Cameron Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 267 +++++++++++++++++++++++------------ 1 file changed, 176 insertions(+), 91 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index d9cb937665cf..be7b04b52d85 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -5,7 +5,8 @@ * * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4. */ -#include +#include +#include #include #include #include @@ -98,36 +99,110 @@ struct quad8 { }; =20 /* Error flag */ -#define QUAD8_FLAG_E BIT(4) +#define FLAG_E BIT(4) /* Up/Down flag */ -#define QUAD8_FLAG_UD BIT(5) +#define FLAG_UD BIT(5) + +#define REGISTER_SELECTION GENMASK(6, 5) + /* Reset and Load Signal Decoders */ -#define QUAD8_CTR_RLD 0x00 +#define SELECT_RLD FIELD_PREP(REGISTER_SELECTION, 0x0) /* Counter Mode Register */ -#define QUAD8_CTR_CMR 0x20 +#define SELECT_CMR FIELD_PREP(REGISTER_SELECTION, 0x1) /* Input / Output Control Register */ -#define QUAD8_CTR_IOR 0x40 +#define SELECT_IOR FIELD_PREP(REGISTER_SELECTION, 0x2) /* Index Control Register */ -#define QUAD8_CTR_IDR 0x60 +#define SELECT_IDR FIELD_PREP(REGISTER_SELECTION, 0x3) + +/* + * Reset and Load Signal Decoders + */ +#define RESETS GENMASK(2, 1) +#define LOADS GENMASK(4, 3) /* Reset Byte Pointer (three byte data pointer) */ -#define QUAD8_RLD_RESET_BP 0x01 -/* Reset Counter */ -#define QUAD8_RLD_RESET_CNTR 0x02 -/* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */ -#define QUAD8_RLD_RESET_FLAGS 0x04 +#define RESET_BP BIT(0) +/* Reset Borrow Toggle, Carry toggle, Compare toggle, Sign, and Index flag= s */ +#define RESET_BT_CT_CPT_S_IDX FIELD_PREP(RESETS, 0x2) /* Reset Error flag */ -#define QUAD8_RLD_RESET_E 0x06 +#define RESET_E FIELD_PREP(RESETS, 0x3) /* Preset Register to Counter */ -#define QUAD8_RLD_PRESET_CNTR 0x08 +#define TRANSFER_PR_TO_CNTR FIELD_PREP(LOADS, 0x1) /* Transfer Counter to Output Latch */ -#define QUAD8_RLD_CNTR_OUT 0x10 +#define TRANSFER_CNTR_TO_OL FIELD_PREP(LOADS, 0x2) /* Transfer Preset Register LSB to FCK Prescaler */ -#define QUAD8_RLD_PRESET_PSC 0x18 -#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01 -#define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04 -#define QUAD8_CMR_QUADRATURE_X1 0x08 -#define QUAD8_CMR_QUADRATURE_X2 0x10 -#define QUAD8_CMR_QUADRATURE_X4 0x18 +#define TRANSFER_PR0_TO_PSC FIELD_PREP(LOADS, 0x3) + +/* + * Counter Mode Registers + */ +#define COUNT_ENCODING BIT(0) +#define COUNT_MODE GENMASK(2, 1) +#define QUADRATURE_MODE GENMASK(4, 3) +/* Binary count */ +#define BINARY FIELD_PREP(COUNT_ENCODING, 0x0) +/* Normal count */ +#define NORMAL_COUNT 0x0 +#define CMR_NORMAL_COUNT FIELD_PREP(COUNT_MODE, NORMAL_COUNT) +/* Range Limit */ +#define RANGE_LIMIT 0x1 +/* Non-recycle count */ +#define NON_RECYCLE_COUNT 0x2 +/* Modulo-N */ +#define MODULO_N 0x3 +/* Non-quadrature */ +#define NON_QUADRATURE FIELD_PREP(QUADRATURE_MODE, 0x0) +/* Quadrature X1 */ +#define QUADRATURE_X1 FIELD_PREP(QUADRATURE_MODE, 0x1) +/* Quadrature X2 */ +#define QUADRATURE_X2 FIELD_PREP(QUADRATURE_MODE, 0x2) +/* Quadrature X4 */ +#define QUADRATURE_X4 FIELD_PREP(QUADRATURE_MODE, 0x3) + +/* + * Input/Output Control Register + */ +#define AB_GATE BIT(0) +#define LOAD_PIN BIT(1) +#define FLG_PINS GENMASK(4, 3) +/* Disable inputs A and B */ +#define DISABLE_AB FIELD_PREP(AB_GATE, 0x0) +/* Load Counter input */ +#define LOAD_CNTR FIELD_PREP(LOAD_PIN, 0x0) +/* FLG1 =3D CARRY(active low); FLG2 =3D BORROW(active low) */ +#define FLG1_CARRY_FLG2_BORROW 0x0 +#define IOR_FLG1_CARRY_FLG2_BORROW FIELD_PREP(FLG_PINS, FLG1_CARRY_FLG2_BO= RROW) +/* FLG1 =3D COMPARE(active low); FLG2 =3D BORROW(active low) */ +#define FLG1_COMPARE_FLG2_BORROW 0x1 +/* FLG1 =3D Carry(active low)/Borrow(active low); FLG2 =3D U/D(active low)= flag */ +#define FLG1_CARRYBORROW_FLG2_UD 0x2 +/* FLG1 =3D INDX (low pulse at INDEX pin active level); FLG2 =3D E flag */ +#define FLG1_INDX_FLG2_E 0x3 + +/* + * INDEX CONTROL REGISTERS + */ +#define INDEX_MODE BIT(0) +#define INDEX_POLARITY BIT(1) +/* Disable Index mode */ +#define DISABLE_INDEX_MODE FIELD_PREP(INDEX_MODE, 0x0) +/* Negative Index Polarity */ +#define NEGATIVE_INDEX_POLARITY FIELD_PREP(INDEX_POLARITY, 0x0) + +/* + * Channel Operation Register + */ +#define COUNTERS_OPERATION BIT(0) +#define INTERRUPT_FUNCTION BIT(2) +/* Enable all Counters */ +#define ENABLE_COUNTERS FIELD_PREP(COUNTERS_OPERATION, 0x0) +/* Reset all Counters */ +#define RESET_COUNTERS FIELD_PREP(COUNTERS_OPERATION, 0x1) +/* Disable the interrupt function */ +#define DISABLE_INTERRUPT_FUNCTION FIELD_PREP(INTERRUPT_FUNCTION, 0x0) +/* Enable the interrupt function */ +#define ENABLE_INTERRUPT_FUNCTION FIELD_PREP(INTERRUPT_FUNCTION, 0x1) +/* Any write to the Channel Operation register clears any pending interrup= ts */ +#define CLEAR_PENDING_INTERRUPTS (ENABLE_COUNTERS | ENABLE_INTERRUPT_FUNCT= ION) =20 /* Each Counter is 24 bits wide */ #define LS7267_CNTR_MAX GENMASK(23, 0) @@ -163,8 +238,7 @@ static int quad8_count_read(struct counter_device *coun= ter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Reset Byte Pointer; transfer Counter to Output Latch */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, - &chan->control); + iowrite8(SELECT_RLD | RESET_BP | TRANSFER_CNTR_TO_OL, &chan->control); =20 for (i =3D 0; i < 3; i++) *val |=3D (unsigned long)ioread8(&chan->data) << (8 * i); @@ -188,17 +262,17 @@ static int quad8_count_write(struct counter_device *c= ounter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Reset Byte Pointer */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + iowrite8(SELECT_RLD | RESET_BP, &chan->control); =20 /* Counter can only be set via Preset Register */ for (i =3D 0; i < 3; i++) iowrite8(val >> (8 * i), &chan->data); =20 /* Transfer Preset Register to Counter */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control); + iowrite8(SELECT_RLD | TRANSFER_PR_TO_CNTR, &chan->control); =20 /* Reset Byte Pointer */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + iowrite8(SELECT_RLD | RESET_BP, &chan->control); =20 /* Set Preset Register back to original value */ val =3D priv->preset[count->id]; @@ -206,9 +280,9 @@ static int quad8_count_write(struct counter_device *cou= nter, iowrite8(val >> (8 * i), &chan->data); =20 /* Reset Borrow, Carry, Compare, and Sign flags */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); + iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control); /* Reset Error flag */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); + iowrite8(SELECT_RLD | RESET_E, &chan->control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -279,8 +353,8 @@ static int quad8_function_write(struct counter_device *= counter, =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - mode_cfg =3D priv->count_mode[id] << 1; - idr_cfg =3D priv->index_polarity[id] << 1; + mode_cfg =3D FIELD_PREP(COUNT_MODE, priv->count_mode[id]); + idr_cfg =3D FIELD_PREP(INDEX_POLARITY, priv->index_polarity[id]); =20 if (function =3D=3D COUNTER_FUNCTION_PULSE_DIRECTION) { *quadrature_mode =3D 0; @@ -288,11 +362,14 @@ static int quad8_function_write(struct counter_device= *counter, /* Quadrature scaling only available in quadrature mode */ *scale =3D 0; =20 + mode_cfg |=3D NON_QUADRATURE; + /* Synchronous function not supported in non-quadrature mode */ if (*synchronous_mode) { - *synchronous_mode =3D 0; /* Disable synchronous function mode */ - iowrite8(QUAD8_CTR_IDR | idr_cfg, control); + *synchronous_mode =3D 0; + idr_cfg |=3D FIELD_PREP(INDEX_MODE, *synchronous_mode); + iowrite8(SELECT_IDR | idr_cfg, control); } } else { *quadrature_mode =3D 1; @@ -300,15 +377,15 @@ static int quad8_function_write(struct counter_device= *counter, switch (function) { case COUNTER_FUNCTION_QUADRATURE_X1_A: *scale =3D 0; - mode_cfg |=3D QUAD8_CMR_QUADRATURE_X1; + mode_cfg |=3D QUADRATURE_X1; break; case COUNTER_FUNCTION_QUADRATURE_X2_A: *scale =3D 1; - mode_cfg |=3D QUAD8_CMR_QUADRATURE_X2; + mode_cfg |=3D QUADRATURE_X2; break; case COUNTER_FUNCTION_QUADRATURE_X4: *scale =3D 2; - mode_cfg |=3D QUAD8_CMR_QUADRATURE_X4; + mode_cfg |=3D QUADRATURE_X4; break; default: /* should never reach this path */ @@ -318,7 +395,7 @@ static int quad8_function_write(struct counter_device *= counter, } =20 /* Load mode configuration to Counter Mode Register */ - iowrite8(QUAD8_CTR_CMR | mode_cfg, control); + iowrite8(SELECT_CMR | mode_cfg, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -332,9 +409,11 @@ static int quad8_direction_read(struct counter_device = *counter, const struct quad8 *const priv =3D counter_priv(counter); unsigned int ud_flag; u8 __iomem *const flag_addr =3D &priv->reg->channel[count->id].control; + unsigned long flag; =20 + flag =3D ioread8(flag_addr); /* U/D flag: nonzero =3D up, zero =3D down */ - ud_flag =3D ioread8(flag_addr) & QUAD8_FLAG_UD; + ud_flag =3D FIELD_GET(FLAG_UD, flag); =20 *direction =3D (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD; @@ -423,10 +502,10 @@ static int quad8_action_read(struct counter_device *c= ounter, } =20 enum { - QUAD8_EVENT_CARRY =3D 0, - QUAD8_EVENT_COMPARE =3D 1, - QUAD8_EVENT_CARRY_BORROW =3D 2, - QUAD8_EVENT_INDEX =3D 3, + QUAD8_EVENT_CARRY =3D FLG1_CARRY_FLG2_BORROW, + QUAD8_EVENT_COMPARE =3D FLG1_COMPARE_FLG2_BORROW, + QUAD8_EVENT_CARRY_BORROW =3D FLG1_CARRYBORROW_FLG2_UD, + QUAD8_EVENT_INDEX =3D FLG1_INDX_FLG2_E, }; =20 static int quad8_events_configure(struct counter_device *counter) @@ -471,10 +550,13 @@ static int quad8_events_configure(struct counter_devi= ce *counter) priv->irq_trigger[event_node->channel] =3D next_irq_trigger; =20 /* Load configuration to I/O Control Register */ - ior_cfg =3D priv->ab_enable[event_node->channel] | - priv->preset_enable[event_node->channel] << 1 | - priv->irq_trigger[event_node->channel] << 3; - iowrite8(QUAD8_CTR_IOR | ior_cfg, + ior_cfg =3D FIELD_PREP(AB_GATE, + priv->ab_enable[event_node->channel]) | + FIELD_PREP(LOAD_PIN, + priv->preset_enable[event_node->channel]) | + FIELD_PREP(FLG_PINS, + priv->irq_trigger[event_node->channel]); + iowrite8(SELECT_IOR | ior_cfg, &priv->reg->channel[event_node->channel].control); } =20 @@ -544,16 +626,16 @@ static int quad8_index_polarity_set(struct counter_de= vice *counter, const size_t channel_id =3D signal->id - 16; u8 __iomem *const control =3D &priv->reg->channel[channel_id].control; unsigned long irqflags; - unsigned int idr_cfg =3D index_polarity << 1; + unsigned int idr_cfg =3D FIELD_PREP(INDEX_POLARITY, index_polarity); =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - idr_cfg |=3D priv->synchronous_mode[channel_id]; + idr_cfg |=3D FIELD_PREP(INDEX_MODE, priv->synchronous_mode[channel_id]); =20 priv->index_polarity[channel_id] =3D index_polarity; =20 /* Load Index Control configuration to Index Control Register */ - iowrite8(QUAD8_CTR_IDR | idr_cfg, control); + iowrite8(SELECT_IDR | idr_cfg, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -611,11 +693,11 @@ static int quad8_synchronous_mode_set(struct counter_= device *counter, const size_t channel_id =3D signal->id - 16; u8 __iomem *const control =3D &priv->reg->channel[channel_id].control; unsigned long irqflags; - unsigned int idr_cfg =3D synchronous_mode; + unsigned int idr_cfg =3D FIELD_PREP(INDEX_MODE, synchronous_mode); =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - idr_cfg |=3D priv->index_polarity[channel_id] << 1; + idr_cfg |=3D FIELD_PREP(INDEX_POLARITY, priv->index_polarity[channel_id]); =20 /* Index function must be non-synchronous in non-quadrature mode */ if (synchronous_mode && !priv->quadrature_mode[channel_id]) { @@ -626,7 +708,7 @@ static int quad8_synchronous_mode_set(struct counter_de= vice *counter, priv->synchronous_mode[channel_id] =3D synchronous_mode; =20 /* Load Index Control configuration to Index Control Register */ - iowrite8(QUAD8_CTR_IDR | idr_cfg, control); + iowrite8(SELECT_IDR | idr_cfg, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -648,18 +730,17 @@ static int quad8_count_mode_read(struct counter_devic= e *counter, { const struct quad8 *const priv =3D counter_priv(counter); =20 - /* Map 104-QUAD-8 count mode to Generic Counter count mode */ switch (priv->count_mode[count->id]) { - case 0: + case NORMAL_COUNT: *cnt_mode =3D COUNTER_COUNT_MODE_NORMAL; break; - case 1: + case RANGE_LIMIT: *cnt_mode =3D COUNTER_COUNT_MODE_RANGE_LIMIT; break; - case 2: + case NON_RECYCLE_COUNT: *cnt_mode =3D COUNTER_COUNT_MODE_NON_RECYCLE; break; - case 3: + case MODULO_N: *cnt_mode =3D COUNTER_COUNT_MODE_MODULO_N; break; } @@ -677,19 +758,18 @@ static int quad8_count_mode_write(struct counter_devi= ce *counter, u8 __iomem *const control =3D &priv->reg->channel[count->id].control; unsigned long irqflags; =20 - /* Map Generic Counter count mode to 104-QUAD-8 count mode */ switch (cnt_mode) { case COUNTER_COUNT_MODE_NORMAL: - count_mode =3D 0; + count_mode =3D NORMAL_COUNT; break; case COUNTER_COUNT_MODE_RANGE_LIMIT: - count_mode =3D 1; + count_mode =3D RANGE_LIMIT; break; case COUNTER_COUNT_MODE_NON_RECYCLE: - count_mode =3D 2; + count_mode =3D NON_RECYCLE_COUNT; break; case COUNTER_COUNT_MODE_MODULO_N: - count_mode =3D 3; + count_mode =3D MODULO_N; break; default: /* should never reach this path */ @@ -701,14 +781,17 @@ static int quad8_count_mode_write(struct counter_devi= ce *counter, priv->count_mode[count->id] =3D count_mode; =20 /* Set count mode configuration value */ - mode_cfg =3D count_mode << 1; + mode_cfg =3D FIELD_PREP(COUNT_MODE, count_mode); =20 /* Add quadrature mode configuration */ if (priv->quadrature_mode[count->id]) - mode_cfg |=3D (priv->quadrature_scale[count->id] + 1) << 3; + mode_cfg |=3D FIELD_PREP(QUADRATURE_MODE, + priv->quadrature_scale[count->id] + 1); + else + mode_cfg |=3D NON_QUADRATURE; =20 /* Load mode configuration to Counter Mode Register */ - iowrite8(QUAD8_CTR_CMR | mode_cfg, control); + iowrite8(SELECT_CMR | mode_cfg, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -737,11 +820,12 @@ static int quad8_count_enable_write(struct counter_de= vice *counter, =20 priv->ab_enable[count->id] =3D enable; =20 - ior_cfg =3D enable | priv->preset_enable[count->id] << 1 | - priv->irq_trigger[count->id] << 3; + ior_cfg =3D FIELD_PREP(AB_GATE, enable) | + FIELD_PREP(LOAD_PIN, priv->preset_enable[count->id]) | + FIELD_PREP(FLG_PINS, priv->irq_trigger[count->id]); =20 /* Load I/O control configuration */ - iowrite8(QUAD8_CTR_IOR | ior_cfg, control); + iowrite8(SELECT_IOR | ior_cfg, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -758,8 +842,10 @@ static int quad8_error_noise_get(struct counter_device= *counter, { const struct quad8 *const priv =3D counter_priv(counter); u8 __iomem *const flag_addr =3D &priv->reg->channel[count->id].control; + unsigned long flag; =20 - *noise_error =3D !!(ioread8(flag_addr) & QUAD8_FLAG_E); + flag =3D ioread8(flag_addr); + *noise_error =3D FIELD_GET(FLAG_E, flag); =20 return 0; } @@ -783,7 +869,7 @@ static void quad8_preset_register_set(struct quad8 *con= st priv, const int id, priv->preset[id] =3D preset; =20 /* Reset Byte Pointer */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + iowrite8(SELECT_RLD | RESET_BP, &chan->control); =20 /* Set Preset Register */ for (i =3D 0; i < 3; i++) @@ -818,8 +904,8 @@ static int quad8_count_ceiling_read(struct counter_devi= ce *counter, =20 /* Range Limit and Modulo-N count modes use preset value as ceiling */ switch (priv->count_mode[count->id]) { - case 1: - case 3: + case RANGE_LIMIT: + case MODULO_N: *ceiling =3D priv->preset[count->id]; break; default: @@ -845,8 +931,8 @@ static int quad8_count_ceiling_write(struct counter_dev= ice *counter, =20 /* Range Limit and Modulo-N count modes use preset value as ceiling */ switch (priv->count_mode[count->id]) { - case 1: - case 3: + case RANGE_LIMIT: + case MODULO_N: quad8_preset_register_set(priv, count->id, ceiling); spin_unlock_irqrestore(&priv->lock, irqflags); return 0; @@ -884,11 +970,12 @@ static int quad8_count_preset_enable_write(struct cou= nter_device *counter, =20 priv->preset_enable[count->id] =3D preset_enable; =20 - ior_cfg =3D priv->ab_enable[count->id] | preset_enable << 1 | - priv->irq_trigger[count->id] << 3; + ior_cfg =3D FIELD_PREP(AB_GATE, priv->ab_enable[count->id]) | + FIELD_PREP(LOAD_PIN, preset_enable) | + FIELD_PREP(FLG_PINS, priv->irq_trigger[count->id]); =20 /* Load I/O control configuration to Input / Output Control Register */ - iowrite8(QUAD8_CTR_IOR | ior_cfg, control); + iowrite8(SELECT_IOR | ior_cfg, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -988,12 +1075,11 @@ static int quad8_signal_fck_prescaler_write(struct c= ounter_device *counter, priv->fck_prescaler[channel_id] =3D prescaler; =20 /* Reset Byte Pointer */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + iowrite8(SELECT_RLD | RESET_BP, &chan->control); =20 /* Set filter clock factor */ iowrite8(prescaler, &chan->data); - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - &chan->control); + iowrite8(SELECT_RLD | RESET_BP | TRANSFER_PR0_TO_PSC, &chan->control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -1183,7 +1269,7 @@ static irqreturn_t quad8_irq_handler(int irq, void *p= rivate) } =20 /* Clear pending interrupts on device */ - iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); + iowrite8(CLEAR_PENDING_INTERRUPTS, &priv->reg->channel_oper); =20 return IRQ_HANDLED; } @@ -1193,26 +1279,25 @@ static void quad8_init_counter(struct channel_reg _= _iomem *const chan) unsigned long i; =20 /* Reset Byte Pointer */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + iowrite8(SELECT_RLD | RESET_BP, &chan->control); /* Reset filter clock factor */ iowrite8(0, &chan->data); - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - &chan->control); + iowrite8(SELECT_RLD | RESET_BP | TRANSFER_PR0_TO_PSC, &chan->control); /* Reset Byte Pointer */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control); + iowrite8(SELECT_RLD | RESET_BP, &chan->control); /* Reset Preset Register */ for (i =3D 0; i < 3; i++) iowrite8(0x00, &chan->data); /* Reset Borrow, Carry, Compare, and Sign flags */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); + iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control); /* Reset Error flag */ - iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control); + iowrite8(SELECT_RLD | RESET_E, &chan->control); /* Binary encoding; Normal count; non-quadrature mode */ - iowrite8(QUAD8_CTR_CMR, &chan->control); + iowrite8(SELECT_CMR | BINARY | CMR_NORMAL_COUNT | NON_QUADRATURE, &chan->= control); /* Disable A and B inputs; preset on index; FLG1 as Carry */ - iowrite8(QUAD8_CTR_IOR, &chan->control); + iowrite8(SELECT_IOR | DISABLE_AB | LOAD_CNTR | IOR_FLG1_CARRY_FLG2_BORROW= , &chan->control); /* Disable index function; negative index polarity */ - iowrite8(QUAD8_CTR_IDR, &chan->control); + iowrite8(SELECT_IDR | DISABLE_INDEX_MODE | NEGATIVE_INDEX_POLARITY, &chan= ->control); } =20 static int quad8_probe(struct device *dev, unsigned int id) @@ -1251,14 +1336,14 @@ static int quad8_probe(struct device *dev, unsigned= int id) /* Reset Index/Interrupt Register */ iowrite8(0x00, &priv->reg->index_interrupt); /* Reset all counters and disable interrupt function */ - iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper); + iowrite8(RESET_COUNTERS | DISABLE_INTERRUPT_FUNCTION, &priv->reg->channel= _oper); /* Set initial configuration for all counters */ for (i =3D 0; i < QUAD8_NUM_COUNTERS; i++) quad8_init_counter(priv->reg->channel + i); /* Disable Differential Encoder Cable Status for all channels */ iowrite8(0xFF, &priv->reg->cable_status); /* Enable all counters and enable interrupt function */ - iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); + iowrite8(ENABLE_COUNTERS | ENABLE_INTERRUPT_FUNCTION, &priv->reg->channel= _oper); =20 err =3D devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, IRQF_SHARED, counter->name, counter); --=20 2.39.2 From nobody Sat Apr 20 02:52:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D23DC61DA4 for ; Sat, 18 Mar 2023 15:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229824AbjCRPAL (ORCPT ); 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id f67-20020a37d246000000b00745daadd210sm3709162qkj.71.2023.03.18.08.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Mar 2023 08:00:04 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: Johannes Berg , Jonathan Cameron , Andy Shevchenko , Andrew Morton , linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH 2/4] bitfield: Introduce the FIELD_MODIFY() macro Date: Sat, 18 Mar 2023 10:59:49 -0400 Message-Id: <1c1492558c1a72b64bb26f7a44c4e69fff0e6b44.1679149543.git.william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It is a common code pattern to modify a bitfield by masking the field and performing a bitwise OR with the respective FIELD_PREP. Wrap such a task into a macro by introducing FIELD_MODIFY() which modifies the field specified by a mask from a bitfield by putting a val in the field. Signed-off-by: William Breathitt Gray --- include/linux/bitfield.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index ebfa12f69501..b06a98f0a87f 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -38,8 +38,7 @@ * FIELD_PREP(REG_FIELD_D, 0x40); * * Modify: - * reg &=3D ~REG_FIELD_C; - * reg |=3D FIELD_PREP(REG_FIELD_C, c); + * reg =3D FIELD_MODIFY(REG_FIELD_C, reg, c); */ =20 #define __bf_shf(x) (__builtin_ffsll(x) - 1) @@ -155,6 +154,21 @@ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ }) =20 +/** + * FIELD_MODIFY() - modify a bitfield element + * @_mask: shifted mask defining the field's length and position + * @_reg: value of entire bitfield + * @_val: value to put in the field + * + * FIELD_MODIFY() modifies the field specified by @_mask from the + * bitfield passed in as @_reg by putting @val in the field. + */ +#define FIELD_MODIFY(_mask, _reg, _val) \ + ({ \ + __BF_FIELD_CHECK(_mask, _reg, _val, "FIELD_MODIFY: "); \ + (typeof(_mask))(((_reg) & ~(_mask)) | FIELD_PREP(_mask, _val)); \ + }) + extern void __compiletime_error("value doesn't fit into mask") __field_overflow(void); extern void __compiletime_error("bad bitfield mask") --=20 2.39.2 From nobody Sat Apr 20 02:52:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88C9DC61DA4 for ; Sat, 18 Mar 2023 15:00:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229778AbjCRPAX (ORCPT ); Sat, 18 Mar 2023 11:00:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229769AbjCRPAK (ORCPT ); Sat, 18 Mar 2023 11:00:10 -0400 Received: from mail-qt1-x835.google.com (mail-qt1-x835.google.com [IPv6:2607:f8b0:4864:20::835]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 405EAC650 for ; Sat, 18 Mar 2023 08:00:07 -0700 (PDT) Received: by mail-qt1-x835.google.com with SMTP id fy17so6069293qtb.2 for ; Sat, 18 Mar 2023 08:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1679151606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+WNK2qr4NtSUrjAdDswMM5zimvyS9Q/fEHBITpCtqFQ=; b=TmmnWKsPYGN656svxqg3mQUzWxR0l6o8RWv+n8X3IqOyonYd/1Y4DOPFqItpVrfjPC 7Tpxjq8IbRbzdCNUr9Ek//R4irARou5ElELjOI2n9cxjZc7y976Fs+7AZD4SCfHXvqQ3 ZGpZ/ulddBmdEhIoUq8j+K/5ahezz8VkixfX06ODRhBuCn2qfUA6kGhyTVOXmDWXmbY7 BIOjUQO0kt5JFOHJhRsX4g/6gsL1exStQEN1Ktf7b00GzUoAD0cWY4oUkrlsI3Yvy+RB 73fKq35whydhJyXOd0IIddYw+fE4uV1FXROV5UOxu1WrDLxDsddqxyfK6ds1nbh0diBo X53w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679151606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+WNK2qr4NtSUrjAdDswMM5zimvyS9Q/fEHBITpCtqFQ=; b=GwO65PFtsHOv7XE0pDUOD1/0T/Y1TKtwvFhj0dyeKXx1VXFGbYIdONXD2sVC5ts8yl TSaAIsn6emZxUf39dxQ4U6iOcHEotxDLLfAkAuOfy9KOdT861ZF+b6P0tLZz6tGvHasX lEwhTSqdX/frsLZE1I6qy9i2APipK20F0ppqyse4fjy6CrEz60AuaGweRVQoZPPW+FRc dP25L8kQ8Ko4dFWbWPYklbeLeSw0TerFvT7DmIjPGKjsVxDsVl39RJZOEsZUF6nBunhp 4P13kZGrY8ZPu2vX+9/lvfMwK7Mv9Ho7KFvuloxoy1UwKtAzT1yzT3x2xHdjXbExoti+ YhSA== X-Gm-Message-State: AO0yUKXGfM34+4b5o3ACLihEM8nww3nVEsEiPU7w4vCBs1X/fg6vzpCk YSSpAFu3br99YJCCcHTz6SVpEA== X-Google-Smtp-Source: AK7set9FbYD24wW5vz7ACHUGQukbFdImreyrtwLVt9DqelfGeYKlSqNOT/fp6T/JIX2QSRbiE/VRyA== X-Received: by 2002:ac8:5bc3:0:b0:3d6:9528:a0e7 with SMTP id b3-20020ac85bc3000000b003d69528a0e7mr17729940qtb.66.1679151605742; Sat, 18 Mar 2023 08:00:05 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id f67-20020a37d246000000b00745daadd210sm3709162qkj.71.2023.03.18.08.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Mar 2023 08:00:05 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: Johannes Berg , Jonathan Cameron , Andy Shevchenko , Andrew Morton , linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH 3/4] counter: 104-quad-8: Refactor to buffer states for CMR, IOR, and IDR Date: Sat, 18 Mar 2023 10:59:50 -0400 Message-Id: <27359bb20eed0e54f1470cd32be0fd10b06c40fe.1679149543.git.william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The 104-quad-8 driver buffers the device configuration states separately, however each device has only three control registers: CMR, IOR, and IDR. Refactoring to buffer the states of these control registers rather than each configuration separately results in more succinct code that more closely matches what is happening on the device. Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 290 ++++++++++++++--------------------- 1 file changed, 113 insertions(+), 177 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index be7b04b52d85..796f02fc53b8 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -68,32 +68,21 @@ struct quad8_reg { /** * struct quad8 - device private data structure * @lock: lock to prevent clobbering device states during R/W ops - * @counter: instance of the counter_device + * @cmr: array of Counter Mode Register states + * @ior: array of Input / Output Control Register states + * @idr: array of Index Control Register states * @fck_prescaler: array of filter clock prescaler configurations * @preset: array of preset values - * @count_mode: array of count mode configurations - * @quadrature_mode: array of quadrature mode configurations - * @quadrature_scale: array of quadrature mode scale configurations - * @ab_enable: array of A and B inputs enable configurations - * @preset_enable: array of set_to_preset_on_index attribute configurations - * @irq_trigger: array of current IRQ trigger function configurations - * @synchronous_mode: array of index function synchronous mode configurati= ons - * @index_polarity: array of index function polarity configurations * @cable_fault_enable: differential encoder cable status enable configura= tions * @reg: I/O address offset for the device registers */ struct quad8 { spinlock_t lock; + unsigned long cmr[QUAD8_NUM_COUNTERS]; + unsigned long ior[QUAD8_NUM_COUNTERS]; + unsigned long idr[QUAD8_NUM_COUNTERS]; unsigned int fck_prescaler[QUAD8_NUM_COUNTERS]; unsigned int preset[QUAD8_NUM_COUNTERS]; - unsigned int count_mode[QUAD8_NUM_COUNTERS]; - unsigned int quadrature_mode[QUAD8_NUM_COUNTERS]; - unsigned int quadrature_scale[QUAD8_NUM_COUNTERS]; - unsigned int ab_enable[QUAD8_NUM_COUNTERS]; - unsigned int preset_enable[QUAD8_NUM_COUNTERS]; - unsigned int irq_trigger[QUAD8_NUM_COUNTERS]; - unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; - unsigned int index_polarity[QUAD8_NUM_COUNTERS]; unsigned int cable_fault_enable; struct quad8_reg __iomem *reg; }; @@ -102,6 +91,8 @@ struct quad8 { #define FLAG_E BIT(4) /* Up/Down flag */ #define FLAG_UD BIT(5) +/* Counting up */ +#define UP 0x1 =20 #define REGISTER_SELECTION GENMASK(6, 5) =20 @@ -142,7 +133,6 @@ struct quad8 { #define BINARY FIELD_PREP(COUNT_ENCODING, 0x0) /* Normal count */ #define NORMAL_COUNT 0x0 -#define CMR_NORMAL_COUNT FIELD_PREP(COUNT_MODE, NORMAL_COUNT) /* Range Limit */ #define RANGE_LIMIT 0x1 /* Non-recycle count */ @@ -150,13 +140,13 @@ struct quad8 { /* Modulo-N */ #define MODULO_N 0x3 /* Non-quadrature */ -#define NON_QUADRATURE FIELD_PREP(QUADRATURE_MODE, 0x0) +#define NON_QUADRATURE 0x0 /* Quadrature X1 */ -#define QUADRATURE_X1 FIELD_PREP(QUADRATURE_MODE, 0x1) +#define QUADRATURE_X1 0x1 /* Quadrature X2 */ -#define QUADRATURE_X2 FIELD_PREP(QUADRATURE_MODE, 0x2) +#define QUADRATURE_X2 0x2 /* Quadrature X4 */ -#define QUADRATURE_X4 FIELD_PREP(QUADRATURE_MODE, 0x3) +#define QUADRATURE_X4 0x3 =20 /* * Input/Output Control Register @@ -167,10 +157,9 @@ struct quad8 { /* Disable inputs A and B */ #define DISABLE_AB FIELD_PREP(AB_GATE, 0x0) /* Load Counter input */ -#define LOAD_CNTR FIELD_PREP(LOAD_PIN, 0x0) +#define LOAD_CNTR 0x0 /* FLG1 =3D CARRY(active low); FLG2 =3D BORROW(active low) */ #define FLG1_CARRY_FLG2_BORROW 0x0 -#define IOR_FLG1_CARRY_FLG2_BORROW FIELD_PREP(FLG_PINS, FLG1_CARRY_FLG2_BO= RROW) /* FLG1 =3D COMPARE(active low); FLG2 =3D BORROW(active low) */ #define FLG1_COMPARE_FLG2_BORROW 0x1 /* FLG1 =3D Carry(active low)/Borrow(active low); FLG2 =3D U/D(active low)= flag */ @@ -184,9 +173,13 @@ struct quad8 { #define INDEX_MODE BIT(0) #define INDEX_POLARITY BIT(1) /* Disable Index mode */ -#define DISABLE_INDEX_MODE FIELD_PREP(INDEX_MODE, 0x0) +#define DISABLE_INDEX_MODE 0x0 +/* Enable Index mode */ +#define ENABLE_INDEX_MODE 0x1 /* Negative Index Polarity */ -#define NEGATIVE_INDEX_POLARITY FIELD_PREP(INDEX_POLARITY, 0x0) +#define NEGATIVE_INDEX_POLARITY 0x0 +/* Positive Index Polarity */ +#define POSITIVE_INDEX_POLARITY 0x1 =20 /* * Channel Operation Register @@ -299,19 +292,17 @@ static const enum counter_function quad8_count_functi= ons_list[] =3D { static int quad8_function_get(const struct quad8 *const priv, const size_t= id, enum counter_function *const function) { - if (!priv->quadrature_mode[id]) { + switch (FIELD_GET(QUADRATURE_MODE, priv->cmr[id])) { + case NON_QUADRATURE: *function =3D COUNTER_FUNCTION_PULSE_DIRECTION; return 0; - } - - switch (priv->quadrature_scale[id]) { - case 0: + case QUADRATURE_X1: *function =3D COUNTER_FUNCTION_QUADRATURE_X1_A; return 0; - case 1: + case QUADRATURE_X2: *function =3D COUNTER_FUNCTION_QUADRATURE_X2_A; return 0; - case 2: + case QUADRATURE_X4: *function =3D COUNTER_FUNCTION_QUADRATURE_X4; return 0; default: @@ -343,59 +334,42 @@ static int quad8_function_write(struct counter_device= *counter, { struct quad8 *const priv =3D counter_priv(counter); const int id =3D count->id; - unsigned int *const quadrature_mode =3D priv->quadrature_mode + id; - unsigned int *const scale =3D priv->quadrature_scale + id; - unsigned int *const synchronous_mode =3D priv->synchronous_mode + id; u8 __iomem *const control =3D &priv->reg->channel[id].control; + unsigned long *const idr =3D &priv->idr[id]; + unsigned long *const cmr =3D &priv->cmr[id]; unsigned long irqflags; unsigned int mode_cfg; - unsigned int idr_cfg; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - mode_cfg =3D FIELD_PREP(COUNT_MODE, priv->count_mode[id]); - idr_cfg =3D FIELD_PREP(INDEX_POLARITY, priv->index_polarity[id]); - - if (function =3D=3D COUNTER_FUNCTION_PULSE_DIRECTION) { - *quadrature_mode =3D 0; - - /* Quadrature scaling only available in quadrature mode */ - *scale =3D 0; - - mode_cfg |=3D NON_QUADRATURE; + switch (function) { + case COUNTER_FUNCTION_PULSE_DIRECTION: + mode_cfg =3D NON_QUADRATURE; =20 /* Synchronous function not supported in non-quadrature mode */ - if (*synchronous_mode) { + if (FIELD_GET(INDEX_MODE, *idr) =3D=3D ENABLE_INDEX_MODE) { /* Disable synchronous function mode */ - *synchronous_mode =3D 0; - idr_cfg |=3D FIELD_PREP(INDEX_MODE, *synchronous_mode); - iowrite8(SELECT_IDR | idr_cfg, control); - } - } else { - *quadrature_mode =3D 1; - - switch (function) { - case COUNTER_FUNCTION_QUADRATURE_X1_A: - *scale =3D 0; - mode_cfg |=3D QUADRATURE_X1; - break; - case COUNTER_FUNCTION_QUADRATURE_X2_A: - *scale =3D 1; - mode_cfg |=3D QUADRATURE_X2; - break; - case COUNTER_FUNCTION_QUADRATURE_X4: - *scale =3D 2; - mode_cfg |=3D QUADRATURE_X4; - break; - default: - /* should never reach this path */ - spin_unlock_irqrestore(&priv->lock, irqflags); - return -EINVAL; + *idr =3D FIELD_MODIFY(INDEX_MODE, *idr, DISABLE_INDEX_MODE); + iowrite8(*idr, control); } + break; + case COUNTER_FUNCTION_QUADRATURE_X1_A: + mode_cfg =3D QUADRATURE_X1; + break; + case COUNTER_FUNCTION_QUADRATURE_X2_A: + mode_cfg =3D QUADRATURE_X2; + break; + case COUNTER_FUNCTION_QUADRATURE_X4: + mode_cfg =3D QUADRATURE_X4; + break; + default: + /* should never reach this path */ + spin_unlock_irqrestore(&priv->lock, irqflags); + return -EINVAL; } =20 - /* Load mode configuration to Counter Mode Register */ - iowrite8(SELECT_CMR | mode_cfg, control); + *cmr =3D FIELD_MODIFY(QUADRATURE_MODE, *cmr, mode_cfg); + iowrite8(*cmr, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -407,15 +381,11 @@ static int quad8_direction_read(struct counter_device= *counter, enum counter_count_direction *direction) { const struct quad8 *const priv =3D counter_priv(counter); - unsigned int ud_flag; u8 __iomem *const flag_addr =3D &priv->reg->channel[count->id].control; unsigned long flag; =20 flag =3D ioread8(flag_addr); - /* U/D flag: nonzero =3D up, zero =3D down */ - ud_flag =3D FIELD_GET(FLAG_UD, flag); - - *direction =3D (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : + *direction =3D (FIELD_GET(FLAG_UD, flag) =3D=3D UP) ? COUNTER_COUNT_DIREC= TION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD; =20 return 0; @@ -447,7 +417,7 @@ static int quad8_action_read(struct counter_device *cou= nter, =20 /* Handle Index signals */ if (synapse->signal->id >=3D 16) { - if (!priv->preset_enable[count->id]) + if (FIELD_GET(LOAD_PIN, priv->ior[count->id]) =3D=3D LOAD_CNTR) *action =3D COUNTER_SYNAPSE_ACTION_RISING_EDGE; else *action =3D COUNTER_SYNAPSE_ACTION_NONE; @@ -501,37 +471,30 @@ static int quad8_action_read(struct counter_device *c= ounter, } } =20 -enum { - QUAD8_EVENT_CARRY =3D FLG1_CARRY_FLG2_BORROW, - QUAD8_EVENT_COMPARE =3D FLG1_COMPARE_FLG2_BORROW, - QUAD8_EVENT_CARRY_BORROW =3D FLG1_CARRYBORROW_FLG2_UD, - QUAD8_EVENT_INDEX =3D FLG1_INDX_FLG2_E, -}; - static int quad8_events_configure(struct counter_device *counter) { struct quad8 *const priv =3D counter_priv(counter); unsigned long irq_enabled =3D 0; unsigned long irqflags; struct counter_event_node *event_node; - unsigned int next_irq_trigger; - unsigned long ior_cfg; + unsigned long flg_pins; + unsigned long *ior; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 list_for_each_entry(event_node, &counter->events_list, l) { switch (event_node->event) { case COUNTER_EVENT_OVERFLOW: - next_irq_trigger =3D QUAD8_EVENT_CARRY; + flg_pins =3D FLG1_CARRY_FLG2_BORROW; break; case COUNTER_EVENT_THRESHOLD: - next_irq_trigger =3D QUAD8_EVENT_COMPARE; + flg_pins =3D FLG1_COMPARE_FLG2_BORROW; break; case COUNTER_EVENT_OVERFLOW_UNDERFLOW: - next_irq_trigger =3D QUAD8_EVENT_CARRY_BORROW; + flg_pins =3D FLG1_CARRYBORROW_FLG2_UD; break; case COUNTER_EVENT_INDEX: - next_irq_trigger =3D QUAD8_EVENT_INDEX; + flg_pins =3D FLG1_INDX_FLG2_E; break; default: /* should never reach this path */ @@ -542,22 +505,15 @@ static int quad8_events_configure(struct counter_devi= ce *counter) /* Enable IRQ line */ irq_enabled |=3D BIT(event_node->channel); =20 + ior =3D &priv->ior[event_node->channel]; + /* Skip configuration if it is the same as previously set */ - if (priv->irq_trigger[event_node->channel] =3D=3D next_irq_trigger) + if (flg_pins =3D=3D FIELD_GET(FLG_PINS, *ior)) continue; =20 /* Save new IRQ function configuration */ - priv->irq_trigger[event_node->channel] =3D next_irq_trigger; - - /* Load configuration to I/O Control Register */ - ior_cfg =3D FIELD_PREP(AB_GATE, - priv->ab_enable[event_node->channel]) | - FIELD_PREP(LOAD_PIN, - priv->preset_enable[event_node->channel]) | - FIELD_PREP(FLG_PINS, - priv->irq_trigger[event_node->channel]); - iowrite8(SELECT_IOR | ior_cfg, - &priv->reg->channel[event_node->channel].control); + *ior =3D FIELD_MODIFY(FLG_PINS, *ior, flg_pins); + iowrite8(*ior, &priv->reg->channel[event_node->channel].control); } =20 iowrite8(irq_enabled, &priv->reg->index_interrupt); @@ -613,7 +569,7 @@ static int quad8_index_polarity_get(struct counter_devi= ce *counter, const struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; =20 - *index_polarity =3D priv->index_polarity[channel_id]; + *index_polarity =3D FIELD_GET(INDEX_POLARITY, priv->idr[channel_id]); =20 return 0; } @@ -625,17 +581,13 @@ static int quad8_index_polarity_set(struct counter_de= vice *counter, struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; u8 __iomem *const control =3D &priv->reg->channel[channel_id].control; + unsigned long *const idr =3D &priv->idr[channel_id]; unsigned long irqflags; - unsigned int idr_cfg =3D FIELD_PREP(INDEX_POLARITY, index_polarity); =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - idr_cfg |=3D FIELD_PREP(INDEX_MODE, priv->synchronous_mode[channel_id]); - - priv->index_polarity[channel_id] =3D index_polarity; - - /* Load Index Control configuration to Index Control Register */ - iowrite8(SELECT_IDR | idr_cfg, control); + *idr =3D FIELD_MODIFY(INDEX_POLARITY, *idr, index_polarity); + iowrite8(*idr, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -653,8 +605,8 @@ static int quad8_polarity_read(struct counter_device *c= ounter, if (err) return err; =20 - *polarity =3D (index_polarity) ? COUNTER_SIGNAL_POLARITY_POSITIVE : - COUNTER_SIGNAL_POLARITY_NEGATIVE; + *polarity =3D (index_polarity =3D=3D POSITIVE_INDEX_POLARITY) ? COUNTER_S= IGNAL_POLARITY_POSITIVE : + COUNTER_SIGNAL_POLARITY_NEGATIVE; =20 return 0; } @@ -663,7 +615,8 @@ static int quad8_polarity_write(struct counter_device *= counter, struct counter_signal *signal, enum counter_signal_polarity polarity) { - const u32 pol =3D (polarity =3D=3D COUNTER_SIGNAL_POLARITY_POSITIVE) ? 1 = : 0; + const u32 pol =3D (polarity =3D=3D COUNTER_SIGNAL_POLARITY_POSITIVE) ? + POSITIVE_INDEX_POLARITY : NEGATIVE_INDEX_POLARITY; =20 return quad8_index_polarity_set(counter, signal, pol); } @@ -680,7 +633,7 @@ static int quad8_synchronous_mode_get(struct counter_de= vice *counter, const struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; =20 - *synchronous_mode =3D priv->synchronous_mode[channel_id]; + *synchronous_mode =3D FIELD_GET(INDEX_MODE, priv->idr[channel_id]); =20 return 0; } @@ -692,23 +645,19 @@ static int quad8_synchronous_mode_set(struct counter_= device *counter, struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; u8 __iomem *const control =3D &priv->reg->channel[channel_id].control; + unsigned long *const idr =3D &priv->idr[channel_id]; unsigned long irqflags; - unsigned int idr_cfg =3D FIELD_PREP(INDEX_MODE, synchronous_mode); =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - idr_cfg |=3D FIELD_PREP(INDEX_POLARITY, priv->index_polarity[channel_id]); - /* Index function must be non-synchronous in non-quadrature mode */ - if (synchronous_mode && !priv->quadrature_mode[channel_id]) { + if (synchronous_mode && FIELD_GET(QUADRATURE_MODE, *idr) =3D=3D NON_QUADR= ATURE) { spin_unlock_irqrestore(&priv->lock, irqflags); return -EINVAL; } =20 - priv->synchronous_mode[channel_id] =3D synchronous_mode; - - /* Load Index Control configuration to Index Control Register */ - iowrite8(SELECT_IDR | idr_cfg, control); + *idr =3D FIELD_MODIFY(INDEX_MODE, *idr, synchronous_mode); + iowrite8(*idr, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -730,7 +679,7 @@ static int quad8_count_mode_read(struct counter_device = *counter, { const struct quad8 *const priv =3D counter_priv(counter); =20 - switch (priv->count_mode[count->id]) { + switch (FIELD_GET(COUNT_MODE, priv->cmr[count->id])) { case NORMAL_COUNT: *cnt_mode =3D COUNTER_COUNT_MODE_NORMAL; break; @@ -754,8 +703,8 @@ static int quad8_count_mode_write(struct counter_device= *counter, { struct quad8 *const priv =3D counter_priv(counter); unsigned int count_mode; - unsigned int mode_cfg; u8 __iomem *const control =3D &priv->reg->channel[count->id].control; + unsigned long *const cmr =3D &priv->cmr[count->id]; unsigned long irqflags; =20 switch (cnt_mode) { @@ -778,20 +727,8 @@ static int quad8_count_mode_write(struct counter_devic= e *counter, =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - priv->count_mode[count->id] =3D count_mode; - - /* Set count mode configuration value */ - mode_cfg =3D FIELD_PREP(COUNT_MODE, count_mode); - - /* Add quadrature mode configuration */ - if (priv->quadrature_mode[count->id]) - mode_cfg |=3D FIELD_PREP(QUADRATURE_MODE, - priv->quadrature_scale[count->id] + 1); - else - mode_cfg |=3D NON_QUADRATURE; - - /* Load mode configuration to Counter Mode Register */ - iowrite8(SELECT_CMR | mode_cfg, control); + *cmr =3D FIELD_MODIFY(COUNT_MODE, *cmr, count_mode); + iowrite8(*cmr, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -803,7 +740,7 @@ static int quad8_count_enable_read(struct counter_devic= e *counter, { const struct quad8 *const priv =3D counter_priv(counter); =20 - *enable =3D priv->ab_enable[count->id]; + *enable =3D FIELD_GET(AB_GATE, priv->ior[count->id]); =20 return 0; } @@ -813,19 +750,13 @@ static int quad8_count_enable_write(struct counter_de= vice *counter, { struct quad8 *const priv =3D counter_priv(counter); u8 __iomem *const control =3D &priv->reg->channel[count->id].control; + unsigned long *const ior =3D &priv->ior[count->id]; unsigned long irqflags; - unsigned int ior_cfg; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - priv->ab_enable[count->id] =3D enable; - - ior_cfg =3D FIELD_PREP(AB_GATE, enable) | - FIELD_PREP(LOAD_PIN, priv->preset_enable[count->id]) | - FIELD_PREP(FLG_PINS, priv->irq_trigger[count->id]); - - /* Load I/O control configuration */ - iowrite8(SELECT_IOR | ior_cfg, control); + *ior =3D FIELD_MODIFY(AB_GATE, *ior, enable); + iowrite8(*ior, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -903,7 +834,7 @@ static int quad8_count_ceiling_read(struct counter_devi= ce *counter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Range Limit and Modulo-N count modes use preset value as ceiling */ - switch (priv->count_mode[count->id]) { + switch (FIELD_GET(COUNT_MODE, priv->cmr[count->id])) { case RANGE_LIMIT: case MODULO_N: *ceiling =3D priv->preset[count->id]; @@ -930,7 +861,7 @@ static int quad8_count_ceiling_write(struct counter_dev= ice *counter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Range Limit and Modulo-N count modes use preset value as ceiling */ - switch (priv->count_mode[count->id]) { + switch (FIELD_GET(COUNT_MODE, priv->cmr[count->id])) { case RANGE_LIMIT: case MODULO_N: quad8_preset_register_set(priv, count->id, ceiling); @@ -949,7 +880,8 @@ static int quad8_count_preset_enable_read(struct counte= r_device *counter, { const struct quad8 *const priv =3D counter_priv(counter); =20 - *preset_enable =3D !priv->preset_enable[count->id]; + /* Preset enable is active low in Input/Output Control register */ + *preset_enable =3D !FIELD_GET(LOAD_PIN, priv->ior[count->id]); =20 return 0; } @@ -960,22 +892,14 @@ static int quad8_count_preset_enable_write(struct cou= nter_device *counter, { struct quad8 *const priv =3D counter_priv(counter); u8 __iomem *const control =3D &priv->reg->channel[count->id].control; + unsigned long *const ior =3D &priv->ior[count->id]; unsigned long irqflags; - unsigned int ior_cfg; - - /* Preset enable is active low in Input/Output Control register */ - preset_enable =3D !preset_enable; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - priv->preset_enable[count->id] =3D preset_enable; - - ior_cfg =3D FIELD_PREP(AB_GATE, priv->ab_enable[count->id]) | - FIELD_PREP(LOAD_PIN, preset_enable) | - FIELD_PREP(FLG_PINS, priv->irq_trigger[count->id]); - - /* Load I/O control configuration to Input / Output Control Register */ - iowrite8(SELECT_IOR | ior_cfg, control); + /* Preset enable is active low in Input/Output Control register */ + *ior =3D FIELD_MODIFY(LOAD_PIN, *ior, !preset_enable); + iowrite8(*ior, control); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -1238,6 +1162,7 @@ static irqreturn_t quad8_irq_handler(int irq, void *p= rivate) struct quad8 *const priv =3D counter_priv(counter); unsigned long irq_status; unsigned long channel; + unsigned int flg_pins; u8 event; =20 irq_status =3D ioread8(&priv->reg->interrupt_status); @@ -1245,23 +1170,24 @@ static irqreturn_t quad8_irq_handler(int irq, void = *private) return IRQ_NONE; =20 for_each_set_bit(channel, &irq_status, QUAD8_NUM_COUNTERS) { - switch (priv->irq_trigger[channel]) { - case QUAD8_EVENT_CARRY: + flg_pins =3D FIELD_GET(FLG_PINS, priv->ior[channel]); + switch (flg_pins) { + case FLG1_CARRY_FLG2_BORROW: event =3D COUNTER_EVENT_OVERFLOW; break; - case QUAD8_EVENT_COMPARE: + case FLG1_COMPARE_FLG2_BORROW: event =3D COUNTER_EVENT_THRESHOLD; break; - case QUAD8_EVENT_CARRY_BORROW: + case FLG1_CARRYBORROW_FLG2_UD: event =3D COUNTER_EVENT_OVERFLOW_UNDERFLOW; break; - case QUAD8_EVENT_INDEX: + case FLG1_INDX_FLG2_E: event =3D COUNTER_EVENT_INDEX; break; default: /* should never reach this path */ WARN_ONCE(true, "invalid interrupt trigger function %u configured for c= hannel %lu\n", - priv->irq_trigger[channel], channel); + flg_pins, channel); continue; } =20 @@ -1274,8 +1200,9 @@ static irqreturn_t quad8_irq_handler(int irq, void *p= rivate) return IRQ_HANDLED; } =20 -static void quad8_init_counter(struct channel_reg __iomem *const chan) +static void quad8_init_counter(struct quad8 *const priv, const size_t chan= nel) { + struct channel_reg __iomem *const chan =3D priv->reg->channel + channel; unsigned long i; =20 /* Reset Byte Pointer */ @@ -1292,12 +1219,21 @@ static void quad8_init_counter(struct channel_reg _= _iomem *const chan) iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control); /* Reset Error flag */ iowrite8(SELECT_RLD | RESET_E, &chan->control); + /* Binary encoding; Normal count; non-quadrature mode */ - iowrite8(SELECT_CMR | BINARY | CMR_NORMAL_COUNT | NON_QUADRATURE, &chan->= control); + priv->cmr[channel] =3D SELECT_CMR | BINARY | FIELD_PREP(COUNT_MODE, NORMA= L_COUNT) | + FIELD_PREP(QUADRATURE_MODE, NON_QUADRATURE); + iowrite8(priv->cmr[channel], &chan->control); + /* Disable A and B inputs; preset on index; FLG1 as Carry */ - iowrite8(SELECT_IOR | DISABLE_AB | LOAD_CNTR | IOR_FLG1_CARRY_FLG2_BORROW= , &chan->control); + priv->ior[channel] =3D SELECT_IOR | DISABLE_AB | FIELD_PREP(LOAD_PIN, LOA= D_CNTR) | + FIELD_PREP(FLG_PINS, FLG1_CARRY_FLG2_BORROW); + iowrite8(priv->ior[channel], &chan->control); + /* Disable index function; negative index polarity */ - iowrite8(SELECT_IDR | DISABLE_INDEX_MODE | NEGATIVE_INDEX_POLARITY, &chan= ->control); + priv->idr[channel] =3D SELECT_IDR | FIELD_PREP(INDEX_MODE, DISABLE_INDEX_= MODE) | + FIELD_PREP(INDEX_POLARITY, NEGATIVE_INDEX_POLARITY); + iowrite8(priv->idr[channel], &chan->control); } =20 static int quad8_probe(struct device *dev, unsigned int id) @@ -1339,7 +1275,7 @@ static int quad8_probe(struct device *dev, unsigned i= nt id) iowrite8(RESET_COUNTERS | DISABLE_INTERRUPT_FUNCTION, &priv->reg->channel= _oper); /* Set initial configuration for all counters */ for (i =3D 0; i < QUAD8_NUM_COUNTERS; i++) - quad8_init_counter(priv->reg->channel + i); + quad8_init_counter(priv, i); /* Disable Differential Encoder Cable Status for all channels */ iowrite8(0xFF, &priv->reg->cable_status); /* Enable all counters and enable interrupt function */ --=20 2.39.2 From nobody Sat Apr 20 02:52:14 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4012EC7618A for ; Sat, 18 Mar 2023 15:00:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbjCRPAP (ORCPT ); Sat, 18 Mar 2023 11:00:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229738AbjCRPAJ (ORCPT ); Sat, 18 Mar 2023 11:00:09 -0400 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCE841716D for ; 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id f67-20020a37d246000000b00745daadd210sm3709162qkj.71.2023.03.18.08.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Mar 2023 08:00:06 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: Johannes Berg , Jonathan Cameron , Andy Shevchenko , Andrew Morton , linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH 4/4] counter: 104-quad-8: Utilize helper functions to handle PR, FLAG and PSC Date: Sat, 18 Mar 2023 10:59:51 -0400 Message-Id: <71496f9295e68388ce07f3051bf5882177be83c5.1679149543.git.william.gray@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Preset Register (PR), Flag Register (FLAG), and Filter Clock Prescaler (PSC) have common usage patterns. Wrap up such usage into dedicated functions to improve code clarity. Signed-off-by: William Breathitt Gray --- drivers/counter/104-quad-8.c | 103 +++++++++++++++-------------------- 1 file changed, 45 insertions(+), 58 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index 796f02fc53b8..27ec905ebe85 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -241,41 +241,49 @@ static int quad8_count_read(struct counter_device *co= unter, return 0; } =20 +static void quad8_preset_register_set(struct quad8 *const priv, const size= _t id, + const unsigned long preset) +{ + struct channel_reg __iomem *const chan =3D priv->reg->channel + id; + int i; + + /* Reset Byte Pointer */ + iowrite8(SELECT_RLD | RESET_BP, &chan->control); + + /* Set Preset Register */ + for (i =3D 0; i < 3; i++) + iowrite8(preset >> (8 * i), &chan->data); +} + +static void quad8_flag_register_reset(struct quad8 *const priv, const size= _t id) +{ + struct channel_reg __iomem *const chan =3D priv->reg->channel + id; + + /* Reset Borrow, Carry, Compare, and Sign flags */ + iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control); + /* Reset Error flag */ + iowrite8(SELECT_RLD | RESET_E, &chan->control); +} + static int quad8_count_write(struct counter_device *counter, struct counter_count *count, u64 val) { struct quad8 *const priv =3D counter_priv(counter); struct channel_reg __iomem *const chan =3D priv->reg->channel + count->id; unsigned long irqflags; - int i; =20 if (val > LS7267_CNTR_MAX) return -ERANGE; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 - /* Reset Byte Pointer */ - iowrite8(SELECT_RLD | RESET_BP, &chan->control); - /* Counter can only be set via Preset Register */ - for (i =3D 0; i < 3; i++) - iowrite8(val >> (8 * i), &chan->data); - + quad8_preset_register_set(priv, count->id, val); /* Transfer Preset Register to Counter */ iowrite8(SELECT_RLD | TRANSFER_PR_TO_CNTR, &chan->control); - - /* Reset Byte Pointer */ - iowrite8(SELECT_RLD | RESET_BP, &chan->control); - + quad8_flag_register_reset(priv, count->id); /* Set Preset Register back to original value */ - val =3D priv->preset[count->id]; - for (i =3D 0; i < 3; i++) - iowrite8(val >> (8 * i), &chan->data); - - /* Reset Borrow, Carry, Compare, and Sign flags */ - iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control); - /* Reset Error flag */ - iowrite8(SELECT_RLD | RESET_E, &chan->control); + quad8_preset_register_set(priv, count->id, priv->preset[count->id]); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -791,22 +799,6 @@ static int quad8_count_preset_read(struct counter_devi= ce *counter, return 0; } =20 -static void quad8_preset_register_set(struct quad8 *const priv, const int = id, - const unsigned int preset) -{ - struct channel_reg __iomem *const chan =3D priv->reg->channel + id; - int i; - - priv->preset[id] =3D preset; - - /* Reset Byte Pointer */ - iowrite8(SELECT_RLD | RESET_BP, &chan->control); - - /* Set Preset Register */ - for (i =3D 0; i < 3; i++) - iowrite8(preset >> (8 * i), &chan->data); -} - static int quad8_count_preset_write(struct counter_device *counter, struct counter_count *count, u64 preset) { @@ -818,6 +810,7 @@ static int quad8_count_preset_write(struct counter_devi= ce *counter, =20 spin_lock_irqsave(&priv->lock, irqflags); =20 + priv->preset[count->id] =3D preset; quad8_preset_register_set(priv, count->id, preset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); @@ -864,6 +857,7 @@ static int quad8_count_ceiling_write(struct counter_dev= ice *counter, switch (FIELD_GET(COUNT_MODE, priv->cmr[count->id])) { case RANGE_LIMIT: case MODULO_N: + priv->preset[count->id] =3D ceiling; quad8_preset_register_set(priv, count->id, ceiling); spin_unlock_irqrestore(&priv->lock, irqflags); return 0; @@ -985,25 +979,30 @@ static int quad8_signal_fck_prescaler_read(struct cou= nter_device *counter, return 0; } =20 +static void quad8_filter_clock_prescaler_set(struct quad8 *const priv, con= st size_t id, + const u8 prescaler) +{ + struct channel_reg __iomem *const chan =3D priv->reg->channel + id; + + /* Reset Byte Pointer */ + iowrite8(SELECT_RLD | RESET_BP, &chan->control); + /* Reset filter clock factor */ + iowrite8(prescaler, &chan->data); + iowrite8(SELECT_RLD | TRANSFER_PR0_TO_PSC, &chan->control); +} + static int quad8_signal_fck_prescaler_write(struct counter_device *counter, struct counter_signal *signal, u8 prescaler) { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id / 2; - struct channel_reg __iomem *const chan =3D priv->reg->channel + channel_i= d; unsigned long irqflags; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 priv->fck_prescaler[channel_id] =3D prescaler; - - /* Reset Byte Pointer */ - iowrite8(SELECT_RLD | RESET_BP, &chan->control); - - /* Set filter clock factor */ - iowrite8(prescaler, &chan->data); - iowrite8(SELECT_RLD | RESET_BP | TRANSFER_PR0_TO_PSC, &chan->control); + quad8_filter_clock_prescaler_set(priv, channel_id, prescaler); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -1203,22 +1202,10 @@ static irqreturn_t quad8_irq_handler(int irq, void = *private) static void quad8_init_counter(struct quad8 *const priv, const size_t chan= nel) { struct channel_reg __iomem *const chan =3D priv->reg->channel + channel; - unsigned long i; =20 - /* Reset Byte Pointer */ - iowrite8(SELECT_RLD | RESET_BP, &chan->control); - /* Reset filter clock factor */ - iowrite8(0, &chan->data); - iowrite8(SELECT_RLD | RESET_BP | TRANSFER_PR0_TO_PSC, &chan->control); - /* Reset Byte Pointer */ - iowrite8(SELECT_RLD | RESET_BP, &chan->control); - /* Reset Preset Register */ - for (i =3D 0; i < 3; i++) - iowrite8(0x00, &chan->data); - /* Reset Borrow, Carry, Compare, and Sign flags */ - iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control); - /* Reset Error flag */ - iowrite8(SELECT_RLD | RESET_E, &chan->control); + quad8_filter_clock_prescaler_set(priv, channel, 0); + quad8_preset_register_set(priv, channel, 0); + quad8_flag_register_reset(priv, channel); =20 /* Binary encoding; Normal count; non-quadrature mode */ priv->cmr[channel] =3D SELECT_CMR | BINARY | FIELD_PREP(COUNT_MODE, NORMA= L_COUNT) | --=20 2.39.2