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Thu, 9 Mar 2023 02:54:33 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 01/14] iommu: Add iommu_get_unmanaged_domain helper Date: Thu, 9 Mar 2023 02:53:37 -0800 Message-ID: <9b1077601cace998533129327f5e7ad946752d29.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|CH0PR12MB5234:EE_ X-MS-Office365-Filtering-Correlation-Id: d0d3ea8f-7eb0-491f-397a-08db208cafdc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yk84aD8Dv/eDWYMltwGPtGgg8kPBtET+w0WBdpof+Kzh4yExMsc5VXZQLlF61rgP/cdhaQ7vG4NnUpnNSK+SQEBMuAEGd9kOgjujm3Dti9P4M5mH7mVGMZy0ItvJTRnSDA28mHADah+0rMTi3+M+184bj6ZIJ3gkVgl/1qJDbtAmmCUQjS9vuIBnNTv8v+QBq7q9G+U1NdU+4iFiMIQqdbwLFiIavZR93zaN7yu6ixdm6dVEJqqMumQT6/PWMC6Oj7I9ILNC6LEm+t2N1sAILNrsaD3iKsh/8RRqhwaufJOqnnVo3OASAweim4evFzsDOE5SUgFsm706fJQhkgAx3+1tQcMFnSKJ83ZVVLXcqaqjCtG2/zBnHdo5cOryApwX68uNq4U5YIoudyTA7HxPSo4bHb+/AIgypNPFJ7KWwymubwvDufukSgMEpNMcsSdegBhZ2S8p2CjE2pn6zWOsOq8gUOXfcMGJ5+AK0vezsY12kO3Gvzo9j0h7JrFtCCfQ4nOmjDKz1N7/H+0Axp7zZIoQfy0d50wCfuLMP+sDOl1XNR4Oto3T5Qe4NUO7zft49KD0ZkwXMr5cMLkeoJRj95/GR+oBkGzd5e/G6C3PakkadLBtFrWK7vha/rXnMasLceN6zWj6yYOlOWdoLpPaAYfJE+vcq2h+APdKvPSLHdZk1CEwImxRgsiDQsA4UU/M5eDYyL9GEmGHvnWer8SRyhbzq9unMnQgLXagzOja9QAb/FwX/utnSdxsveYWzQRX X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(82310400005)(82740400003)(36860700001)(83380400001)(426003)(47076005)(36756003)(478600001)(40480700001)(54906003)(110136005)(7636003)(356005)(316002)(336012)(7696005)(2616005)(40460700003)(186003)(26005)(7416002)(5660300002)(70206006)(70586007)(41300700001)(8936002)(4326008)(2906002)(8676002)(86362001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:41.8981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0d3ea8f-7eb0-491f-397a-08db208cafdc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5234 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The nature of ITS virtualization on ARM is done via hypercalls, so kernel handles all IOVA mappings for the MSI doorbell in iommu_dma_prepare_msi() and iommu_dma_compose_msi_msg(). The current virtualization solution with a 2-stage nested translation setup is to do 1:1 IOVA mappings at stage-1 guest-level IO page table via a RMR region in guest-level IORT, aligning with an IOVA region that's predefined and mapped in the host kernel: [stage-2 host level] #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 ... iommu_get_msi_cookie(): cookie->msi_iova =3D MSI_IOVA_BASE; ... iommu_dma_prepare_msi(its_pa): domain =3D iommu_get_domain_for_dev(dev); iommu_dma_get_msi_page(its_pa, domain): cookie =3D domain->iova_cookie; iova =3D iommu_dma_alloc_iova(): return cookie->msi_iova - size; iommu_map(iova, its_pa, ...); [stage-1 guest level] // Define in IORT a RMR [MSI_IOVA_BASE, MSI_IOVA_LENGTH] ... iommu_create_device_direct_mappings(): iommu_map(iova=3DMSI_IOVA_BASE, pa=3DMSI_IOVA_BASE, len=3DMSI_IOVA_LENGTH); This solution calling iommu_get_domain_for_dev() needs the device to get attached to a host-level iommu_domain that has the msi_cookie. On the other hand, IOMMUFD designs two iommu_domain objects to represent the two stages: a stage-1 domain (IOMMU_DOMAIN_NESTED type) and a stage-2 domain (IOMMU_DOMAIN_UNMANAGED type). In this design, the device will be attached to the stage-1 domain representing a guest-level IO page table, or a Context Descriptor Table in SMMU's term. This is obviously a mismatch, as the iommu_get_domain_for_dev() does not return the correct domain pointer in iommu_dma_prepare_msi(). Add an iommu_get_unmanaged_domain helper to allow drivers to return the correct IOMMU_DOMAIN_UNMANAGED iommu_domain having the IOVA mappings for the msi_cookie. Keep it in the iommu-priv header for internal use only. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/dma-iommu.c | 5 +++-- drivers/iommu/iommu-priv.h | 15 +++++++++++++++ include/linux/iommu.h | 2 ++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 99b2646cb5c7..6b0409d0ff85 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -31,6 +31,7 @@ #include =20 #include "dma-iommu.h" +#include "iommu-priv.h" =20 struct iommu_dma_msi_page { struct list_head list; @@ -1652,7 +1653,7 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_p= age(struct device *dev, int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) { struct device *dev =3D msi_desc_to_dev(desc); - struct iommu_domain *domain =3D iommu_get_domain_for_dev(dev); + struct iommu_domain *domain =3D iommu_get_unmanaged_domain(dev); struct iommu_dma_msi_page *msi_page; static DEFINE_MUTEX(msi_prepare_lock); /* see below */ =20 @@ -1685,7 +1686,7 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys= _addr_t msi_addr) void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg) { struct device *dev =3D msi_desc_to_dev(desc); - const struct iommu_domain *domain =3D iommu_get_domain_for_dev(dev); + const struct iommu_domain *domain =3D iommu_get_unmanaged_domain(dev); const struct iommu_dma_msi_page *msi_page; =20 msi_page =3D msi_desc_get_iommu_cookie(desc); diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index a6e694f59f64..da8044da9ad8 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -15,6 +15,21 @@ static inline const struct iommu_ops *dev_iommu_ops(stru= ct device *dev) return dev->iommu->iommu_dev->ops; } =20 +static inline struct iommu_domain *iommu_get_unmanaged_domain(struct devic= e *dev) +{ + const struct iommu_ops *ops; + + if (!dev->iommu || !dev->iommu->iommu_dev) + goto attached_domain; + + ops =3D dev_iommu_ops(dev); + if (ops->get_unmanaged_domain) + return ops->get_unmanaged_domain(dev); + +attached_domain: + return iommu_get_domain_for_dev(dev); +} + int iommu_group_replace_domain(struct iommu_group *group, struct iommu_domain *new_domain); =20 diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 080278c8154d..76c65cc4fc15 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -275,6 +275,8 @@ struct iommu_ops { struct iommu_domain *parent, const void *user_data); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:43.6481 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cae24fa-5983-45f2-41fe-08db208cb0e7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4433 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the following data structures for corresponding ioctls: iommu_hwpt_arm_smmuv3 =3D> IOMMUFD_CMD_HWPT_ALLOC iommu_hwpt_invalidate_arm_smmuv3 =3D> IOMMUFD_CMD_HWPT_INVALIDATE Also, add IOMMU_HW_INFO_TYPE_ARM_SMMUV3 and IOMMU_PGTBL_TYPE_ARM_SMMUV3_S1 to the header and corresponding type/size arrays. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/hw_pagetable.c | 4 +++ drivers/iommu/iommufd/main.c | 1 + include/uapi/linux/iommufd.h | 50 ++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/h= w_pagetable.c index 8f9985bddeeb..5e798b2f9a3a 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -173,6 +173,7 @@ iommufd_hw_pagetable_alloc(struct iommufd_ctx *ictx, st= ruct iommufd_ioas *ioas, static const size_t iommufd_hwpt_alloc_data_size[] =3D { [IOMMU_HWPT_TYPE_DEFAULT] =3D 0, [IOMMU_HWPT_TYPE_VTD_S1] =3D sizeof(struct iommu_hwpt_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] =3D sizeof(struct iommu_hwpt_arm_smmuv3), }; =20 /* @@ -183,6 +184,8 @@ const u64 iommufd_hwpt_type_bitmaps[] =3D { [IOMMU_HW_INFO_TYPE_DEFAULT] =3D BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT), [IOMMU_HW_INFO_TYPE_INTEL_VTD] =3D BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | BIT_ULL(IOMMU_HWPT_TYPE_VTD_S1), + [IOMMU_HW_INFO_TYPE_ARM_SMMUV3] =3D BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | + BIT_ULL(IOMMU_HWPT_TYPE_ARM_SMMUV3), }; =20 /* Return true if type is supported, otherwise false */ @@ -329,6 +332,7 @@ int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) */ static const size_t iommufd_hwpt_invalidate_info_size[] =3D { [IOMMU_HWPT_TYPE_VTD_S1] =3D sizeof(struct iommu_hwpt_invalidate_intel_vt= d), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] =3D sizeof(struct iommu_hwpt_invalidate_arm_= smmuv3), }; =20 int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 514db4c26927..0b0097af7c86 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -280,6 +280,7 @@ union ucmd_buffer { * path. */ struct iommu_hwpt_invalidate_intel_vtd vtd; + struct iommu_hwpt_invalidate_arm_smmuv3 smmuv3; }; =20 struct iommufd_ioctl_op { diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 2a6c326391b2..0d5551b1b2be 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -352,10 +352,13 @@ struct iommu_vfio_ioas { * enum iommu_hwpt_type - IOMMU HWPT Type * @IOMMU_HWPT_TYPE_DEFAULT: default * @IOMMU_HWPT_TYPE_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_TYPE_ARM_SMMUV3: ARM SMMUv3 stage-1 Context Descriptor + * table */ enum iommu_hwpt_type { IOMMU_HWPT_TYPE_DEFAULT, IOMMU_HWPT_TYPE_VTD_S1, + IOMMU_HWPT_TYPE_ARM_SMMUV3, }; =20 /** @@ -411,6 +414,28 @@ struct iommu_hwpt_intel_vtd { __u32 __reserved; }; =20 +/** + * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 specific page table data + * + * @flags: page table entry attributes + * @s2vmid: Virtual machine identifier + * @s1ctxptr: Stage-1 context descriptor pointer + * @s1cdmax: Number of CDs pointed to by s1ContextPtr + * @s1fmt: Stage-1 Format + * @s1dss: Default substream + */ +struct iommu_hwpt_arm_smmuv3 { +#define IOMMU_SMMUV3_FLAG_S2 (1 << 0) /* if unset, stage-1 */ +#define IOMMU_SMMUV3_FLAG_VMID (1 << 1) /* vmid override */ + __u64 flags; + __u32 s2vmid; + __u32 __reserved; + __u64 s1ctxptr; + __u64 s1cdmax; + __u64 s1fmt; + __u64 s1dss; +}; + /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) @@ -446,6 +471,8 @@ struct iommu_hwpt_intel_vtd { * +------------------------------+-------------------------------------+-= ----------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_intel_vtd | = HWPT | * +------------------------------+-------------------------------------+-= ----------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_arm_smmuv3 | = IOAS/HWPT | + * +------------------------------+---------------------------------------= ----------+ */ struct iommu_hwpt_alloc { __u32 size; @@ -463,10 +490,12 @@ struct iommu_hwpt_alloc { /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type + * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_DEFAULT, IOMMU_HW_INFO_TYPE_INTEL_VTD, + IOMMU_HW_INFO_TYPE_ARM_SMMUV3, }; =20 /** @@ -591,6 +620,25 @@ struct iommu_hwpt_invalidate_intel_vtd { __u64 nb_granules; }; =20 +/** + * struct iommu_hwpt_invalidate_arm_smmuv3 - ARM SMMUv3 cahce invalidation= info + * @flags: boolean attributes of cache invalidation command + * @opcode: opcode of cache invalidation command + * @ssid: SubStream ID + * @granule_size: page/block size of the mapping in bytes + * @range: IOVA range to invalidate + */ +struct iommu_hwpt_invalidate_arm_smmuv3 { +#define IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF (1 << 0) + __u64 flags; + __u8 opcode; + __u8 padding[3]; + __u32 asid; + __u32 ssid; + __u32 granule_size; + struct iommu_iova_range range; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) @@ -609,6 +657,8 @@ struct iommu_hwpt_invalidate_intel_vtd { * +------------------------------+---------------------------------------= -+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_invalidate_intel_vtd= | * +------------------------------+---------------------------------------= -+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_invalidate_arm_smmuv= 3| + * +------------------------------+---------------------------------------= -+ */ struct iommu_hwpt_invalidate { __u32 size; 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Thu, 9 Mar 2023 02:54:34 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 03/14] iommufd/device: Setup MSI on kernel-managed domains Date: Thu, 9 Mar 2023 02:53:39 -0800 Message-ID: <5149b7e711a46e81aea8515676cf0e45608b3afd.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E8:EE_|SJ2PR12MB8649:EE_ X-MS-Office365-Filtering-Correlation-Id: f56f7c7c-84df-4e8c-b1f0-08db208cb19f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Nzp/q2s89mmRmMG2JtRD3iM6C5AG4h5iaRtYtHQWIk9LbuyP/2uR0DbYlVJ5chED/tsDAyi3hsj4Cr5k1yjrEAoPn9n/VsoAdNlqzcUwVm8rCP4vvPePMh9DiUZySRbsZW+PYrSwIOtJPceTVEKJD6Awd1bOQtNHeRR6ltp3VQIIf1qE6iNTKMtqn2GrhtmAUKCyJ80rt76ttbfZHZxk4ysJAr+q2lDmJWnGBfUnGWUqmXyAMiAOU+FYPdsEFDGXsV/0YHwVIfYWYHdzpdEDCIKxYpn5AH0MqMazpEetmIog3Svz6pdBLuUZXQ/Lbd/wk6GIU7J7G2WMol0omXSGeH7NhXLXV9FnFByQtUpyFZQEffdMEkeoWFwWAftej+5cFCuY3d4tipztIkyEFHhTDi9HrHQetSIkeVgWGw/ane0FSvzOpNXm2OrF4rjctvbLsgq68QBvcIgYqfSLMLljkLprRg2lwuVewQfVbw89zWs1ZWEzK+sx+yGGt9dEEDf5qO3vBEgRtp1DufSXvfHQQ8akz4hiHmCR0DmFuz0kV1Qm/w4svQm/E78lOGIo70Z/yvNS4RhOqVHDs8HHOXkb5j3UneqCNNzNg+A1b5Rnas4RKMqSiJFrrr43UpeoTD6YI8e3tPq7u6f6emW9P/MpMWYRbgHYSosHhOMBJoJrO3ViSlmnvuR9DhmLAcTrvRhDA57n25NPkj/Hzdvn4VO/jp7GexjUjLQRZoFmcXgOgAuY7TmngpIjeZaZRrU5OS7/ X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(346002)(136003)(376002)(39860400002)(451199018)(36840700001)(46966006)(40470700004)(36860700001)(86362001)(7636003)(356005)(82740400003)(70586007)(7416002)(70206006)(36756003)(2906002)(8936002)(5660300002)(4326008)(8676002)(41300700001)(82310400005)(47076005)(186003)(26005)(336012)(40480700001)(2616005)(426003)(40460700003)(83380400001)(316002)(54906003)(478600001)(7696005)(110136005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:44.8881 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f56f7c7c-84df-4e8c-b1f0-08db208cb19f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8649 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The IOMMU_RESV_SW_MSI is a kernel-managed domain thing. So, it should be only setup on a kernel-managed domain only. If the attaching domain is a user-managed domain, redirect the hwpt to hwpt->parent to do it correctly. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index f95b558f5e95..a3e7d2889164 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -350,7 +350,8 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, * call iommu_get_msi_cookie() on its behalf. This is necessary to setup * the MSI window so iommu_dma_prepare_msi() can install pages into our * domain after request_irq(). If it is not done interrupts will not - * work on this domain. + * work on this domain. And the msi_cookie should be always set into the + * kernel-managed (parent) domain. * * FIXME: This is conceptually broken for iommufd since we want to allow * userspace to change the domains, eg switch from an identity IOAS to a @@ -358,6 +359,8 @@ static int iommufd_group_setup_msi(struct iommufd_group= *igroup, * matches what the IRQ layer actually expects in a newly created * domain. */ + if (hwpt->parent) + hwpt =3D hwpt->parent; if (sw_msi_start !=3D PHYS_ADDR_MAX && !hwpt->msi_cookie) { rc =3D iommu_get_msi_cookie(hwpt->domain, sw_msi_start); if (rc) --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7A2FC61DA4 for ; Thu, 9 Mar 2023 10:55:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231249AbjCIKzY (ORCPT ); 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Thu, 9 Mar 2023 02:54:36 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 9 Mar 2023 02:54:36 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 9 Mar 2023 02:54:35 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 04/14] iommu/arm-smmu-v3: Add arm_smmu_hw_info Date: Thu, 9 Mar 2023 02:53:40 -0800 Message-ID: <494e36cbb77d49e11427b308868dbc1b0e19fe18.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108EB:EE_|DM4PR12MB5167:EE_ X-MS-Office365-Filtering-Correlation-Id: e1751a30-cbd3-47a0-88a6-08db208cb295 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:46.4836 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e1751a30-cbd3-47a0-88a6-08db208cb295 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5167 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is used to forward the host IDR values to the user space, so the hypervisor and the guest VM can learn about the underlying hardware's capabilities. Also, set the driver_type to IOMMU_HW_INFO_TYPE_ARM_SMMUV3 to pass the corresponding type sanity in the core. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ include/uapi/linux/iommufd.h | 14 ++++++++++++ 3 files changed, 41 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index f2425b0f0cd6..c1aac695ae0d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2005,6 +2005,29 @@ static bool arm_smmu_capable(struct device *dev, enu= m iommu_cap cap) } } =20 +static void *arm_smmu_hw_info(struct device *dev, u32 *length) +{ + struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + struct iommu_hw_info_smmuv3 *info; + void *base_idr; + int i; + + if (!master || !master->smmu) + return ERR_PTR(-ENODEV); + + info =3D kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); + + base_idr =3D master->smmu->base + ARM_SMMU_IDR0; + for (i =3D 0; i <=3D 5; i++) + info->idr[i] =3D readl_relaxed(base_idr + 0x4 * i); + + *length =3D sizeof(*info); + + return info; +} + static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) { struct arm_smmu_domain *smmu_domain; @@ -2845,6 +2868,7 @@ static void arm_smmu_remove_dev_pasid(struct device *= dev, ioasid_t pasid) =20 static struct iommu_ops arm_smmu_ops =3D { .capable =3D arm_smmu_capable, + .hw_info =3D arm_smmu_hw_info, .domain_alloc =3D arm_smmu_domain_alloc, .probe_device =3D arm_smmu_probe_device, .release_device =3D arm_smmu_release_device, @@ -2857,6 +2881,7 @@ static struct iommu_ops arm_smmu_ops =3D { .page_response =3D arm_smmu_page_response, .def_domain_type =3D arm_smmu_def_domain_type, .pgsize_bitmap =3D -1UL, /* Restricted during device attach */ + .driver_type =3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3, .owner =3D THIS_MODULE, .default_domain_ops =3D &(const struct iommu_domain_ops) { .attach_dev =3D arm_smmu_attach_dev, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 8d772ea8a583..ba2b4562f4b2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -14,6 +14,8 @@ #include #include =20 +#include + /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 #define IDR0_ST_LVL GENMASK(28, 27) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 0d5551b1b2be..c7a37915b49c 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -519,6 +519,20 @@ struct iommu_hw_info_vtd { __aligned_u64 ecap_reg; }; =20 +/** + * struct iommu_hw_info_smmuv3 - ARM SMMUv3 device info + * + * @flags: Must be set to 0 + * @__reserved: Must be 0 + * @idr: Implemented features for the SMMU Non-secure programming interfac= e. + * Please refer to the chapters from 6.3.1 to 6.3.6 in the SMMUv3 Sp= ec. + */ +struct iommu_hw_info_smmuv3 { + __u32 flags; + __u32 __reserved; + __u32 idr[6]; +}; + /** * struct iommu_hw_info - ioctl(IOMMU_DEVICE_GET_HW_INFO) * @size: sizeof(struct iommu_hw_info) --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E606EC61DA4 for ; Thu, 9 Mar 2023 10:55:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231236AbjCIKzT (ORCPT ); Thu, 9 Mar 2023 05:55:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231154AbjCIKyy (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:46.9315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df00ed52-7200-42a6-deee-08db208cb2d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5748 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" IOMMUFD designs two iommu_domain pointers to represent two stages. The S1 iommu_domain (IOMMU_DOMAIN_NESTED type) represents the Context Descriptor table in the user space. The S2 iommu_domain (IOMMU_DOMAIN_UNMANAGED type) represents the translation table in the kernel, owned by a hypervisor. So there comes to no use case of the ARM_SMMU_DOMAIN_NESTED. Drop it, and use the type IOMMU_DOMAIN_NESTED instead. Also drop the unused arm_smmu_enable_nesting(). One following patche will configure the correct smmu_domain->stage. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 ------------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 - 2 files changed, 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c1aac695ae0d..c5616145e2a3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1279,7 +1279,6 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, s1_cfg =3D &smmu_domain->s1_cfg; break; case ARM_SMMU_DOMAIN_S2: - case ARM_SMMU_DOMAIN_NESTED: s2_cfg =3D &smmu_domain->s2_cfg; break; default: @@ -2220,7 +2219,6 @@ static int arm_smmu_domain_finalise(struct iommu_doma= in *domain, fmt =3D ARM_64_LPAE_S1; finalise_stage_fn =3D arm_smmu_domain_finalise_s1; break; - case ARM_SMMU_DOMAIN_NESTED: case ARM_SMMU_DOMAIN_S2: ias =3D smmu->ias; oas =3D smmu->oas; @@ -2747,21 +2745,6 @@ static struct iommu_group *arm_smmu_device_group(str= uct device *dev) return group; } =20 -static int arm_smmu_enable_nesting(struct iommu_domain *domain) -{ - struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); - int ret =3D 0; - - mutex_lock(&smmu_domain->init_mutex); - if (smmu_domain->smmu) - ret =3D -EPERM; - else - smmu_domain->stage =3D ARM_SMMU_DOMAIN_NESTED; - mutex_unlock(&smmu_domain->init_mutex); - - return ret; -} - static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *a= rgs) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -2890,7 +2873,6 @@ static struct iommu_ops arm_smmu_ops =3D { .flush_iotlb_all =3D arm_smmu_flush_iotlb_all, .iotlb_sync =3D arm_smmu_iotlb_sync, .iova_to_phys =3D arm_smmu_iova_to_phys, - .enable_nesting =3D arm_smmu_enable_nesting, .free =3D arm_smmu_domain_free, } }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ba2b4562f4b2..233bfc377267 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -704,7 +704,6 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 =3D 0, ARM_SMMU_DOMAIN_S2, - ARM_SMMU_DOMAIN_NESTED, ARM_SMMU_DOMAIN_BYPASS, }; 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Thu, 9 Mar 2023 02:54:37 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Date: Thu, 9 Mar 2023 02:53:42 -0800 Message-ID: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|SN7PR12MB6888:EE_ X-MS-Office365-Filtering-Correlation-Id: 5644ae0f-0c37-4b76-806d-08db208cb3af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hCS2MVoNx7iiFq1hrtdJt5LXJe8GoliRz9heG1xcNnoKSXNoajM2uCCXRkdsXeHOciR9DJOnU6E75GULglV/JOx3EXXA2+Q+G9+uoh0Ns01RVEgxKyNgFSPC1e/nbrm2LPfPKpK8yx+bOfSWJk09F2BxlTO9CZoAH8BqogjM/oSCpOouztKYsXf79jHWd3ho3txQyLa12nps332akDqoDQJgQ2zMYxSQFWjmt+K+xow2PhefTaei0D/730B1sBbXq8M32DE62pSEOAr738hkBtSG2st7VFdeAvpUJ1fTsPT/KG4pIMaYgM8seGN35R1eX+61d5rIobGINtoYIDNEsnm321SMvWTmLMnFlK0CclQvXt6k5bKs9L+TQFB6+nrgeqPQ2TMliXzJx56Dw6wuUBRcAecCmKQXX/OZpc5B5nY0OSb440VgtygWJLmvAp2nFPsc9Fg/q6M49AqHehatHsuXahxnqUyQlIdnityulCAONi+ulVCFoMegO5tItUzwpIL9wFC1CRNm28iTEZe4YPjXdhwPHPj8tBKppPd8DrYzvll9UoSO1WDV2fEnL2FC9Yr99urZRkCXURkxLW0ihlojn8BvQ/K803CWZDQFqpzSnB21VTzdKaLgSIHmMewpuSyQwBwKRsV01BZJVBkWq+z4SQT9irBsRgwUkkDeq+W8i3n4PG9hPpA6fpzPU36Cv3/MNwArq+7gJsDDYvUXxiAI40lNC79jE/N1icCmb7VOMFVmv0+V7c8yR4UGD7q5 X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199018)(46966006)(36840700001)(40470700004)(82740400003)(7696005)(36860700001)(186003)(36756003)(478600001)(7636003)(356005)(54906003)(110136005)(86362001)(316002)(82310400005)(336012)(26005)(47076005)(426003)(41300700001)(2616005)(40460700003)(6666004)(5660300002)(7416002)(70206006)(70586007)(40480700001)(8936002)(2906002)(4326008)(8676002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:48.3315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5644ae0f-0c37-4b76-806d-08db208cb3af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6888 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Eric Auger Despite the spec does not seem to mention this, on some implementations, when the STE configuration switches from an S1+S2 cfg to an S1 only one, a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. Explicitly reset those two higher 64b fields, to prevent that. Note that this is not a bug at this moment, since a 2-stage translation setup is not yet enabled, until the following patches add its support. Reported-by: Shameer Kolothum Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index c5616145e2a3..29e36448d23b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1361,6 +1361,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, dst[3] =3D cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); =20 val |=3D FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); + } else { + dst[2] =3D 0; + dst[3] =3D 0; } =20 if (master->ats_enabled) --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 326D9C61DA4 for ; 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Thu, 9 Mar 2023 02:54:38 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 07/14] iommu/arm-smmu-v3: Add STRTAB_STE_0_CFG_NESTED for 2-stage translation Date: Thu, 9 Mar 2023 02:53:43 -0800 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D1:EE_|SA1PR12MB8966:EE_ X-MS-Office365-Filtering-Correlation-Id: 3059bac4-fc4b-462c-cc6d-08db208cb4aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kue/I/zPYOFUNsRCFVYTSRqIRXUz/Ww9zwHYpJS+lnMgHHFI5eAAFu3BbI1fGHPxqxUfD2PHi+Gl4VycREV4HBYaqU/zvc29M4ga3OqkM98WWqBFyEcTxwi4dfT7swbkbwTmbhI3YaXyEgCBH5Gtny/z9qdODMoBr09OLokGcUDJgi54ZFx+prv2i52KCzY2UMtkslOcRFtAjI139EqH+NtTa0rJxdwdVLmDn0wib0o2ZGE7ibfKVxZCBBCtx23m/EOkdZbpMz2zrRGJPcefcwNrUpAPhrNMnFy8QDY2fhUtPVgk64bZBeiue969orW0tRBQC6xIiuHjIv/x0Ypuh+uhPhm5HqZawNU2om8WepepOcoTUMGrLjIkKNZbA3YnoebSQ7p6N1KiNxmEHGdGS0sZqJxRF4tQTusT4jLHb2f2GiL6vdFBnwoRfNT7EQvvE2s3IzWg+g7nwLYtSibKqCUnH3l/7qgdTnW9Kd+R1P8JCeAON2kx2qvMpVmdcMCiKCrZ1OP/qsqtSvyTiqayPMvXzWP3tDTyt5kZ8StKbekkEZxer29SuO/5ku1tzD2+vM03CdCg96LvwJHU9C6i3JEnXAg1TqwW81N+wtY26ye5J0jCm9SzB0itDLz8x0a3yJC25KunTR8PwQDHrnyfz65gz1Q1g91Aikuxkm/OJMz/1d/sSklgGrTktunfRKPkM+8lgIlxh4inV8R7kEt7BGxfBw8+tSo7JM2LOPagf7ti7o1VTklh5KuTeaLZEviE X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(396003)(346002)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(7636003)(2906002)(186003)(5660300002)(8936002)(36860700001)(41300700001)(7416002)(82740400003)(2616005)(26005)(86362001)(70206006)(70586007)(82310400005)(4326008)(6666004)(336012)(316002)(426003)(7696005)(110136005)(478600001)(8676002)(47076005)(36756003)(356005)(40480700001)(54906003)(40460700003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:49.9784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3059bac4-fc4b-462c-cc6d-08db208cb4aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8966 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Eric Auger The value of the STRTAB_STE_0_CFG field can be 0b111 as the configuration for a 2-stage translation, meaning that both S1 and S2 are valid. Add it and mark the ste_live accordingly. Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 29e36448d23b..21d819979865 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1292,6 +1292,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, break; case STRTAB_STE_0_CFG_S1_TRANS: case STRTAB_STE_0_CFG_S2_TRANS: + case STRTAB_STE_0_CFG_NESTED: ste_live =3D true; break; case STRTAB_STE_0_CFG_ABORT: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 233bfc377267..1a93eeb993ea 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -208,6 +208,7 @@ #define STRTAB_STE_0_CFG_BYPASS 4 #define STRTAB_STE_0_CFG_S1_TRANS 5 #define STRTAB_STE_0_CFG_S2_TRANS 6 +#define STRTAB_STE_0_CFG_NESTED 7 =20 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1BA9C61DA4 for ; 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Thu, 9 Mar 2023 02:54:39 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 08/14] iommu/arm-smmu-v3: Prepare for nested domain support Date: Thu, 9 Mar 2023 02:53:44 -0800 Message-ID: <4740f8a40caf68ccc1f9fee5fcdf1604546fb354.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E8:EE_|CY5PR12MB6154:EE_ X-MS-Office365-Filtering-Correlation-Id: be2ff6f0-63a3-4ba8-619f-08db208cb3b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VwPJdVdK50NWl1RQoHrKWqqf96pSzR8xjQ48o18mSHVZ4HZcoKUGxqVbunfw/vAOovtQ2p6wHj1OdbI4tSJRVDhLKjaN5FQVVt2vJ8ogoNE5y0FeDSv9PxVPU6o6kxb0KDvAmrtDrDKiOe2lS7nvnDPbffeqcbRlURkjYQXnemgIBzQ5hc+3tzpcL+3x90frnBGRdaF9xB67djRLxborrzw5o4AP5KnDx5UhMuVRcoqfzUlEQ+OIjx07XwHxPXYPVIqf/uYxQCD/6LBjUd6pJChLfDh6CvdDrJfceIUibwHJPudhqm7bTbfmG+JUUEggegLpoJs1VaLBoVXrEUqECaJqfyjfwQpuul3nEAKKVzpynVSeL9PQmkcc00Rk51byT9Z+3u1IzqQhgR3dj3fAe8THjf55ofTm+V7aoEHnts9u7o14jewCrOXJPkmYD2aumxfEE6RseHe7a26Js+7J8F9JEI1dA+BPDYvPselkJ0eyfYfearqjUIIHjRo7NBRRslyq+TwovftWdFLueBsbghRx+9zMSYOq3muI/O6AHuy0KKQuao+kPfEGWLcIZYAy36uqfrN2vc2eqwHl/gNZFIJKgU+1/5wSnTUPtiG6fNLvqGMDMsXeZ4GUYbj3CKCGZxilWEhlBVb2JKQehO5CBfd/3EM9XM1qWSRklDbc4b2yvppyTV2P0XfcrjAL5nQCqNes7c/BR/I3IaPevTQ/yEpA7KkDItvyo4GgMucoqGjchL72WUh6tAeAPBebv83o X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199018)(36840700001)(46966006)(40470700004)(36756003)(82740400003)(83380400001)(47076005)(426003)(36860700001)(186003)(26005)(6666004)(2616005)(7696005)(336012)(41300700001)(40460700003)(8936002)(70206006)(70586007)(86362001)(8676002)(2906002)(4326008)(7416002)(5660300002)(356005)(7636003)(316002)(40480700001)(478600001)(54906003)(110136005)(82310400005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:48.3569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be2ff6f0-63a3-4ba8-619f-08db208cb3b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6154 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In a nested translation setup, the device is attached to a stage-1 domain that represents the guest-level Context Descriptor table. A Stream Table Entry for a 2-stage translation needs both the stage-1 Context Descriptor table info and the stage-2 Translation table information, i.e. a pair of s1_cfg and s2_cfg. Add an "s2" pointer in struct arm_smmu_domain, so a nested stage-1 domain can simply navigate its stage-2 domain for the s2_cfg pointer. Also, add a to_s2_cfg() helper for this purpose, and use it at proper places. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 +++++++++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 21d819979865..fee5977feef3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -100,6 +100,24 @@ static void parse_driver_options(struct arm_smmu_devic= e *smmu) } while (arm_smmu_options[++i].opt); } =20 +static struct arm_smmu_s2_cfg *to_s2_cfg(struct arm_smmu_domain *smmu_doma= in) +{ + if (!smmu_domain) + return NULL; + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_S1: + if (smmu_domain->s2) + return &smmu_domain->s2->s2_cfg; + return NULL; + case ARM_SMMU_DOMAIN_S2: + return &smmu_domain->s2_cfg; + case ARM_SMMU_DOMAIN_BYPASS: + default: + return NULL; + } +} + /* Low-level queue manipulation functions */ static bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n) { @@ -1277,6 +1295,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu= _master *master, u32 sid, switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: s1_cfg =3D &smmu_domain->s1_cfg; + s2_cfg =3D to_s2_cfg(smmu_domain); break; case ARM_SMMU_DOMAIN_S2: s2_cfg =3D &smmu_domain->s2_cfg; @@ -1846,6 +1865,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *s= mmu_domain, int ssid, static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain =3D cookie; + struct arm_smmu_s2_cfg *s2_cfg =3D to_s2_cfg(smmu_domain); struct arm_smmu_device *smmu =3D smmu_domain->smmu; struct arm_smmu_cmdq_ent cmd; =20 @@ -1860,7 +1880,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); } else { cmd.opcode =3D CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; + cmd.tlbi.vmid =3D s2_cfg->vmid; arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0); @@ -1931,6 +1951,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, size_t granule, bool leaf, struct arm_smmu_domain *smmu_domain) { + struct arm_smmu_s2_cfg *s2_cfg =3D to_s2_cfg(smmu_domain); struct arm_smmu_cmdq_ent cmd =3D { .tlbi =3D { .leaf =3D leaf, @@ -1943,7 +1964,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned lo= ng iova, size_t size, cmd.tlbi.asid =3D smmu_domain->s1_cfg.cd.asid; } else { cmd.opcode =3D CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid =3D smmu_domain->s2_cfg.vmid; + cmd.tlbi.vmid =3D s2_cfg->vmid; } __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); =20 diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 1a93eeb993ea..6cf516852721 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -709,6 +709,7 @@ enum arm_smmu_domain_stage { }; =20 struct arm_smmu_domain { + struct arm_smmu_domain *s2; struct arm_smmu_device *smmu; struct mutex init_mutex; /* Protects smmu pointer */ =20 --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BA50C64EC4 for ; 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Thu, 9 Mar 2023 02:54:39 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 09/14] iommu/arm-smmu-v3: Implement arm_smmu_get_unmanaged_domain Date: Thu, 9 Mar 2023 02:53:45 -0800 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E8:EE_|DM8PR12MB5495:EE_ X-MS-Office365-Filtering-Correlation-Id: 47f1d7c0-8736-4fbf-1a93-08db208cb4b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0/u6jxisrhtQWdzb5C8FpfgPCfK5IlQ5JYljqF2Stp1f+qwWkYejuu462BzXW6v/gjZYt2G3PictpGK4QkJGCKn04gUVLohRLnajLwf6dizWgojlodkApPXVVFaAfOTWj8G6r0HFK48G+SlH3l9EpBPRzE8odJX6AMXAI68gOtDWmp4PytbbxtPN/IachK/Qh7gdt6D5BwpT2E89RIaE7Ti7tvkDKuIfedua9berQlVinHmoHR5/RquQI0iRf39+5cgCuLsEcn0lNkXpVn3+5IPiKXyJnRDgiGFGexEhIFahV/ZEQFo5XPVVZDz2DCll7nl3HtnUBh9YwJkxB1aaZ2THTSZ9MuvsfEJ6d7ttvRg6CxrF34TAwQKRrdAfu8WfM27tg/6z2bP6v1s/Mk+UnTwyQVpG5S70GgWFzQOaD/kJKdVecWeScI6WK+eNjXI+32LTZsQLTuECAER9f/i121uzuvW3g+jUGKARl6BmPEkxg7LfvCM75hg9hDNRrBUFryui/YcICvBrm0f3BI7LbODKF04Z4/EqyN2yOEJy/lmpveuRJ3FcPpS3OswG78zsU4MTs3hkZlJOfkSAMFLH0l5Q2blNA9CxvGDAOPW+1S3LOEXPHm2JzXNABZlY3/hN3OqTYvXLEDr1ttDG/OzA2htFjbEb9Vl60gpWDGzrzTno9nkKbOg9RHXtVWSNBW/R45azLsbu14ZdcUi2hzCD68Kvr24F13Zasi1QOBmcFtHyg+kUiewdUYrEdpLWuWNm X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(136003)(39860400002)(346002)(376002)(396003)(451199018)(46966006)(40470700004)(36840700001)(2906002)(7416002)(5660300002)(26005)(8676002)(8936002)(36756003)(41300700001)(70206006)(4326008)(70586007)(40460700003)(110136005)(40480700001)(316002)(86362001)(54906003)(356005)(7696005)(478600001)(7636003)(6666004)(82740400003)(36860700001)(186003)(2616005)(82310400005)(47076005)(336012)(426003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:50.0132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47f1d7c0-8736-4fbf-1a93-08db208cb4b0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5495 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In a 1-stage translation setup, a device is attached to an iommu_domain (ARM_SMMU_DOMAIN_S1) that is IOMMU_DOMAIN_UNMANAGED type. In a 2-stage translation setup, a device is attached to an iommu_domain (ARM_SMMU_DOMAIN_S1) that is IOMMU_DOMAIN_NESTED type, which must have a valid "s2" pointer for an iommu_domain (ARM_SMMU_DOMAIN_S2) that is IOMMU_DOMAIN_UNMANAGED type. Add a function to return the correct iommu_domain pointer accordingly. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index fee5977feef3..18ab5d516cf2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2082,6 +2082,17 @@ static struct iommu_domain *arm_smmu_domain_alloc(un= signed type) return &smmu_domain->domain; } =20 +static struct iommu_domain *arm_smmu_get_unmanaged_domain(struct device *d= ev) +{ + struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + struct arm_smmu_domain *smmu_domain =3D master->domain; + + if (smmu_domain->s2) + return &smmu_domain->s2->domain; + + return &smmu_domain->domain; +} + static int arm_smmu_bitmap_alloc(unsigned long *map, int span) { int idx, size =3D 1 << span; @@ -2878,6 +2889,7 @@ static struct iommu_ops arm_smmu_ops =3D { .capable =3D arm_smmu_capable, .hw_info =3D arm_smmu_hw_info, .domain_alloc =3D arm_smmu_domain_alloc, + .get_unmanaged_domain =3D arm_smmu_get_unmanaged_domain, .probe_device =3D arm_smmu_probe_device, .release_device =3D arm_smmu_release_device, .device_group =3D arm_smmu_device_group, --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94450C64EC4 for ; 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Thu, 9 Mar 2023 02:54:40 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 10/14] iommu/arm-smmu-v3: Pass in user_cfg to arm_smmu_domain_finalise Date: Thu, 9 Mar 2023 02:53:46 -0800 Message-ID: <118863752be19884bfe9c2f7384f9ad19a1c2083.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D1:EE_|DS0PR12MB8365:EE_ X-MS-Office365-Filtering-Correlation-Id: c4cdb2f8-ec02-4917-2953-08db208cb6ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yChfbPS2e+FBgyjNUxLqFnlDC4iPzyZH2jdhvVTIMNsJ4bDL9i+OSD+f5dSBwFp7XIfzkPum2wCU0e+U2zzY0S7JbAEckKuI6NLJYqhzUXDffcy1IC3sFtn6+yZJahE92HcFXJARL9pL9WZpSP6wM8kesC99DRh5V2IMhGxJ9dUnMMzqv+t/UVNf8q+I5fLKeWdeH7kwmMI01Gd/qtrFQOQfw06lVeis0Jv3hb72LFcWSNxctOYWLTb98EpcLsehqdsvdf9hcBD6u9rvNOuwQMNjqrYCLcW9XWdBhquOh/BnIWeZ0C9TfIcbCaWaIUsCkLVju1wuJOHdmJroc1ogMUlW/H56IM5HLYC1TULQJiq+rqzSdliXJD69Z6y1cVo9cIfpCASk4bssyqQvU6U6QbLbhEC2aXJVF9FPdsGrxJS8n0EOn5ev4OL05p5UgJSgancmNX9Wa5asWSPsLWnubaDp6EyWeHoME6iwZGhMgjiuKdIEtBCPzZkY5tDA6Isv5yBDJDZdR347PVjj69f78RQsR/I/0xT4DjR9wnU9bckf/p2shlfme++2V/YlhQrByKdD6GHAuF/wGq/dhfuEOMOZHQMwA8tq2EKvypX6c8HqbvJctIdqt96QQJ6QrZ+CBM/LCnxcM71NQ6wBM76LokpeHnDQcva+NKzOyarNp6ZLe6/n5VrH9P4PYl21eUqVDGURwyYEjngzqi+MiVt3LUCGYpo3S9EXpTRFBSzyrF8baqbUGii1mehcPkR9kUk/ X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199018)(46966006)(40470700004)(36840700001)(70586007)(70206006)(36860700001)(316002)(47076005)(41300700001)(83380400001)(8676002)(4326008)(426003)(7636003)(36756003)(54906003)(110136005)(336012)(82740400003)(2906002)(356005)(5660300002)(40460700003)(2616005)(7416002)(478600001)(7696005)(82310400005)(8936002)(186003)(86362001)(26005)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:53.7753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4cdb2f8-ec02-4917-2953-08db208cb6ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8365 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The struct iommu_hwpt_arm_smmuv3 contains the userspace Stream Table Entry info (for ARM_SMMU_DOMAIN_S1) and an "S2" flag (for ARM_SMMU_DOMAIN_S2). Pass in a valid user_cfg pointer, so arm_smmu_domain_finalise() can handle both types of user domain finalizations. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 18ab5d516cf2..2d29f7320570 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,6 +26,7 @@ #include #include #include +#include =20 #include "arm-smmu-v3.h" #include "../../dma-iommu.h" @@ -2223,7 +2224,8 @@ static int arm_smmu_domain_finalise_s2(struct arm_smm= u_domain *smmu_domain, } =20 static int arm_smmu_domain_finalise(struct iommu_domain *domain, - struct arm_smmu_master *master) + struct arm_smmu_master *master, + const struct iommu_hwpt_arm_smmuv3 *user_cfg) { int ret; unsigned long ias, oas; @@ -2235,12 +2237,18 @@ static int arm_smmu_domain_finalise(struct iommu_do= main *domain, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_device *smmu =3D smmu_domain->smmu; + bool user_cfg_s2 =3D user_cfg && (user_cfg->flags & IOMMU_SMMUV3_FLAG_S2); =20 if (domain->type =3D=3D IOMMU_DOMAIN_IDENTITY) { smmu_domain->stage =3D ARM_SMMU_DOMAIN_BYPASS; return 0; } =20 + if (user_cfg_s2 && !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + return -EINVAL; + if (user_cfg_s2) + smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; + /* Restrict the stage to what we can actually support */ if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) smmu_domain->stage =3D ARM_SMMU_DOMAIN_S2; @@ -2484,7 +2492,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) =20 if (!smmu_domain->smmu) { smmu_domain->smmu =3D smmu; - ret =3D arm_smmu_domain_finalise(domain, master); + ret =3D arm_smmu_domain_finalise(domain, master, NULL); if (ret) { smmu_domain->smmu =3D NULL; goto out_unlock; --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C211C64EC4 for ; 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Thu, 9 Mar 2023 02:54:41 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 11/14] iommu/arm-smmu-v3: Add arm_smmu_domain_alloc_user Date: Thu, 9 Mar 2023 02:53:47 -0800 Message-ID: <7d26e897780bdc009b11bc0c0ddc7b755a769b24.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E8:EE_|DM4PR12MB6422:EE_ X-MS-Office365-Filtering-Correlation-Id: 753e7895-e0be-4266-bcd3-08db208cb5f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: l2FPmZkq0+MOofBck0p2ZGL7tAgDXMSpmyCbI9rasYvCbwYgXB874UI7yMCR147hCdbXg6aC9ddCMdLczxh3dWJhnR30A84C01jX7DfmVha5bsaxxmiC24Jj1QchpHeXwZD474DMpLpSfuD3lwhgedIjfuk3NeIuPvOyBtHBB+O1TUmPfJI63wwz0YwMvRlQeRH0sHgyFaa+rFw+1RRtYfoJ9fO+E6D3mQoajMtK3sUZyF8PMCVMJr9Oxwi98NrBdmVNec5YxE9Gkp22mrDMNAVx9D3WaCcsOVRiIemBtcXcGJgN9OnuheW4IQCnX0qtukcPfW2I3WWW6DFqAlUDOLCSNR4fWzJAOKptBcWOGgaP8okyIN1/qlGT5OHnBGs+5sn5tZEAd381rQ+UqeydJ6lvgV6ZLG29U3ydwwZVIzLDt+5a+5XN5uoK+EAzl08ZdGoAI1Vtzysu4QchYC4CfbnBEmbovb0n3rnkI54QKkCxGFez0ogqMQvQuYfnrX8UMhin6V3vTjxjSipjhkSA9396F1TU4uIPblof0XguVoT+NG4targ2k8WMMwkmRbAoRb4P/iet8ZzAlb4eCXIr5Jt3Gub6vKLGH5qU1mew2GpwRbduutxzei95jRLCVRlysqpFkwm5pAwoGFf3+Lu0dzbYqOTD7oQ+6TcAXHYxvgEj7R816NjMf/8G/IJa2mYIIyubb/fJv+UWF/co9phK+Z8o76kP/d/J9IzZz4ISE6t46ZN1niOrs4iq7EMNwvMv X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199018)(40470700004)(46966006)(36840700001)(2906002)(7416002)(8936002)(5660300002)(336012)(47076005)(70586007)(41300700001)(426003)(86362001)(7696005)(316002)(70206006)(36756003)(40460700003)(110136005)(40480700001)(54906003)(8676002)(4326008)(83380400001)(7636003)(2616005)(186003)(26005)(36860700001)(356005)(82310400005)(82740400003)(478600001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:52.1382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 753e7895-e0be-4266-bcd3-08db208cb5f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6422 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The arm_smmu_domain_alloc_user callback function is used for userspace to allocate iommu_domains, such as standalone stage-1 domain, nested stage-1 domain, and nested stage-2 domain. The input user_data is in the type of struct iommu_hwpt_arm_smmuv3 that contains the configurations of a nested stage-1 or a nested stage-2 iommu_domain. A NULL user_data will just opt in a standalone stage-1 domain allocation. Add a constitutive function __arm_smmu_domain_alloc to support that. Since ops->domain_alloc_user has a valid dev pointer, the master pointer is available when calling __arm_smmu_domain_alloc() in this case, meaning that arm_smmu_domain_finalise() can be done at the allocation stage. This allows IOMMUFD to initialize the hw_pagetable for the domain. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 95 ++++++++++++++------- 1 file changed, 65 insertions(+), 30 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 2d29f7320570..5ff74edfbd68 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2053,36 +2053,6 @@ static void *arm_smmu_hw_info(struct device *dev, u3= 2 *length) return info; } =20 -static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) -{ - struct arm_smmu_domain *smmu_domain; - - if (type =3D=3D IOMMU_DOMAIN_SVA) - return arm_smmu_sva_domain_alloc(); - - if (type !=3D IOMMU_DOMAIN_UNMANAGED && - type !=3D IOMMU_DOMAIN_DMA && - type !=3D IOMMU_DOMAIN_DMA_FQ && - type !=3D IOMMU_DOMAIN_IDENTITY) - return NULL; - - /* - * Allocate the domain and initialise some of its data structures. - * We can't really do anything meaningful until we've added a - * master. - */ - smmu_domain =3D kzalloc(sizeof(*smmu_domain), GFP_KERNEL); - if (!smmu_domain) - return NULL; - - mutex_init(&smmu_domain->init_mutex); - INIT_LIST_HEAD(&smmu_domain->devices); - spin_lock_init(&smmu_domain->devices_lock); - INIT_LIST_HEAD(&smmu_domain->mmu_notifiers); - - return &smmu_domain->domain; -} - static struct iommu_domain *arm_smmu_get_unmanaged_domain(struct device *d= ev) { struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); @@ -2893,10 +2863,75 @@ static void arm_smmu_remove_dev_pasid(struct device= *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } =20 +static struct iommu_domain * +__arm_smmu_domain_alloc(unsigned type, + struct arm_smmu_domain *s2, + struct arm_smmu_master *master, + const struct iommu_hwpt_arm_smmuv3 *user_cfg) +{ + struct arm_smmu_domain *smmu_domain; + struct iommu_domain *domain; + int ret =3D 0; + + if (type =3D=3D IOMMU_DOMAIN_SVA) + return arm_smmu_sva_domain_alloc(); + + if (type !=3D IOMMU_DOMAIN_UNMANAGED && + type !=3D IOMMU_DOMAIN_DMA && + type !=3D IOMMU_DOMAIN_DMA_FQ && + type !=3D IOMMU_DOMAIN_IDENTITY) + return NULL; + + /* + * Allocate the domain and initialise some of its data structures. + * We can't really finalise the domain unless a master is given. + */ + smmu_domain =3D kzalloc(sizeof(*smmu_domain), GFP_KERNEL); + if (!smmu_domain) + return NULL; + domain =3D &smmu_domain->domain; + + domain->type =3D type; + domain->ops =3D arm_smmu_ops.default_domain_ops; + + mutex_init(&smmu_domain->init_mutex); + INIT_LIST_HEAD(&smmu_domain->devices); + spin_lock_init(&smmu_domain->devices_lock); + INIT_LIST_HEAD(&smmu_domain->mmu_notifiers); + + if (master) { + smmu_domain->smmu =3D master->smmu; + ret =3D arm_smmu_domain_finalise(domain, master, user_cfg); + if (ret) { + kfree(smmu_domain); + return NULL; + } + } + + return domain; +} + +static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) +{ + return __arm_smmu_domain_alloc(type, NULL, NULL, NULL); +} + +static struct iommu_domain * +arm_smmu_domain_alloc_user(struct device *dev, struct iommu_domain *parent, + const void *user_data) +{ + const struct iommu_hwpt_arm_smmuv3 *user_cfg =3D user_data; + struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + unsigned type =3D IOMMU_DOMAIN_UNMANAGED; + + return __arm_smmu_domain_alloc(type, NULL, master, user_cfg); +} + static struct iommu_ops arm_smmu_ops =3D { .capable =3D arm_smmu_capable, .hw_info =3D arm_smmu_hw_info, .domain_alloc =3D arm_smmu_domain_alloc, + .domain_alloc_user =3D arm_smmu_domain_alloc_user, .get_unmanaged_domain =3D arm_smmu_get_unmanaged_domain, .probe_device =3D arm_smmu_probe_device, .release_device =3D arm_smmu_release_device, --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 350A6C61DA4 for ; Thu, 9 Mar 2023 10:55:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbjCIKz4 (ORCPT ); Thu, 9 Mar 2023 05:55:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231128AbjCIKzC (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:53.6243 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e658049-009d-4d57-8189-08db208cb6d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5836 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add domain allocation support for IOMMU_DOMAIN_NESTED type. This includes the "finalise" part to log in the user space Stream Table Entry info. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 38 +++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 5ff74edfbd68..1f318b5e0921 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2214,6 +2214,19 @@ static int arm_smmu_domain_finalise(struct iommu_dom= ain *domain, return 0; } =20 + if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) { + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) { + dev_dbg(smmu->dev, "does not implement two stages\n"); + return -EINVAL; + } + smmu_domain->stage =3D ARM_SMMU_DOMAIN_S1; + smmu_domain->s1_cfg.s1fmt =3D user_cfg->s1fmt; + smmu_domain->s1_cfg.s1cdmax =3D user_cfg->s1cdmax; + smmu_domain->s1_cfg.cdcfg.cdtab_dma =3D user_cfg->s1ctxptr; + return 0; + } + if (user_cfg_s2 && !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) return -EINVAL; if (user_cfg_s2) @@ -2863,6 +2876,11 @@ static void arm_smmu_remove_dev_pasid(struct device = *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } =20 +static const struct iommu_domain_ops arm_smmu_nested_domain_ops =3D { + .attach_dev =3D arm_smmu_attach_dev, + .free =3D arm_smmu_domain_free, +}; + static struct iommu_domain * __arm_smmu_domain_alloc(unsigned type, struct arm_smmu_domain *s2, @@ -2877,11 +2895,15 @@ __arm_smmu_domain_alloc(unsigned type, return arm_smmu_sva_domain_alloc(); =20 if (type !=3D IOMMU_DOMAIN_UNMANAGED && + type !=3D IOMMU_DOMAIN_NESTED && type !=3D IOMMU_DOMAIN_DMA && type !=3D IOMMU_DOMAIN_DMA_FQ && type !=3D IOMMU_DOMAIN_IDENTITY) return NULL; =20 + if (s2 && s2->stage !=3D ARM_SMMU_DOMAIN_S2) + return NULL; + /* * Allocate the domain and initialise some of its data structures. * We can't really finalise the domain unless a master is given. @@ -2889,10 +2911,14 @@ __arm_smmu_domain_alloc(unsigned type, smmu_domain =3D kzalloc(sizeof(*smmu_domain), GFP_KERNEL); if (!smmu_domain) return NULL; + smmu_domain->s2 =3D s2; domain =3D &smmu_domain->domain; =20 domain->type =3D type; - domain->ops =3D arm_smmu_ops.default_domain_ops; + if (s2) + domain->ops =3D &arm_smmu_nested_domain_ops; + else + domain->ops =3D arm_smmu_ops.default_domain_ops; =20 mutex_init(&smmu_domain->init_mutex); INIT_LIST_HEAD(&smmu_domain->devices); @@ -2923,8 +2949,16 @@ arm_smmu_domain_alloc_user(struct device *dev, struc= t iommu_domain *parent, const struct iommu_hwpt_arm_smmuv3 *user_cfg =3D user_data; struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); unsigned type =3D IOMMU_DOMAIN_UNMANAGED; + struct arm_smmu_domain *s2 =3D NULL; + + if (parent) { + if (parent->ops !=3D arm_smmu_ops.default_domain_ops) + return NULL; + type =3D IOMMU_DOMAIN_NESTED; + s2 =3D to_smmu_domain(parent); + } =20 - return __arm_smmu_domain_alloc(type, NULL, master, user_cfg); + return __arm_smmu_domain_alloc(type, s2, master, user_cfg); } =20 static struct iommu_ops arm_smmu_ops =3D { --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F6D1C64EC4 for ; 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Thu, 9 Mar 2023 02:54:43 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 13/14] iommu/arm-smmu-v3: Add CMDQ_OP_TLBI_NH_VAA and CMDQ_OP_TLBI_NH_ALL Date: Thu, 9 Mar 2023 02:53:49 -0800 Message-ID: <3b059f4b0bda1e83d402248114a774186f678387.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D1:EE_|DM6PR12MB4925:EE_ X-MS-Office365-Filtering-Correlation-Id: e29bf047-9f56-4d24-76e3-08db208cb8e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G60v53t1DrhomcTjc9JQINaiVEMjq537xZJbzQ3EcfLS1CEnnR0GT5f38KoE+t72ej4O7+cpEH9kn56O+Vrn3Cdt1Vptul0J/6iFoiwU0xH3dqx7HKvntgMKTOJ6kwupbGSGixUsREFzLFUl6BW+a4XSnTdwSotACUMRIfYcScTc6ReSBr0iKp/+jaVgnFJG9y57H2lm79PhHICwnBysQg+OTfu0VN7VJ93T+ZRsz6T+XRbadhEJw4nN5xJjbAMifs8ZlSp33Rz5cYbicHlKl1RDq5hCC4F7pXmfKVlVqSILwoyzfIgURRXXsYx9j/ylRpE37kpUUrzXnWtn9asQuQxYUYgGZqjFls/+K4hHPkK49575la/ispih/+85euskJwMojsyRD3/vd3H5ioTDx03yo9gX87JqVEVUR8hmD6F9HC01T6T6WsR8LJJaFVOGKaVhxZtjlSFSvPmledDSP7pPQPy4DAOT0JdINkcJOMKwfvBhfjc4U+unCM4pLo/KwepF/Isqkcr6zbg7reEXRIDtMv55D+yglYhrUzusqveUldJB4Zdn3FoHvwiWWZHVt04HQXLuZ8FEXBLS+EaCKKmZKNGpozx2bKrZxX65/7XTlwUy1Cvr0XURipHW1I1H2FvYZMg0QmJKh5HVxxCow3tw3Ch2PKD6OrJhP97LUNNECz2fu/WagOjCs2QaIuLPL9QWuddSPFjMyEIzv64vzjuM80qzzGr+IQWOdbHzpL4jyjKP+x/2Jfr3NtvzyN5Y X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230025)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199018)(40470700004)(36840700001)(46966006)(356005)(186003)(336012)(2906002)(82740400003)(26005)(2616005)(7636003)(5660300002)(36860700001)(7416002)(8936002)(41300700001)(82310400005)(110136005)(47076005)(86362001)(40460700003)(70586007)(8676002)(40480700001)(70206006)(4326008)(478600001)(426003)(316002)(7696005)(83380400001)(54906003)(36756003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:57.0410 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e29bf047-9f56-4d24-76e3-08db208cb8e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4925 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With a nested translation setup, a stage-1 Context Descriptor table can be managed by a guest OS in the user space. So, the kernel driver should not assume that the guest OS will use a user space device driver that doesn't support TLBI_NH_VAA and TLBI_NH_ALL commands. Add them in the arm_smmu_cmdq_build_cmd(), to prepare for support of these two TLBI invalidation requests from the guest level. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1f318b5e0921..ac63185ae268 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -277,6 +277,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm= _smmu_cmdq_ent *ent) /* Cover the entire SID range */ cmd[1] |=3D FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); break; + case CMDQ_OP_TLBI_NH_VAA: + ent->tlbi.asid =3D 0; + fallthrough; case CMDQ_OP_TLBI_NH_VA: cmd[0] |=3D FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); fallthrough; @@ -301,6 +304,7 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm= _smmu_cmdq_ent *ent) case CMDQ_OP_TLBI_NH_ASID: cmd[0] |=3D FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); fallthrough; + case CMDQ_OP_TLBI_NH_ALL: case CMDQ_OP_TLBI_S12_VMALL: cmd[0] |=3D FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); break; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 6cf516852721..6181d6cd8b51 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -454,8 +454,10 @@ struct arm_smmu_cmdq_ent { }; } cfgi; =20 + #define CMDQ_OP_TLBI_NH_ALL 0x10 #define CMDQ_OP_TLBI_NH_ASID 0x11 #define CMDQ_OP_TLBI_NH_VA 0x12 + #define CMDQ_OP_TLBI_NH_VAA 0x13 #define CMDQ_OP_TLBI_EL2_ALL 0x20 #define CMDQ_OP_TLBI_EL2_ASID 0x21 #define CMDQ_OP_TLBI_EL2_VA 0x22 --=20 2.39.2 From nobody Wed Sep 10 07:36:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DA7BC61DA4 for ; Thu, 9 Mar 2023 10:56:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230256AbjCIK4U (ORCPT ); Thu, 9 Mar 2023 05:56:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231216AbjCIKzS (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:57.4525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 707da11f-994c-464f-4114-08db208cb91f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4213 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add arm_smmu_cache_invalidate_user() function for user space to invalidate TLB entries and Context Descriptors, since either an IO page table entrie or a Context Descriptor in the user space is still cached by the hardware. The input user_data is defined in "struct iommu_hwpt_invalidate_arm_smmuv3" that contains the essential data for corresponding invalidation commands. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 56 +++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ac63185ae268..7d73eab5e7f4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2880,9 +2880,65 @@ static void arm_smmu_remove_dev_pasid(struct device = *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } =20 +static void arm_smmu_cache_invalidate_user(struct iommu_domain *domain, + void *user_data) +{ + struct iommu_hwpt_invalidate_arm_smmuv3 *inv_info =3D user_data; + struct arm_smmu_cmdq_ent cmd =3D { .opcode =3D inv_info->opcode }; + struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); + struct arm_smmu_device *smmu =3D smmu_domain->smmu; + size_t granule_size =3D inv_info->granule_size; + unsigned long iova =3D 0; + size_t size =3D 0; + int ssid =3D 0; + + if (!smmu || !smmu_domain->s2 || domain->type !=3D IOMMU_DOMAIN_NESTED) + return; + + switch (inv_info->opcode) { + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + return arm_smmu_sync_cd(smmu_domain, inv_info->ssid, true); + case CMDQ_OP_TLBI_NH_VA: + cmd.tlbi.asid =3D inv_info->asid; + fallthrough; + case CMDQ_OP_TLBI_NH_VAA: + if (!granule_size || !(granule_size & smmu->pgsize_bitmap) || + granule_size & ~(1ULL << __ffs(granule_size))) + return; + + iova =3D inv_info->range.start; + size =3D inv_info->range.last - inv_info->range.start + 1; + if (!size) + return; + + cmd.tlbi.vmid =3D smmu_domain->s2->s2_cfg.vmid; + cmd.tlbi.leaf =3D inv_info->flags & IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF; + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule_size, smmu_domain); + break; + case CMDQ_OP_TLBI_NH_ASID: + cmd.tlbi.asid =3D inv_info->asid; + fallthrough; + case CMDQ_OP_TLBI_NH_ALL: + cmd.tlbi.vmid =3D smmu_domain->s2->s2_cfg.vmid; + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + break; + case CMDQ_OP_ATC_INV: + ssid =3D inv_info->ssid; + iova =3D inv_info->range.start; + size =3D inv_info->range.last - inv_info->range.start + 1; + break; + default: + return; + } + + arm_smmu_atc_inv_domain(smmu_domain, ssid, iova, size); +} + static const struct iommu_domain_ops arm_smmu_nested_domain_ops =3D { .attach_dev =3D arm_smmu_attach_dev, .free =3D arm_smmu_domain_free, + .cache_invalidate_user =3D arm_smmu_cache_invalidate_user, }; =20 static struct iommu_domain * --=20 2.39.2