From nobody Fri Sep 12 23:55:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA366C61DA4 for ; Tue, 7 Feb 2023 02:10:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229957AbjBGCKA (ORCPT ); Mon, 6 Feb 2023 21:10:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbjBGCJz (ORCPT ); Mon, 6 Feb 2023 21:09:55 -0500 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2A5B2BF3A for ; Mon, 6 Feb 2023 18:09:53 -0800 (PST) Received: by mail-pg1-x52f.google.com with SMTP id r18so9489607pgr.12 for ; Mon, 06 Feb 2023 18:09:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QpoaSRADxtOzIb7bPjBbBJEJdeXVedb+PzOMYN8weXw=; b=FQEbiqUxyI8fQeaMTCTDwQf3T1Nu/FuItXg+Yk022rm0CsG/08xoalp/qHQToTgD5R 3BHlt5ItYP9ZtzHnUl2pkYJxBwK1B8RM476l/30Zas2wNH2cKcukRx3umW+or7m27DPy 4Y1QDEQpI/9vVr0zWrPiDZ0tXIYl4cHmYwP1AifY+ibaT6CbPEBV1NZOSKiNjFbk5HLx 9GJTemx4OMOl27aNyN6LKIfLIsPQfQBqVbc1lYtt4rRyTae2k7Eo/5APO55Cc1Etvnzx 21I7IAYHp9tojzBZTfd6Dn1RvuVSqnB6/ypbrIl4Nizq2PE6v9ZalHcpTE4M4e3/kers 2RhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QpoaSRADxtOzIb7bPjBbBJEJdeXVedb+PzOMYN8weXw=; b=Id23jTog2suzINQbnQ0SxYE6Bu1fdBYgyPkZZ3Ibnirp1/pXb63NGSv2njVPJIYwbE zxt+iOSTFsURCo0ikHsv/A7QpJUK5W8waBs1csuxFEeJQvdgtEo9ZPH152bB7YYxXk+7 w15bFqUefc6h0sP2kjZ0dwpfqgDGe2U6urT1xDW8IztZk0vf+evVZzcR4grpvrDDo2+8 zU6eqdusjSsB1DTT0+i1gWDMRmCQaSLz6O+b0Ct7W0vwYThIORgrI3WOSlUkZvstJMsY h0Tk2Rs0yB2yJ2YaSzPTA4YlZEWLQPd3f4bdIceiRivEfPZtU0QeYUh6rEqYApfDPxzQ 1GgA== X-Gm-Message-State: AO0yUKVW1n10x3m/Un0AiZjWOciwV7xN3CgRovi+BMDjjZbBxJdprj3N edf6+dUkxFsnfZwZ0r9U5uY= X-Google-Smtp-Source: AK7set/G5YL/cRNecJlI0OL5X9JU2dAif/RQpv7rVn7Jf1IZdM9rGPGLcauFF8rjhePoJiJZymLKRQ== X-Received: by 2002:aa7:9a0d:0:b0:593:b880:211f with SMTP id w13-20020aa79a0d000000b00593b880211fmr1547075pfj.26.1675735793385; Mon, 06 Feb 2023 18:09:53 -0800 (PST) Received: from localhost.localdomain ([112.20.108.204]) by smtp.gmail.com with ESMTPSA id d198-20020a621dcf000000b00593225b379dsm7843765pfd.106.2023.02.06.18.09.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Feb 2023 18:09:52 -0800 (PST) From: chris.chenfeiyang@gmail.com X-Google-Original-From: chenfeiyang@loongson.cn To: w@1wt.eu, paulmck@kernel.org Cc: Feiyang Chen , chenhuacai@kernel.org, jiaxun.yang@flygoat.com, arnd@arndb.de, chris.chenfeiyang@gmail.com, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] nolibc: Add statx() support to implement sys_stat() Date: Tue, 7 Feb 2023 10:09:40 +0800 Message-Id: <1af05c1441e9f96870be1cc20b1162e3f5043b2e.1675734681.git.chenfeiyang@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Feiyang Chen Neither __NR_newfstatat nor __NR_stat is defined on new architecture like LoongArch, but we can use statx() to implement sys_stat(). Signed-off-by: Feiyang Chen --- tools/include/nolibc/sys.h | 36 +++++++++++++++++++++++++--- tools/include/nolibc/types.h | 46 ++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 3 deletions(-) diff --git a/tools/include/nolibc/sys.h b/tools/include/nolibc/sys.h index b5f8cd35c03b..7ff9b401008a 100644 --- a/tools/include/nolibc/sys.h +++ b/tools/include/nolibc/sys.h @@ -1054,6 +1054,7 @@ pid_t setsid(void) * Warning: the struct stat's layout is arch-dependent. */ =20 +#if defined(__NR_newfstatat) || defined(__NR_stat) static __attribute__((unused)) int sys_stat(const char *path, struct stat *buf) { @@ -1063,10 +1064,8 @@ int sys_stat(const char *path, struct stat *buf) #ifdef __NR_newfstatat /* only solution for arm64 */ ret =3D my_syscall4(__NR_newfstatat, AT_FDCWD, path, &stat, 0); -#elif defined(__NR_stat) +#else /* __NR_stat */ ret =3D my_syscall2(__NR_stat, path, &stat); -#else -#error Neither __NR_newfstatat nor __NR_stat defined, cannot implement sys= _stat() #endif buf->st_dev =3D stat.st_dev; buf->st_ino =3D stat.st_ino; @@ -1083,6 +1082,37 @@ int sys_stat(const char *path, struct stat *buf) buf->st_ctime =3D stat.st_ctime; return ret; } +#elif defined(__NR_statx) +/* only solution for loongarch */ +static __attribute__((unused)) +int sys_stat(const char *path, struct stat *buf) +{ + struct statx statx; + long ret; + + ret =3D my_syscall5(__NR_statx, AT_FDCWD, path, 0, STATX_BASIC_STATS, &st= atx); + buf->st_dev =3D ((statx.stx_dev_minor & 0xff) + | (statx.stx_dev_major << 8) + | ((statx.stx_dev_minor & ~0xff) << 12)); + buf->st_ino =3D statx.stx_ino; + buf->st_mode =3D statx.stx_mode; + buf->st_nlink =3D statx.stx_nlink; + buf->st_uid =3D statx.stx_uid; + buf->st_gid =3D statx.stx_gid; + buf->st_rdev =3D ((statx.stx_rdev_minor & 0xff) + | (statx.stx_rdev_major << 8) | + ((statx.stx_rdev_minor & ~0xff) << 12)); + buf->st_size =3D statx.stx_size; + buf->st_blksize =3D statx.stx_blksize; + buf->st_blocks =3D statx.stx_blocks; + buf->st_atime =3D statx.stx_atime.tv_sec; + buf->st_mtime =3D statx.stx_mtime.tv_sec; + buf->st_ctime =3D statx.stx_ctime.tv_sec; + return ret; +} +#else +#error None of __NR_newfstatat, __NR_stat, nor __NR_statx defined, cannot = implement sys_stat() +#endif =20 static __attribute__((unused)) int stat(const char *path, struct stat *buf) diff --git a/tools/include/nolibc/types.h b/tools/include/nolibc/types.h index fbbc0e68c001..9b244af1ec2c 100644 --- a/tools/include/nolibc/types.h +++ b/tools/include/nolibc/types.h @@ -193,6 +193,52 @@ struct stat { time_t st_ctime; /* time of last status change */ }; =20 +/* for statx() */ +#ifndef STATX_BASIC_STATS +#define STATX_BASIC_STATS (0x000007ffU) +#endif + +struct statx_timestamp { + __s64 tv_sec; + __u32 tv_nsec; + __s32 __reserved; +}; + +struct statx { + /* 0x00 */ + __u32 stx_mask; /* What results were written [uncond] */ + __u32 stx_blksize; /* Preferred general I/O size [uncond] */ + __u64 stx_attributes; /* Flags conveying information about the file [unco= nd] */ + /* 0x10 */ + __u32 stx_nlink; /* Number of hard links */ + __u32 stx_uid; /* User ID of owner */ + __u32 stx_gid; /* Group ID of owner */ + __u16 stx_mode; /* File mode */ + __u16 __spare0[1]; + /* 0x20 */ + __u64 stx_ino; /* Inode number */ + __u64 stx_size; /* File size */ + __u64 stx_blocks; /* Number of 512-byte blocks allocated */ + __u64 stx_attributes_mask; /* Mask to show what's supported in stx_attrib= utes */ + /* 0x40 */ + struct statx_timestamp stx_atime; /* Last access time */ + struct statx_timestamp stx_btime; /* File creation time */ + struct statx_timestamp stx_ctime; /* Last attribute change time */ + struct statx_timestamp stx_mtime; /* Last data modification time */ + /* 0x80 */ + __u32 stx_rdev_major; /* Device ID of special file [if bdev/cdev] */ + __u32 stx_rdev_minor; + __u32 stx_dev_major; /* ID of device containing file [uncond] */ + __u32 stx_dev_minor; + /* 0x90 */ + __u64 stx_mnt_id; + __u32 stx_dio_mem_align; /* Memory buffer alignment for direct I/O */ + __u32 stx_dio_offset_align; /* File offset alignment for direct I/O */ + /* 0xa0 */ + __u64 __spare3[12]; /* Spare space for future expansion */ + /* 0x100 */ +}; + /* WARNING, it only deals with the 4096 first majors and 256 first minors = */ #define makedev(major, minor) ((dev_t)((((major) & 0xfff) << 8) | ((minor)= & 0xff))) #define major(dev) ((unsigned int)(((dev) >> 8) & 0xfff)) --=20 2.39.0 From nobody Fri Sep 12 23:55:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 638ECC05027 for ; Tue, 7 Feb 2023 02:10:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229847AbjBGCKD (ORCPT ); Mon, 6 Feb 2023 21:10:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229921AbjBGCJ6 (ORCPT ); Mon, 6 Feb 2023 21:09:58 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07ACD35262 for ; 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Mon, 06 Feb 2023 18:09:55 -0800 (PST) From: chris.chenfeiyang@gmail.com X-Google-Original-From: chenfeiyang@loongson.cn To: w@1wt.eu, paulmck@kernel.org Cc: Feiyang Chen , chenhuacai@kernel.org, jiaxun.yang@flygoat.com, arnd@arndb.de, chris.chenfeiyang@gmail.com, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] nolibc: Add support for LoongArch Date: Tue, 7 Feb 2023 10:09:41 +0800 Message-Id: <612947724da74327edb5e774de73d6d2a96d1648.1675734681.git.chenfeiyang@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Feiyang Chen Add support for LoongArch (32 and 64 bit) to nolibc. Signed-off-by: Feiyang Chen --- tools/include/nolibc/arch-loongarch.h | 223 ++++++++++++++++++++++++++ tools/include/nolibc/arch.h | 2 + 2 files changed, 225 insertions(+) create mode 100644 tools/include/nolibc/arch-loongarch.h diff --git a/tools/include/nolibc/arch-loongarch.h b/tools/include/nolibc/a= rch-loongarch.h new file mode 100644 index 000000000000..610efe00915c --- /dev/null +++ b/tools/include/nolibc/arch-loongarch.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: LGPL-2.1 OR MIT */ +/* + * LoongArch specific definitions for NOLIBC + * Copyright (C) 2023 Loongson Technology Corporation Limited + */ + +#ifndef _NOLIBC_ARCH_LOONGARCH_H +#define _NOLIBC_ARCH_LOONGARCH_H + +struct sys_stat_struct { + unsigned long st_dev; /* Device. */ + unsigned long st_ino; /* File serial number. */ + unsigned int st_mode; /* File mode. */ + unsigned int st_nlink; /* Link count. */ + unsigned int st_uid; /* User ID of the file's owner. */ + unsigned int st_gid; /* Group ID of the file's group. */ + unsigned long st_rdev; /* Device number, if device. */ + unsigned long __pad1; + long st_size; /* Size of file, in bytes. */ + int st_blksize; /* Optimal block size for I/O. */ + int __pad2; + long st_blocks; /* Number 512-byte blocks allocated. */ + long st_atime; /* Time of last access. */ + unsigned long st_atime_nsec; + long st_mtime; /* Time of last modification. */ + unsigned long st_mtime_nsec; + long st_ctime; /* Time of last status change. */ + unsigned long st_ctime_nsec; + unsigned int __unused4; + unsigned int __unused5; +}; + +/* Syscalls for LoongArch : + * - stack is 16-byte aligned + * - syscall number is passed in a7 + * - arguments are in a0, a1, a2, a3, a4, a5 + * - the system call is performed by calling "syscall 0" + * - syscall return comes in a0 + * - the arguments are cast to long and assigned into the target + * registers which are then simply passed as registers to the asm code, + * so that we don't have to experience issues with register constraint= s. + * + * On LoongArch, select() is not implemented so we have to use pselect6(). + */ +#define __ARCH_WANT_SYS_PSELECT6 + +#define my_syscall0(num) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0"); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "=3Dr"(_arg1) \ + : "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +#define my_syscall1(num, arg1) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0") =3D (long)(arg1); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "+r"(_arg1) \ + : "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +#define my_syscall2(num, arg1, arg2) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0") =3D (long)(arg1); \ + register long _arg2 __asm__ ("a1") =3D (long)(arg2); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "+r"(_arg1) \ + : "r"(_arg2), \ + "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +#define my_syscall3(num, arg1, arg2, arg3) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0") =3D (long)(arg1); \ + register long _arg2 __asm__ ("a1") =3D (long)(arg2); \ + register long _arg3 __asm__ ("a2") =3D (long)(arg3); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "+r"(_arg1) \ + : "r"(_arg2), "r"(_arg3), \ + "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +#define my_syscall4(num, arg1, arg2, arg3, arg4) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0") =3D (long)(arg1); \ + register long _arg2 __asm__ ("a1") =3D (long)(arg2); \ + register long _arg3 __asm__ ("a2") =3D (long)(arg3); \ + register long _arg4 __asm__ ("a3") =3D (long)(arg4); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "+r"(_arg1) \ + : "r"(_arg2), "r"(_arg3), "r"(_arg4), \ + "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +#define my_syscall5(num, arg1, arg2, arg3, arg4, arg5) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0") =3D (long)(arg1); \ + register long _arg2 __asm__ ("a1") =3D (long)(arg2); \ + register long _arg3 __asm__ ("a2") =3D (long)(arg3); \ + register long _arg4 __asm__ ("a3") =3D (long)(arg4); \ + register long _arg5 __asm__ ("a4") =3D (long)(arg5); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "+r"(_arg1) \ + : "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \ + "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +#define my_syscall6(num, arg1, arg2, arg3, arg4, arg5, arg6) = \ +({ = \ + register long _num __asm__ ("a7") =3D (num); \ + register long _arg1 __asm__ ("a0") =3D (long)(arg1); \ + register long _arg2 __asm__ ("a1") =3D (long)(arg2); \ + register long _arg3 __asm__ ("a2") =3D (long)(arg3); \ + register long _arg4 __asm__ ("a3") =3D (long)(arg4); \ + register long _arg5 __asm__ ("a4") =3D (long)(arg5); \ + register long _arg6 __asm__ ("a5") =3D (long)(arg6); \ + \ + __asm__ volatile ( \ + "syscall 0\n" \ + : "+r"(_arg1) \ + : "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), "r"(_arg6), \ + "r"(_num) \ + : "memory", "$t0", "$t1", "$t2", "$t3", \ + "$t4", "$t5", "$t6", "$t7", "$t8" \ + ); \ + _arg1; \ +}) + +char **environ __attribute__((weak)); +const unsigned long *_auxv __attribute__((weak)); + +#if __loongarch_grlen =3D=3D 32 +#define LONGLOG "2" +#define SZREG "4" +#define REG_L "ld.w" +#define LONG_S "st.w" +#define LONG_ADD "add.w" +#define LONG_ADDI "addi.w" +#define LONG_SLL "slli.w" +#define LONG_BSTRINS "bstrins.w" +#else // __loongarch_grlen =3D=3D 64 +#define LONGLOG "3" +#define SZREG "8" +#define REG_L "ld.d" +#define LONG_S "st.d" +#define LONG_ADD "add.d" +#define LONG_ADDI "addi.d" +#define LONG_SLL "slli.d" +#define LONG_BSTRINS "bstrins.d" +#endif + +/* startup code */ +void __attribute__((weak,noreturn,optimize("omit-frame-pointer"))) _start(= void) +{ + __asm__ volatile ( + REG_L " $a0, $sp, 0\n" // argc (a0) was in the stack + LONG_ADDI " $a1, $sp, "SZREG"\n" // argv (a1) =3D sp + SZREG + LONG_SLL " $a2, $a0, "LONGLOG"\n" // envp (a2) =3D SZREG*argc ... + LONG_ADDI " $a2, $a2, "SZREG"\n" // + SZREG (skip null) + LONG_ADD " $a2, $a2, $a1\n" // + argv + + "move $a3, $a2\n" // iterate a3 over envp to find au= xv (after NULL) + "0:\n" // do { + REG_L " $a4, $a3, 0\n" // a4 =3D *a3; + LONG_ADDI " $a3, $a3, "SZREG"\n" // a3 +=3D sizeof(void*); + "bne $a4, $zero, 0b\n" // } while (a4); + LONG_S " $a3, %[_auxv]\n" // store a3 into _auxv + + LONG_S " $a2, %[environ]\n" // store envp(a2) into environ + LONG_BSTRINS " $sp, $zero, 3, 0\n" // sp must be 16-byte aligned + "bl main\n" // main() returns the status code,= we'll exit with it. + "li.w $a7, 93\n" // NR_exit =3D=3D 93 + "syscall 0\n" + : + : [_auxv]"m"(_auxv), [environ]"m"(environ) + ); + __builtin_unreachable(); +} + +#endif // _NOLIBC_ARCH_LOONGARCH_H diff --git a/tools/include/nolibc/arch.h b/tools/include/nolibc/arch.h index 78b067a4fa47..2d5386a8d6aa 100644 --- a/tools/include/nolibc/arch.h +++ b/tools/include/nolibc/arch.h @@ -29,6 +29,8 @@ #include "arch-riscv.h" #elif defined(__s390x__) #include "arch-s390.h" +#elif defined(__loongarch__) +#include "arch-loongarch.h" #endif =20 #endif /* _NOLIBC_ARCH_H */ --=20 2.39.0 From nobody Fri Sep 12 23:55:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07FEFC636D3 for ; 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Mon, 06 Feb 2023 18:09:58 -0800 (PST) From: chris.chenfeiyang@gmail.com X-Google-Original-From: chenfeiyang@loongson.cn To: w@1wt.eu, paulmck@kernel.org Cc: Feiyang Chen , chenhuacai@kernel.org, jiaxun.yang@flygoat.com, arnd@arndb.de, chris.chenfeiyang@gmail.com, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] selftests/nolibc: Add support for LoongArch Date: Tue, 7 Feb 2023 10:09:42 +0800 Message-Id: <2d77fe4e895847ae1ea09088dcfa411ce2f57f5f.1675734681.git.chenfeiyang@loongson.cn> X-Mailer: git-send-email 2.39.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Feiyang Chen Add support for LoongArch (64 bit) to nolibc selftest. Signed-off-by: Feiyang Chen --- tools/testing/selftests/nolibc/Makefile | 78 +++++++++++++------------ 1 file changed, 41 insertions(+), 37 deletions(-) diff --git a/tools/testing/selftests/nolibc/Makefile b/tools/testing/selfte= sts/nolibc/Makefile index 8fe61d3e3cce..ea2b82a3cd86 100644 --- a/tools/testing/selftests/nolibc/Makefile +++ b/tools/testing/selftests/nolibc/Makefile @@ -13,52 +13,56 @@ ARCH =3D $(SUBARCH) endif =20 # kernel image names by architecture -IMAGE_i386 =3D arch/x86/boot/bzImage -IMAGE_x86_64 =3D arch/x86/boot/bzImage -IMAGE_x86 =3D arch/x86/boot/bzImage -IMAGE_arm64 =3D arch/arm64/boot/Image -IMAGE_arm =3D arch/arm/boot/zImage -IMAGE_mips =3D vmlinuz -IMAGE_riscv =3D arch/riscv/boot/Image -IMAGE_s390 =3D arch/s390/boot/bzImage -IMAGE =3D $(IMAGE_$(ARCH)) -IMAGE_NAME =3D $(notdir $(IMAGE)) +IMAGE_i386 =3D arch/x86/boot/bzImage +IMAGE_x86_64 =3D arch/x86/boot/bzImage +IMAGE_x86 =3D arch/x86/boot/bzImage +IMAGE_arm64 =3D arch/arm64/boot/Image +IMAGE_arm =3D arch/arm/boot/zImage +IMAGE_mips =3D vmlinuz +IMAGE_riscv =3D arch/riscv/boot/Image +IMAGE_s390 =3D arch/s390/boot/bzImage +IMAGE_loongarch =3D arch/loongarch/boot/vmlinuz.efi +IMAGE =3D $(IMAGE_$(ARCH)) +IMAGE_NAME =3D $(notdir $(IMAGE)) =20 # default kernel configurations that appear to be usable -DEFCONFIG_i386 =3D defconfig -DEFCONFIG_x86_64 =3D defconfig -DEFCONFIG_x86 =3D defconfig -DEFCONFIG_arm64 =3D defconfig -DEFCONFIG_arm =3D multi_v7_defconfig -DEFCONFIG_mips =3D malta_defconfig -DEFCONFIG_riscv =3D defconfig -DEFCONFIG_s390 =3D defconfig -DEFCONFIG =3D $(DEFCONFIG_$(ARCH)) +DEFCONFIG_i386 =3D defconfig +DEFCONFIG_x86_64 =3D defconfig +DEFCONFIG_x86 =3D defconfig +DEFCONFIG_arm64 =3D defconfig +DEFCONFIG_arm =3D multi_v7_defconfig +DEFCONFIG_mips =3D malta_defconfig +DEFCONFIG_riscv =3D defconfig +DEFCONFIG_s390 =3D defconfig +DEFCONFIG_loongarch =3D defconfig +DEFCONFIG =3D $(DEFCONFIG_$(ARCH)) =20 # optional tests to run (default =3D all) TEST =3D =20 # QEMU_ARCH: arch names used by qemu -QEMU_ARCH_i386 =3D i386 -QEMU_ARCH_x86_64 =3D x86_64 -QEMU_ARCH_x86 =3D x86_64 -QEMU_ARCH_arm64 =3D aarch64 -QEMU_ARCH_arm =3D arm -QEMU_ARCH_mips =3D mipsel # works with malta_defconfig -QEMU_ARCH_riscv =3D riscv64 -QEMU_ARCH_s390 =3D s390x -QEMU_ARCH =3D $(QEMU_ARCH_$(ARCH)) +QEMU_ARCH_i386 =3D i386 +QEMU_ARCH_x86_64 =3D x86_64 +QEMU_ARCH_x86 =3D x86_64 +QEMU_ARCH_arm64 =3D aarch64 +QEMU_ARCH_arm =3D arm +QEMU_ARCH_mips =3D mipsel # works with malta_defconfig +QEMU_ARCH_riscv =3D riscv64 +QEMU_ARCH_s390 =3D s390x +QEMU_ARCH_loongarch =3D loongarch64 +QEMU_ARCH =3D $(QEMU_ARCH_$(ARCH)) =20 # QEMU_ARGS : some arch-specific args to pass to qemu -QEMU_ARGS_i386 =3D -M pc -append "console=3DttyS0,9600 i8042.noaux pani= c=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" -QEMU_ARGS_x86_64 =3D -M pc -append "console=3DttyS0,9600 i8042.noaux pani= c=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" -QEMU_ARGS_x86 =3D -M pc -append "console=3DttyS0,9600 i8042.noaux pani= c=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" -QEMU_ARGS_arm64 =3D -M virt -cpu cortex-a53 -append "panic=3D-1 $(TEST:%= =3DNOLIBC_TEST=3D%)" -QEMU_ARGS_arm =3D -M virt -append "panic=3D-1 $(TEST:%=3DNOLIBC_TEST= =3D%)" -QEMU_ARGS_mips =3D -M malta -append "panic=3D-1 $(TEST:%=3DNOLIBC_TEST= =3D%)" -QEMU_ARGS_riscv =3D -M virt -append "console=3DttyS0 panic=3D-1 $(TEST:%= =3DNOLIBC_TEST=3D%)" -QEMU_ARGS_s390 =3D -M s390-ccw-virtio -m 1G -append "console=3DttyS0 pa= nic=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" -QEMU_ARGS =3D $(QEMU_ARGS_$(ARCH)) +QEMU_ARGS_i386 =3D -M pc -append "console=3DttyS0,9600 i8042.noaux p= anic=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS_x86_64 =3D -M pc -append "console=3DttyS0,9600 i8042.noaux p= anic=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS_x86 =3D -M pc -append "console=3DttyS0,9600 i8042.noaux p= anic=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS_arm64 =3D -M virt -cpu cortex-a53 -append "panic=3D-1 $(TES= T:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS_arm =3D -M virt -append "panic=3D-1 $(TEST:%=3DNOLIBC_TES= T=3D%)" +QEMU_ARGS_mips =3D -M malta -append "panic=3D-1 $(TEST:%=3DNOLIBC_TE= ST=3D%)" +QEMU_ARGS_riscv =3D -M virt -append "console=3DttyS0 panic=3D-1 $(TES= T:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS_s390 =3D -M s390-ccw-virtio -m 1G -append "console=3DttyS0= panic=3D-1 $(TEST:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS_loongarch =3D -M virt -append "console=3DttyS0,115200 panic=3D-= 1 $(TEST:%=3DNOLIBC_TEST=3D%)" +QEMU_ARGS =3D $(QEMU_ARGS_$(ARCH)) =20 # OUTPUT is only set when run from the main makefile, otherwise # it defaults to this nolibc directory. --=20 2.39.0