From nobody Mon Apr 13 14:30:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E115DC4332F for ; Tue, 22 Nov 2022 07:40:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232444AbiKVHkb (ORCPT ); Tue, 22 Nov 2022 02:40:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232242AbiKVHkW (ORCPT ); Tue, 22 Nov 2022 02:40:22 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94981B491 for ; Mon, 21 Nov 2022 23:39:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bJ2u7mh9nd2kJ2SvCMIUbxbNtsjSUFYoRollOBUuJAE=; b=dFC6GbAPpM573pcrn5gst2XnY+L432w5W0DYRLYPUtrXc4RdAbX1VkTDfsXSeh1OqvDHJ4 N2unV+4HbIgbRC53hwGi1p8QYX3Q82uACfD992EePRQuMSwl8FcNdwg3Y26GKmULY7ciwa Zll8ZHTk+NqW2cxFTvpmaGO92PTRQ0U5WMSx9Q4wU4l8J9WKTEJEaWPE8TzRHY+myFWXOU XUmPcrnmcsR9s6XB8jgINsi18CLziugKkYpdXd5xwUIRHkLN2vSU3+KG0fBQiQQ0KveAg6 TdtNLVnJ/2/dFdV8gTJ+gaqAejSfcsij+CbxSz0TlNFdWu8cHPTsNq1CJgkN4Q== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-9-8qG2M24zMBahALnruAeT0w-2; Tue, 22 Nov 2022 02:39:21 -0500 X-MC-Unique: 8qG2M24zMBahALnruAeT0w-2 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:17 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 1/4] x86/of: Convert Intel's APIC bindings to YAML schema Date: Tue, 22 Nov 2022 15:39:07 +0800 Message-ID: <0cf089495a422b945ac4fc9c980ddb5429a711c3.1669100394.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel's APIC family of interrupt controllers support local APIC (lapic) & I/O APIC (ioapic). Convert existing bindings for lapic & ioapic from text to YAML schema. Separate lapic & ioapic schemas. Addditionally, add description which was missing in text file and add few more required standard properties which were also missing in text file. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../intel,ce4100-ioapic.txt | 26 -------- .../intel,ce4100-ioapic.yaml | 62 +++++++++++++++++++ .../intel,ce4100-lapic.yaml | 49 +++++++++++++++ 3 files changed, 111 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-lapic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.txt b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-ioapic.txt deleted file mode 100644 index 7d19f494f19a..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.txt +++ /dev/null @@ -1,26 +0,0 @@ -Interrupt chips ---------------- - -* Intel I/O Advanced Programmable Interrupt Controller (IO APIC) - - Required properties: - -------------------- - compatible =3D "intel,ce4100-ioapic"; - #interrupt-cells =3D <2>; - - Device's interrupt property: - - interrupts =3D

; - - The first number (P) represents the interrupt pin which is wired to the - IO APIC. The second number (S) represents the sense of interrupt which - should be configured and can be one of: - 0 - Edge Rising - 1 - Level Low - 2 - Level High - 3 - Edge Falling - -* Local APIC - Required property: - - compatible =3D "intel,ce4100-lapic"; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-ioapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/= intel,ce4100-ioapic.yaml new file mode 100644 index 000000000000..da966287eec2 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-i= oapic.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioap= ic.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) + +maintainers: + - Sebastian Andrzej Siewior + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more + details on it. + + This schema defines bindings for I/O APIC interrupt controller. + +properties: + compatible: + const: intel,ce4100-ioapic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + ioapic1: interrupt-controller@fec00000 { + compatible =3D "intel,ce4100-ioapic"; + reg =3D <0xfec00000 0x1000>; + #interrupt-cells =3D <2>; + #address-cells =3D <0>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml new file mode 100644 index 000000000000..d4b99bf7bf6e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapi= c.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Intel Local Advanced Programmable Interrupt Controller (LAPIC) + +maintainers: + - Sebastian Andrzej Siewior + + +description: | + Intel's Advanced Programmable Interrupt Controller (APIC) is a + family of interrupt controllers. The APIC is a split + architecture design, with a local component (LAPIC) integrated + into the processor itself and an external I/O APIC. Local APIC + (lapic) receives interrupts from the processor's interrupt pins, + from internal sources and from an external I/O APIC (ioapic). + And it sends these to the processor core for handling. + See https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf + Chapter 8 for more details. + + Many of the Intel's generic devices like hpet, ioapic, lapic have + the ce4100 name in their compatible property names because they + first appeared in CE4100 SoC. See bindings/x86/ce4100.txt for more + details on it. + + This schema defines bindings for local APIC interrupt controller. + +properties: + compatible: + const: intel,ce4100-lapic + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + lapic0: interrupt-controller@fee00000 { + compatible =3D "intel,ce4100-lapic"; + reg =3D <0xfee00000 0x1000>; + }; --=20 2.17.1 From nobody Mon Apr 13 14:30:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6792C4332F for ; Tue, 22 Nov 2022 07:40:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232492AbiKVHkk (ORCPT ); Tue, 22 Nov 2022 02:40:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232448AbiKVHk2 (ORCPT ); Tue, 22 Nov 2022 02:40:28 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 093FC17589 for ; Mon, 21 Nov 2022 23:39:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uGSJ7DPtFsorciAkWhHmN4hRW1hAr3Y9mVSmMvM8cgs=; b=OXwjCA8EU08bfMp/IWSWlK4upsCRm/k6RIu1R08bvQCjppyapAmg+AoGCCIQ9/NEnJSruj IGqHtaieGnHWi+HRge5KmC84vPfNPlPxL8F1ehyAUTxhxhA8n9IbNeiq6s1MTKSFKRQfRV lksnnx3ozgi960jJK2Nc78YOFSKUo/fRMossnVAXB8QuZhS266tUBBsWL+CzhG+e2D92sl Xvk4wiAl8SFJB5kuaZDrp2g71JsPO7serhn4wO4CGZKAeP6MwJ43zvU9uaV7xJY73fFZwf ROYSsj3iKVRHgqZDANMVmajNkJ3WdE+FvSWtuetAySH1sFRry9skWMvH/tjeyQ== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-564-hiVtk4evPvGvvH9_C1TAOw-1; Tue, 22 Nov 2022 02:39:24 -0500 X-MC-Unique: hiVtk4evPvGvvH9_C1TAOw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:20 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 2/4] x86/of: Introduce new optional bool property for lapic Date: Tue, 22 Nov 2022 15:39:08 +0800 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel defines a few possible interrupt delivery modes. With respect to boot/init time, mainly two interrupt delivery modes are possible. PIC Mode - Legacy external 8259 compliant PIC interrupt controller. Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode. For ACPI or MPS spec compliant systems, it is figured out by some read only bit field/s available in their respective defined data structures. But for OF based systems, it is by default set to PIC mode. Presently, it is hardcoded to legacy PIC mode for OF based x86 systems with no option to choose the configuration between PIC mode & virtual wire mode. For this purpose, introduce a new boolean property for interrupt controller node of lapic which can allow it to be configured to virtual wire mode as well. Property name: 'intel,virtual-wire-mode' Type: Boolean If not present/not defined, interrupt delivery mode defaults to legacy PIC mode. If present/defined, interrupt delivery mode is set to virtual wire mode. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- .../interrupt-controller/intel,ce4100-lapic.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/intel,c= e4100-lapic.yaml b/Documentation/devicetree/bindings/interrupt-controller/i= ntel,ce4100-lapic.yaml index d4b99bf7bf6e..087f849e31ef 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/intel,ce4100-l= apic.yaml @@ -35,6 +35,19 @@ properties: reg: maxItems: 1 =20 + intel,virtual-wire-mode: + description: Intel defines a few possible interrupt delivery + modes. With respect to boot/init time, mainly two interrupt + delivery modes are possible. + PIC Mode - Legacy external 8259 compliant PIC interrupt controller. + Virtual Wire Mode - use lapic as virtual wire interrupt delivery mod= e. + For ACPI or MPS spec compliant systems, it is figured out by some re= ad + only bit field/s available in their respective defined data structur= es. + For OF based systems, it is by default set to PIC mode. + But if this optional boolean property is set, then the interrupt del= ivery + mode is configured to virtual wire compatibility mode. + type: boolean + required: - compatible - reg @@ -46,4 +59,5 @@ examples: lapic0: interrupt-controller@fee00000 { compatible =3D "intel,ce4100-lapic"; reg =3D <0xfee00000 0x1000>; + intel,virtual-wire-mode; }; --=20 2.17.1 From nobody Mon Apr 13 14:30:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FB58C4332F for ; Tue, 22 Nov 2022 07:40:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232478AbiKVHkg (ORCPT ); Tue, 22 Nov 2022 02:40:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232429AbiKVHkX (ORCPT ); Tue, 22 Nov 2022 02:40:23 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A18282F02B for ; Mon, 21 Nov 2022 23:39:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102769; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XtiwGqXBFxhLlETvxktwt1UqNvSglqTHBPfqfwhsYIM=; b=UcP263p6N2TG1BS4XSgvYyUErTmv6YA8VCzKnX4jKwyY49R+zQ/dYeYllwvYObWST3djcb XfbT/2DS0pje3R7oCXETGoaeVtF+2/TL5PI34Ay/oUdAQEMuT1g8Wlxu3/pDkoKAEGw6Be cLFSYPK5vFyVIVNgF02U8NCgIhrKvvu8ttMJHfGaAa8ZeBeFAz8kB2EGeobdm6KrCF5OP5 RkAB/2GiBQJND7+XVPsmvm8l2f3b8PKpqazkPmBIx9iyp69gelEG1bYfK3GBQzZdHZ/NsK ccK3XWglzWqjszV23xHAu34VodndVs/7QGBHlCdMoeZu3RbSvGlQxjp9zlZN3g== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-403-ZD30hwUhOOCueD0AViRi6g-1; Tue, 22 Nov 2022 02:39:27 -0500 X-MC-Unique: ZD30hwUhOOCueD0AViRi6g-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:23 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Date: Tue, 22 Nov 2022 15:39:09 +0800 Message-ID: <64a905649accf1b68f03c31a9b6ce205b03c6703.1669100394.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use latest available pr_lvl() instead of older printk(KERN_LVL) Just a upgrade of print utilities usage no functional changes. Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar Reviewed-by: Andy Shevchenko --- arch/x86/kernel/devicetree.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index 5cd51f25f446..fcc6f1b7818f 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -248,7 +248,7 @@ static void __init dtb_add_ioapic(struct device_node *d= n) =20 ret =3D of_address_to_resource(dn, 0, &r); if (ret) { - printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn); + pr_err("Can't obtain address from device node %pOF.\n", dn); return; } mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg); @@ -265,7 +265,7 @@ static void __init dtb_ioapic_setup(void) of_ioapic =3D 1; return; } - printk(KERN_ERR "Error: No information about IO-APIC in OF.\n"); + pr_err("Error: No information about IO-APIC in OF.\n"); } #else static void __init dtb_ioapic_setup(void) {} --=20 2.17.1 From nobody Mon Apr 13 14:30:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EA69C4332F for ; Tue, 22 Nov 2022 07:40:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232536AbiKVHku (ORCPT ); Tue, 22 Nov 2022 02:40:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232449AbiKVHkd (ORCPT ); Tue, 22 Nov 2022 02:40:33 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FEFB2CDD3 for ; Mon, 21 Nov 2022 23:39:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669102773; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NIxTZz2RzC+iXQFQE7e0/V45lRrJ5i50zwbfXYW5JwA=; b=IsAIDmzitw9T3PISuGOEoATYC3ZrvJpZODtdTKZGxIfvrOdnlYUFCdM16dkGaunED5w3en SSSRzs06a9l5EUWY4UxMoaj5rzLb9eaD4+hm/FVyiZJZwzG7WW1+dNATRuwhhcNSSfrR8P IcActC+tGHr2tax5KZXVAVhqA0EqPBgP4L0Q6zJXwCyLAIZFpV/iEednRp/c+UF+I9T1nX BPdfSpRjLQAgE64ndYM6LCtlKGjDwa/kcOaWHuzZ8Be83vXYJhkQ/uT3ZvjNoOQqpJL+wN fZMKZS6BdEXKJfS+JGmSiFyf5QHa/dz5ZUXqWfvtBsJyrnipbU4Lx9AB3fZuHg== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-648-F9bOVu-HOg-Z6mcJPGgXxg-1; Tue, 22 Nov 2022 02:39:30 -0500 X-MC-Unique: F9bOVu-HOg-Z6mcJPGgXxg-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Mon, 21 Nov 2022 23:39:26 -0800 From: Rahul Tanwar To: , , , , , , CC: , , , , Rahul Tanwar Subject: [PATCH v3 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Tue, 22 Nov 2022 15:39:10 +0800 Message-ID: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This is a bug for platforms which are OF based but do not use 8259 compliant legacy PIC interrupt controller. Such platforms can not even boot because of this bug/hardcoding. Fix this bug by adding support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Fixes: 3879a6f32948 ("x86: dtb: Add early parsing of IO_APIC") Suggested-by: Andy Shevchenko Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) return; } smp_found_config =3D 1; - pic_mode =3D 1; + if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { + pr_info("Virtual Wire compatibility mode.\n"); + pic_mode =3D 0; + } else { + pr_info("IMCR and PIC compatibility mode.\n"); + pic_mode =3D 1; + } + register_lapic_address(lapic_addr); } =20 --=20 2.17.1