From nobody Wed Apr 8 21:14:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB66AC38A02 for ; Sun, 30 Oct 2022 00:51:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbiJ3Avb (ORCPT ); Sat, 29 Oct 2022 20:51:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229629AbiJ3Av2 (ORCPT ); Sat, 29 Oct 2022 20:51:28 -0400 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E66D3FED1; Sat, 29 Oct 2022 17:51:27 -0700 (PDT) Received: by mail-pj1-x102d.google.com with SMTP id r61-20020a17090a43c300b00212f4e9cccdso13015692pjg.5; Sat, 29 Oct 2022 17:51:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:references:in-reply-to:message-id:date :subject:to:from:from:to:cc:subject:date:message-id:reply-to; bh=ANEhihAqc+rSAji5S1A02YEBoRyu9ZtLwD6DRxGi/HU=; b=HZBdE5kmHNDNeA4duKPPdVEErV00KJK5dhhbOh0YvnTE9FOs2/MQXKqnVGeV7b7GF0 ebMS9VGbIwmaKWjg9ThCrU+ILUZwBkV/zs+mqLcofUu7tDKAmqHBFdmf7z7qpYSsywlf GMkAOfezYSIP2vde3D33yj1E2nb6ZFrJ6LYJu4W8bQ9r3530aBHJOUyTEwHMAB1NGQpG BL3VLXweIVOGJm15qLBX598Sg25d7o7WzteFEvgSzoVFfAlHQ6dGTvjbhwjFeEtcYYWG utvoHgMjWTQlAEzkS4aJfXfhDCHSt0+xVkrhlHcGQ72zZbFSF0o/EJomGvY2IMIe2ede wzAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:references:in-reply-to:message-id:date :subject:to:from:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=ANEhihAqc+rSAji5S1A02YEBoRyu9ZtLwD6DRxGi/HU=; b=XBgBtwMUomSHf0gM2ior1ob30YZNwt+R+8ccDwuH9G2UyOgFYavGJ2OEpYapPIh6Si vNZBbfqiN0KgUHwhaI76ry6dxvo8a8D2G0SZHS3ubkDLlYm8AvDnO9EJFv8oJuFICkIw 5wT2tgFteeT3SD0G6E1YBHtDp0yIk4IEYdBs1kt0woW4OCJr3Fjr4+7eJtsi2vrb/9zK civ+fMNZD+e7aCpDGeKRfdOW+IHkDFKYcrHSv41k2Cx+vxVA7/OXE/5yp2MKTbSZi6k/ hjbxwd/yCHmTNVDW0+J135eJCxR0z6Jz5G+Xlsay+rssOm/7ASMDHTmx9qUA8a+C9zI2 rCkg== X-Gm-Message-State: ACrzQf2zg80HnzdwHkos8Ds0GY7P5/nBaDrAPbmTL5sQ1uZk911mHve+ Buc+bJayYhUc7k/o7k2F4WY= X-Google-Smtp-Source: AMsMyM4sO1wbZ9sxSYCXnLbtl3lXKLWKABJsH/0+BF9gxOvsWORV5jGYjv+P9JUMldHag7rRH/a6xA== X-Received: by 2002:a17:903:4ca:b0:179:d21f:f04b with SMTP id jm10-20020a17090304ca00b00179d21ff04bmr6902683plb.7.1667091086918; Sat, 29 Oct 2022 17:51:26 -0700 (PDT) Received: from scdiu3.sunplus.com ([113.196.136.192]) by smtp.googlemail.com with ESMTPSA id b14-20020a170902650e00b00176dd41320dsm1836744plk.119.2022.10.29.17.51.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Oct 2022 17:51:26 -0700 (PDT) From: Tony Huang To: tonyhuang.sunplus@gmail.com, lhjeff911@gmail.com, ulf.hansson@linaro.org, robh+dt@kernle.org, krzk+dz@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, wells.lu@sunplus.com Subject: [PATCH v11 1/2] dt-binding: mmc: Add mmc yaml file for Sunplus SP7021 Date: Sun, 30 Oct 2022 08:50:49 +0800 Message-Id: <61818eada54f5adb873455143cd950b28d57bc2c.1667087353.git.tonyhuang.sunplus@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add MMC YAML file for Sunplus SP7021. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tony Huang --- Changes in v5: - Addressed comments from Krzysztof. Changes in v6: - Addressed comments from Krzysztof. - To substitute MMC for mmc. To substitute YMAL for ymal. - Remove max-frequency. - Fixed wrong file name. Changes in v7: -No change. Changes in v8: -No change. Changes in v9: -No change. Changes in v10: -No change. Changes in v11: -No change. .../devicetree/bindings/mmc/sunplus,mmc.yaml | 62 ++++++++++++++++++= ++++ MAINTAINERS | 6 +++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml diff --git a/Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml b/Docum= entation/devicetree/bindings/mmc/sunplus,mmc.yaml new file mode 100644 index 0000000..50f2119 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Ltd. Co. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/sunplus,mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus MMC Controller + +maintainers: + - Tony Huang + - Li-hao Kuo + +allOf: + - $ref: "mmc-controller.yaml" + +properties: + compatible: + enum: + - sunplus,sp7021-mmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + +unevaluatedProperties: false + +examples: + - | + #include + #include + mmc0: mmc@9c003b00 { + compatible =3D "sunplus,sp7021-mmc"; + reg =3D <0x9c003b00 0x180>; + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clkc 0x4e>; + resets =3D <&rstc 0x3e>; + bus-width =3D <8>; + max-frequency =3D <52000000>; + non-removable; + disable-wp; + cap-mmc-highspeed; + mmc-ddr-3_3v; + no-sdio; + no-sd; + }; + diff --git a/MAINTAINERS b/MAINTAINERS index fd768d4..cdd809a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18869,6 +18869,12 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/dlink/sundance.c =20 +SUNPLUS MMC DRIVER +M: Tony Huang +M: Li-hao Kuo +S: Maintained +F: Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml + SUNPLUS OCOTP DRIVER M: Vincent Shih S: Maintained --=20 2.7.4 From nobody Wed Apr 8 21:14:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9EDCFA3740 for ; Sun, 30 Oct 2022 00:51:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229674AbiJ3Avi (ORCPT ); Sat, 29 Oct 2022 20:51:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229629AbiJ3Avc (ORCPT ); Sat, 29 Oct 2022 20:51:32 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 204C73FEDB; Sat, 29 Oct 2022 17:51:30 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id v4-20020a17090a088400b00212cb0ed97eso7527019pjc.5; Sat, 29 Oct 2022 17:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=references:in-reply-to:references:in-reply-to:message-id:date :subject:to:from:from:to:cc:subject:date:message-id:reply-to; bh=VLooyx4jDkeMtIjuMyoD1nIwOUs+bD/sRF/TFcfeqyQ=; b=XcLVc2s+yg39NVMonlftPqDgEJbDEuWYVJpMJniBdo9bAnNd1tprYXh0OkXdNDKV/F GWMttCbZWaS2O5gt5BxJwu5x1EqZq9el/7LasVD6s9iqrSI1BOXO4PXBO4Lb51zzuYv4 A6P9kc9Dxy7S8TPLEXg+4WovqaaEkcp0AaDRddutuQCLUvXAZ/SoAKAb2jEyGHQaUtDm W1/jY8ZAz01nsI4to8KHN5Wx6HT9QXT9sycjxDVi6G4CQaLntrEzCmITzXOvQ81iV+GD qA0cLac4U1NoUluT2caCxw4nlhkVvLX+0EM8cM7IyOf73p8tHTB9pjxWHOqfkynOeff9 6FLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:references:in-reply-to:message-id:date :subject:to:from:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=VLooyx4jDkeMtIjuMyoD1nIwOUs+bD/sRF/TFcfeqyQ=; b=Sb1QimOFownSgfpa8wCyHtA8URg3Q6Z0nT4e9baGF2KIF/2zro1g+xJaznSvcOxu66 928cCThzaOHiIn/b4KYiESzOhNdxXZsyy80gFKMigJW8XGQfUnSAqSdnkx9RCcWyt9Y8 PzINDe02SuS1mEGuJYk173KwLt2GUkrnDexrWPNBpWf4GJIRkzqYZiWqF3XH0jl9qXvS 5jqVcZ6AMy/4E5bqzflVRqUe7edl1w2qF9cCjFZkXS7CBI0AFJJ7McsXVJ9U9WCvLB7M XZDgOrMSJXaJLMIZDdZ09rXwRChpbHlZ9fCBAqO0bGiGx/uMvsamVWsJdP7RcA8lWSoM dxYQ== X-Gm-Message-State: ACrzQf0/pxY0e9Ns4yhAFHs+pjTa87KjejNbO7rZSlDrk22DtCFZ7HtA l4c1x465rXqQo2IqJUD5M9Q= X-Google-Smtp-Source: AMsMyM6QpW5bKK7lNPJCTeKawKnm48je4lPKNyy3479B/L5tv1O4xCImOtYcCCoccQ5cxtT4mpFMww== X-Received: by 2002:a17:90b:4c86:b0:20d:8410:d829 with SMTP id my6-20020a17090b4c8600b0020d8410d829mr7248093pjb.146.1667091089352; Sat, 29 Oct 2022 17:51:29 -0700 (PDT) Received: from scdiu3.sunplus.com ([113.196.136.192]) by smtp.googlemail.com with ESMTPSA id b14-20020a170902650e00b00176dd41320dsm1836744plk.119.2022.10.29.17.51.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Oct 2022 17:51:28 -0700 (PDT) From: Tony Huang To: tonyhuang.sunplus@gmail.com, lhjeff911@gmail.com, ulf.hansson@linaro.org, robh+dt@kernle.org, krzk+dz@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, wells.lu@sunplus.com Subject: [PATCH v11 2/2] mmc: Add mmc driver for Sunplus SP7021 Date: Sun, 30 Oct 2022 08:50:50 +0800 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a patch for mmc driver for Sunplus SP7021 SOC. Supports eMMC 4.41 DDR 104MB/s speed mode. Acked-by: Arnd Bergmann Signed-off-by: Tony Huang --- Changes in v5: - Addressed comments from Krzysztof. - Remove the relevant sdcard code. - Submit the emmc code only. Changes in v6: - Addressed comments from Arnd. - Use SYSTEM_SLEEP_PM_OPS instead of SET_SYSTEM_SLEEP_PM_OPS. - Use RUNTIME_PM_OPS instead of SET_RUNTIME_PM_OPS. - Remove #ifdef check. - Fixed mutex lock and unlock imbalance issue. Changes in v7: - Addressed comments from kernel test robot. - Remove unused vairable. - Add previous prototype. - Addressed make error and warning in kernel 5.18-rc1. Changes in v8: - Addressed comments from Uffe. Changes in v9: - Addressed comments from Uffe. Changes in v10: - Addressed comments from Uffe. - Addressed MMC test failed. Changes in v11: - Addressed comments from Arnd. - Addressed comments from MMC test failed. MAINTAINERS | 1 + drivers/mmc/host/Kconfig | 9 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sunplus-mmc.c | 976 +++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 987 insertions(+) create mode 100644 drivers/mmc/host/sunplus-mmc.c diff --git a/MAINTAINERS b/MAINTAINERS index cdd809a..2439234 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18874,6 +18874,7 @@ M: Tony Huang M: Li-hao Kuo S: Maintained F: Documentation/devicetree/bindings/mmc/sunplus,mmc.yaml +F: drivers/mmc/host/sunplus-mmc.c =20 SUNPLUS OCOTP DRIVER M: Vincent Shih diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index af6c3c3..d99ee3b 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -14,6 +14,15 @@ config MMC_DEBUG added host drivers please don't invent their private macro for debugging. =20 +config MMC_SUNPLUS + tristate "Sunplus SP7021 MMC Controller" + depends on ARCH_SUNPLUS || COMPILE_TEST + help + If you say yes here, you will get support for eMMC host interface + on Sunplus SoCs. + + If unsure, say N + config MMC_ARMMMCI tristate "ARM AMBA Multimedia Card Interface support" depends on ARM_AMBA diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 4e4ceb3..ba0c6d0 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) +=3D sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) +=3D sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) +=3D sdhci-omap.o obj-$(CONFIG_MMC_SDHCI_SPRD) +=3D sdhci-sprd.o +obj-$(CONFIG_MMC_SUNPLUS) +=3D sunplus-mmc.o obj-$(CONFIG_MMC_CQHCI) +=3D cqhci.o cqhci-y +=3D cqhci-core.o cqhci-$(CONFIG_MMC_CRYPTO) +=3D cqhci-crypto.o diff --git a/drivers/mmc/host/sunplus-mmc.c b/drivers/mmc/host/sunplus-mmc.c new file mode 100644 index 0000000..d36c700 --- /dev/null +++ b/drivers/mmc/host/sunplus-mmc.c @@ -0,0 +1,976 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Sunplus Inc. + * Author: Tony Huang + * Author: Li-hao Kuo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPMMC_MIN_CLK 400000 +#define SPMMC_MAX_CLK 52000000 +#define SPMMC_MAX_BLK_COUNT 65536 +#define SPMMC_MAX_TUNABLE_DLY 7 +#define SPMMC_TIMEOUT 500000 + +#define SPMMC_CARD_MEDIATYPE_SRCDST_REG 0x0000 +#define SPMMC_MEDIA_TYPE GENMASK(2, 0) +#define SPMMC_DMA_SOURCE GENMASK(6, 4) +#define SPMMC_DMA_DESTINATION GENMASK(10, 8) +#define SPMMC_MEDIA_NONE 0 +#define SPMMC_MEDIA_SD 6 +#define SPMMC_MEDIA_MS 7 + +#define SPMMC_SDRAM_SECTOR_0_SIZE_REG 0x0008 +#define SPMMC_DMA_BASE_ADDR_REG 0x000C +#define SPMMC_HW_DMA_CTRL_REG 0x0010 +#define SPMMC_HW_DMA_RST BIT(9) +#define SPMMC_DMAIDLE BIT(10) + +#define SPMMC_MAX_DMA_MEMORY_SECTORS 8 + +#define SPMMC_SDRAM_SECTOR_1_ADDR_REG 0x0018 + +#define SPMMC_SD_INT_REG 0x0088 +#define SPMMC_SDINT_SDCMPEN BIT(0) +#define SPMMC_SDINT_SDCMP BIT(1) +#define SPMMC_SDINT_SDCMPCLR BIT(2) +#define SPMMC_SDINT_SDIOEN BIT(3) +#define SPMMC_SDINT_SDIO BIT(4) +#define SPMMC_SDINT_SDIOCLR BIT(5) + +#define SPMMC_SD_PAGE_NUM_REG 0x008C + +#define SPMMC_SD_CONFIG0_REG 0x0090 +#define SPMMC_SD_PIO_MODE BIT(0) +#define SPMMC_SD_DDR_MODE BIT(1) +#define SPMMC_SD_LEN_MODE BIT(2) +#define SPMMC_SD_TRANS_MODE GENMASK(5, 4) +#define SPMMC_SD_AUTO_RESPONSE BIT(6) +#define SPMMC_SD_CMD_DUMMY BIT(7) +#define SPMMC_SD_RSP_CHK_EN BIT(8) +#define SPMMC_SDIO_MODE BIT(9) +#define SPMMC_SD_MMC_MODE BIT(10) +#define SPMMC_SD_DATA_WD BIT(11) +#define SPMMC_RX4_EN BIT(14) +#define SPMMC_SD_RSP_TYPE BIT(15) +#define SPMMC_MMC8_EN BIT(18) +#define SPMMC_CLOCK_DIVISION GENMASK(31, 20) + +#define SPMMC_SDIO_CTRL_REG 0x0094 +#define SPMMC_INT_MULTI_TRIG BIT(6) + +#define SPMMC_SD_RST_REG 0x0098 +#define SPMMC_SD_CTRL_REG 0x009C +#define SPMMC_NEW_COMMAND_TRIGGER BIT(0) +#define SPMMC_DUMMY_CLOCK_TRIGGER BIT(1) + +#define SPMMC_SD_STATUS_REG 0x00A0 +#define SPMMC_SDSTATUS_DUMMY_READY BIT(0) +#define SPMMC_SDSTATUS_RSP_BUF_FULL BIT(1) +#define SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY BIT(2) +#define SPMMC_SDSTATUS_RX_DATA_BUF_FULL BIT(3) +#define SPMMC_SDSTATUS_CMD_PIN_STATUS BIT(4) +#define SPMMC_SDSTATUS_DAT0_PIN_STATUS BIT(5) +#define SPMMC_SDSTATUS_RSP_TIMEOUT BIT(6) +#define SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT BIT(7) +#define SPMMC_SDSTATUS_STB_TIMEOUT BIT(8) +#define SPMMC_SDSTATUS_RSP_CRC7_ERROR BIT(9) +#define SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR BIT(10) +#define SPMMC_SDSTATUS_RDATA_CRC16_ERROR BIT(11) +#define SPMMC_SDSTATUS_SUSPEND_STATE_READY BIT(12) +#define SPMMC_SDSTATUS_BUSY_CYCLE BIT(13) +#define SPMMC_SDSTATUS_DAT1_PIN_STATUS BIT(14) +#define SPMMC_SDSTATUS_SD_SENSE_STATUS BIT(15) +#define SPMMC_SDSTATUS_BOOT_ACK_TIMEOUT BIT(16) +#define SPMMC_SDSTATUS_BOOT_DATA_TIMEOUT BIT(17) +#define SPMMC_SDSTATUS_BOOT_ACK_ERROR BIT(18) + +#define SPMMC_SD_STATE_REG 0x00A4 +#define SPMMC_CRCTOKEN_CHECK_RESULT GENMASK(6, 4) +#define SPMMC_SDSTATE_ERROR BIT(13) +#define SPMMC_SDSTATE_FINISH BIT(14) + +#define SPMMC_SD_HW_STATE_REG 0x00A8 +#define SPMMC_SD_BLOCKSIZE_REG 0x00AC + +#define SPMMC_SD_CONFIG1_REG 0x00B0 +#define SPMMC_TX_DUMMY_NUM GENMASK(8, 0) +#define SPMMC_SD_HIGH_SPEED_EN BIT(31) + +#define SPMMC_SD_TIMING_CONFIG0_REG 0x00B4 +#define SPMMC_SD_CLOCK_DELAY GENMASK(2, 0) +#define SPMMC_SD_WRITE_DATA_DELAY GENMASK(6, 4) +#define SPMMC_SD_WRITE_COMMAND_DELAY GENMASK(10, 8) +#define SPMMC_SD_READ_RESPONSE_DELAY GENMASK(14, 12) +#define SPMMC_SD_READ_DATA_DELAY GENMASK(18, 16) +#define SPMMC_SD_READ_CRC_DELAY GENMASK(22, 20) + +#define SPMMC_SD_PIODATATX_REG 0x00BC +#define SPMMC_SD_PIODATARX_REG 0x00C0 +#define SPMMC_SD_CMDBUF0_3_REG 0x00C4 +#define SPMMC_SD_CMDBUF4_REG 0x00C8 +#define SPMMC_SD_RSPBUF0_3_REG 0x00CC +#define SPMMC_SD_RSPBUF4_5_REG 0x00D0 + +#define SPMMC_MAX_RETRIES (8 * 8) + +struct spmmc_tuning_info { + int enable_tuning; + int need_tuning; + int retried; /* how many times has been retried */ + u32 rd_crc_dly:3; + u32 rd_dat_dly:3; + u32 rd_rsp_dly:3; + u32 wr_cmd_dly:3; + u32 wr_dat_dly:3; + u32 clk_dly:3; +}; + +#define SPMMC_DMA_MODE 0 +#define SPMMC_PIO_MODE 1 + +struct spmmc_host { + void __iomem *base; + struct clk *clk; + struct reset_control *rstc; + spinlock_t lock; /* Prevent races with irq handler */ + struct mmc_host *mmc; + struct mmc_request *mrq; /* current mrq */ + int irq; + int dmapio_mode; + struct spmmc_tuning_info tuning_info; + int dma_int_threshold; + int dma_use_int; +}; + +static inline int spmmc_wait_finish(struct spmmc_host *host) +{ + u32 state; + + return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state, + (state & SPMMC_SDSTATE_FINISH), 10, SPMMC_TIMEOUT); +} + +static inline int spmmc_wait_sdstatus(struct spmmc_host *host, unsigned in= t status_bit) +{ + u32 status; + + return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status, + (status & status_bit), 10, SPMMC_TIMEOUT); +} + +#define spmmc_wait_rspbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTA= TUS_RSP_BUF_FULL) +#define spmmc_wait_rxbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTAT= US_RX_DATA_BUF_FULL) +#define spmmc_wait_txbuf_empty(host) spmmc_wait_sdstatus(host, SPMMC_SDSTA= TUS_TX_DATA_BUF_EMPTY) + +static void spmmc_get_rsp(struct spmmc_host *host, struct mmc_command *cmd) +{ + u32 value0_3, value4_5; + + if (!(cmd->flags & MMC_RSP_PRESENT)) + return; + if (cmd->flags & MMC_RSP_136) { + if (spmmc_wait_rspbuf_full(host)) + return; + value0_3 =3D readl(host->base + SPMMC_SD_RSPBUF0_3_REG); + value4_5 =3D readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; + cmd->resp[0] =3D (value0_3 << 8) | (value4_5 >> 8); + cmd->resp[1] =3D value4_5 << 24; + value0_3 =3D readl(host->base + SPMMC_SD_RSPBUF0_3_REG); + value4_5 =3D readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; + cmd->resp[1] |=3D value0_3 >> 8; + cmd->resp[2] =3D value0_3 << 24; + cmd->resp[2] |=3D value4_5 << 8; + value0_3 =3D readl(host->base + SPMMC_SD_RSPBUF0_3_REG); + value4_5 =3D readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; + cmd->resp[2] |=3D value0_3 >> 24; + cmd->resp[3] =3D value0_3 << 8; + cmd->resp[3] |=3D value4_5 >> 8; + } else { + if (spmmc_wait_rspbuf_full(host)) + return; + value0_3 =3D readl(host->base + SPMMC_SD_RSPBUF0_3_REG); + value4_5 =3D readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff; + cmd->resp[0] =3D (value0_3 << 8) | (value4_5 >> 8); + cmd->resp[1] =3D value4_5 << 24; + } +} + +static void spmmc_set_bus_clk(struct spmmc_host *host, int clk) +{ + unsigned int clkdiv; + int f_min =3D host->mmc->f_min; + int f_max =3D host->mmc->f_max; + u32 value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + + if (clk < f_min) + clk =3D f_min; + if (clk > f_max) + clk =3D f_max; + + clkdiv =3D (clk_get_rate(host->clk) + clk) / clk - 1; + if (clkdiv > 0xfff) + clkdiv =3D 0xfff; + value &=3D ~SPMMC_CLOCK_DIVISION; + value |=3D FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv); + writel(value, host->base + SPMMC_SD_CONFIG0_REG); +} + +static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int tim= ing) +{ + u32 value =3D readl(host->base + SPMMC_SD_CONFIG1_REG); + int clkdiv =3D FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_S= D_CONFIG0_REG)); + int delay =3D clkdiv / 2 < 7 ? clkdiv / 2 : 7; + int hs_en =3D 1, ddr_enabled =3D 0; + + switch (timing) { + case MMC_TIMING_LEGACY: + hs_en =3D 0; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR50: + case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_MMC_HS200: + hs_en =3D 1; + break; + case MMC_TIMING_UHS_DDR50: + ddr_enabled =3D 1; + break; + case MMC_TIMING_MMC_DDR52: + ddr_enabled =3D 1; + break; + default: + hs_en =3D 0; + break; + } + + if (hs_en) { + value |=3D SPMMC_SD_HIGH_SPEED_EN; + writel(value, host->base + SPMMC_SD_CONFIG1_REG); + value =3D readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); + value &=3D ~SPMMC_SD_WRITE_DATA_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, delay); + value &=3D ~SPMMC_SD_WRITE_COMMAND_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, delay); + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); + } else { + value &=3D ~SPMMC_SD_HIGH_SPEED_EN; + writel(value, host->base + SPMMC_SD_CONFIG1_REG); + } + if (ddr_enabled) { + value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + value |=3D SPMMC_SD_DDR_MODE; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); + } else { + value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + value &=3D ~SPMMC_SD_DDR_MODE; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); + } +} + +static void spmmc_set_bus_width(struct spmmc_host *host, int width) +{ + u32 value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + + switch (width) { + case MMC_BUS_WIDTH_8: + value &=3D ~SPMMC_SD_DATA_WD; + value |=3D SPMMC_MMC8_EN; + break; + case MMC_BUS_WIDTH_4: + value |=3D SPMMC_SD_DATA_WD; + value &=3D ~SPMMC_MMC8_EN; + break; + default: + value &=3D ~SPMMC_SD_DATA_WD; + value &=3D ~SPMMC_MMC8_EN; + break; + }; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); +} + +/* + * select the working mode of controller: sd/sdio/emmc + */ +static void spmmc_set_sdmmc_mode(struct spmmc_host *host) +{ + u32 value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + + value |=3D SPMMC_SD_MMC_MODE; + value &=3D ~SPMMC_SDIO_MODE; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); +} + +static void spmmc_sw_reset(struct spmmc_host *host) +{ + u32 value; + + /* + * Must reset dma operation first, or it will + * be stuck on sd_state =3D=3D 0x1c00 because of + * a controller software reset bug + */ + value =3D readl(host->base + SPMMC_HW_DMA_CTRL_REG); + value |=3D SPMMC_DMAIDLE; + writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); + value &=3D ~SPMMC_DMAIDLE; + writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); + value =3D readl(host->base + SPMMC_HW_DMA_CTRL_REG); + value |=3D SPMMC_HW_DMA_RST; + writel(value, host->base + SPMMC_HW_DMA_CTRL_REG); + writel(0x7, host->base + SPMMC_SD_RST_REG); + readl_poll_timeout_atomic(host->base + SPMMC_SD_HW_STATE_REG, value, + !(value & BIT(6)), 1, SPMMC_TIMEOUT); +} + +static void spmmc_prepare_cmd(struct spmmc_host *host, struct mmc_command = *cmd) +{ + u32 value; + + /* add start bit, according to spec, command format */ + value =3D ((cmd->opcode | 0x40) << 24) | (cmd->arg >> 8); + writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG); + writeb(cmd->arg & 0xff, host->base + SPMMC_SD_CMDBUF4_REG); + + /* disable interrupt if needed */ + value =3D readl(host->base + SPMMC_SD_INT_REG); + value |=3D SPMMC_SDINT_SDCMPCLR; + value &=3D ~SPMMC_SDINT_SDCMPEN; + writel(value, host->base + SPMMC_SD_INT_REG); + + value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + value &=3D ~SPMMC_SD_TRANS_MODE; + value |=3D SPMMC_SD_CMD_DUMMY; + if (cmd->flags & MMC_RSP_PRESENT) { + value |=3D SPMMC_SD_AUTO_RESPONSE; + } else { + value &=3D ~SPMMC_SD_AUTO_RESPONSE; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); + + return; + } + /* + * Currently, host is not capable of checking R2's CRC7, + * thus, enable crc7 check only for 48 bit response commands + */ + if (cmd->flags & MMC_RSP_CRC && !(cmd->flags & MMC_RSP_136)) + value |=3D SPMMC_SD_RSP_CHK_EN; + else + value &=3D ~SPMMC_SD_RSP_CHK_EN; + + if (cmd->flags & MMC_RSP_136) + value |=3D SPMMC_SD_RSP_TYPE; + else + value &=3D ~SPMMC_SD_RSP_TYPE; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); +} + +static void spmmc_prepare_data(struct spmmc_host *host, struct mmc_data *d= ata) +{ + u32 value, srcdst; + + writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG); + writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG); + value =3D readl(host->base + SPMMC_SD_CONFIG0_REG); + if (data->flags & MMC_DATA_READ) { + value &=3D ~SPMMC_SD_TRANS_MODE; + value |=3D FIELD_PREP(SPMMC_SD_TRANS_MODE, 2); + value &=3D ~SPMMC_SD_AUTO_RESPONSE; + value &=3D ~SPMMC_SD_CMD_DUMMY; + srcdst =3D readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); + srcdst &=3D ~SPMMC_DMA_SOURCE; + srcdst |=3D FIELD_PREP(SPMMC_DMA_SOURCE, 0x2); + srcdst &=3D ~SPMMC_DMA_DESTINATION; + srcdst |=3D FIELD_PREP(SPMMC_DMA_DESTINATION, 0x1); + writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); + } else { + value &=3D ~SPMMC_SD_TRANS_MODE; + value |=3D FIELD_PREP(SPMMC_SD_TRANS_MODE, 1); + srcdst =3D readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); + srcdst &=3D ~SPMMC_DMA_SOURCE; + srcdst |=3D FIELD_PREP(SPMMC_DMA_SOURCE, 0x1); + srcdst &=3D ~SPMMC_DMA_DESTINATION; + srcdst |=3D FIELD_PREP(SPMMC_DMA_DESTINATION, 0x2); + writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); + } + + value |=3D SPMMC_SD_LEN_MODE; + if (host->dmapio_mode =3D=3D SPMMC_DMA_MODE) { + struct scatterlist *sg; + dma_addr_t dma_addr; + unsigned int dma_size; + u32 *reg_addr; + int i, count =3D 1; + + count =3D dma_map_sg(host->mmc->parent, data->sg, data->sg_len, + mmc_get_dma_dir(data)); + if (!count || count > SPMMC_MAX_DMA_MEMORY_SECTORS) { + data->error =3D -EINVAL; + + return; + } + for_each_sg(data->sg, sg, count, i) { + dma_addr =3D sg_dma_address(sg); + dma_size =3D sg_dma_len(sg) / data->blksz - 1; + if (i =3D=3D 0) { + writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG); + writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG); + } else { + reg_addr =3D host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG + (i - 1) * 2; + writel(dma_addr, reg_addr); + writel(dma_size, reg_addr + 1); + } + } + value &=3D ~SPMMC_SD_PIO_MODE; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); + /* enable interrupt if needed */ + if (data->blksz * data->blocks > host->dma_int_threshold) { + host->dma_use_int =3D 1; + value =3D readl(host->base + SPMMC_SD_INT_REG); + value &=3D ~SPMMC_SDINT_SDCMPEN; + value |=3D FIELD_PREP(SPMMC_SDINT_SDCMPEN, 1); /* sdcmpen */ + writel(value, host->base + SPMMC_SD_INT_REG); + } + } else { + value |=3D SPMMC_SD_PIO_MODE; + value |=3D SPMMC_RX4_EN; + writel(value, host->base + SPMMC_SD_CONFIG0_REG); + } +} + +static inline void spmmc_trigger_transaction(struct spmmc_host *host) +{ + u32 value =3D readl(host->base + SPMMC_SD_CTRL_REG); + + value |=3D SPMMC_NEW_COMMAND_TRIGGER; + writel(value, host->base + SPMMC_SD_CTRL_REG); +} + +static void spmmc_send_stop_cmd(struct spmmc_host *host) +{ + struct mmc_command stop =3D {}; + u32 value; + + stop.opcode =3D MMC_STOP_TRANSMISSION; + stop.arg =3D 0; + stop.flags =3D MMC_RSP_R1B; + spmmc_prepare_cmd(host, &stop); + value =3D readl(host->base + SPMMC_SD_INT_REG); + value &=3D ~SPMMC_SDINT_SDCMPEN; + value |=3D FIELD_PREP(SPMMC_SDINT_SDCMPEN, 0); + writel(value, host->base + SPMMC_SD_INT_REG); + spmmc_trigger_transaction(host); + readl_poll_timeout_atomic(host->base + SPMMC_SD_STATE_REG, value, + (value & SPMMC_SDSTATE_FINISH), 1, SPMMC_TIMEOUT); +} + +static int spmmc_check_error(struct spmmc_host *host, struct mmc_request *= mrq) +{ + int ret =3D 0; + struct mmc_command *cmd =3D mrq->cmd; + struct mmc_data *data =3D mrq->data; + + u32 value =3D readl(host->base + SPMMC_SD_STATE_REG); + u32 crc_token =3D FIELD_GET(SPMMC_CRCTOKEN_CHECK_RESULT, value); + + if (value & SPMMC_SDSTATE_ERROR) { + u32 timing_cfg0 =3D 0; + + value =3D readl(host->base + SPMMC_SD_STATUS_REG); + + if (host->tuning_info.enable_tuning) { + timing_cfg0 =3D readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); + host->tuning_info.rd_crc_dly =3D FIELD_GET(SPMMC_SD_READ_CRC_DELAY, + timing_cfg0); + host->tuning_info.rd_dat_dly =3D FIELD_GET(SPMMC_SD_READ_DATA_DELAY, + timing_cfg0); + host->tuning_info.rd_rsp_dly =3D FIELD_GET(SPMMC_SD_READ_RESPONSE_DELAY, + timing_cfg0); + host->tuning_info.wr_cmd_dly =3D FIELD_GET(SPMMC_SD_WRITE_COMMAND_DELAY, + timing_cfg0); + host->tuning_info.wr_dat_dly =3D FIELD_GET(SPMMC_SD_WRITE_DATA_DELAY, + timing_cfg0); + } + + if (value & SPMMC_SDSTATUS_RSP_TIMEOUT) { + ret =3D -ETIMEDOUT; + host->tuning_info.wr_cmd_dly++; + } else if (value & SPMMC_SDSTATUS_RSP_CRC7_ERROR) { + ret =3D -EILSEQ; + host->tuning_info.rd_rsp_dly++; + } else if (data) { + if ((value & SPMMC_SDSTATUS_STB_TIMEOUT)) { + ret =3D -ETIMEDOUT; + host->tuning_info.rd_dat_dly++; + } else if (value & SPMMC_SDSTATUS_RDATA_CRC16_ERROR) { + ret =3D -EILSEQ; + host->tuning_info.rd_dat_dly++; + } else if (value & SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT) { + ret =3D -ETIMEDOUT; + host->tuning_info.rd_crc_dly++; + } else if (value & SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR) { + ret =3D -EILSEQ; + if (crc_token =3D=3D 0x5) + host->tuning_info.wr_dat_dly++; + else + host->tuning_info.rd_crc_dly++; + } + } + cmd->error =3D ret; + if (data) { + data->error =3D ret; + data->bytes_xfered =3D 0; + } + if (!host->tuning_info.need_tuning && host->tuning_info.enable_tuning) + cmd->retries =3D SPMMC_MAX_RETRIES; + spmmc_sw_reset(host); + + if (host->tuning_info.enable_tuning) { + timing_cfg0 &=3D ~SPMMC_SD_READ_CRC_DELAY; + timing_cfg0 |=3D FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, + host->tuning_info.rd_crc_dly); + timing_cfg0 &=3D ~SPMMC_SD_READ_DATA_DELAY; + timing_cfg0 |=3D FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, + host->tuning_info.rd_dat_dly); + timing_cfg0 &=3D ~SPMMC_SD_READ_RESPONSE_DELAY; + timing_cfg0 |=3D FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, + host->tuning_info.rd_rsp_dly); + timing_cfg0 &=3D ~SPMMC_SD_WRITE_COMMAND_DELAY; + timing_cfg0 |=3D FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, + host->tuning_info.wr_cmd_dly); + timing_cfg0 &=3D ~SPMMC_SD_WRITE_DATA_DELAY; + timing_cfg0 |=3D FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, + host->tuning_info.wr_dat_dly); + writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG); + } + } else if (data) { + data->error =3D 0; + data->bytes_xfered =3D data->blocks * data->blksz; + } + host->tuning_info.need_tuning =3D ret; + + return ret; +} + +/* + * the strategy is: + * 1. if several continuous delays are acceptable, we choose a middle one; + * 2. otherwise, we choose the first one. + */ +static inline int __find_best_delay(u8 candidate_dly) +{ + int f, w, value; + + if (!candidate_dly) + return 0; + f =3D ffs(candidate_dly) - 1; + w =3D hweight8(candidate_dly); + value =3D ((1 << w) - 1) << f; + if (0xff =3D=3D (value & ~candidate_dly)) + return (f + w / 2); + else + return (f); +} + +static void spmmc_xfer_data_pio(struct spmmc_host *host, struct mmc_data *= data) +{ + u32 *buf; + int data_left =3D data->blocks * data->blksz; + int consumed, remain; + + struct sg_mapping_iter sg_miter; + unsigned int flags =3D 0; + + if (data->flags & MMC_DATA_WRITE) + flags |=3D SG_MITER_FROM_SG; + else + flags |=3D SG_MITER_TO_SG; + sg_miter_start(&sg_miter, data->sg, data->sg_len, flags); + while (data_left > 0) { + consumed =3D 0; + if (!sg_miter_next(&sg_miter)) + break; + buf =3D sg_miter.addr; + remain =3D sg_miter.length; + do { + if (data->flags & MMC_DATA_WRITE) { + if (spmmc_wait_txbuf_empty(host)) + goto done; + writel(*buf, host->base + SPMMC_SD_PIODATATX_REG); + } else { + if (spmmc_wait_rxbuf_full(host)) + goto done; + *buf =3D readl(host->base + SPMMC_SD_PIODATARX_REG); + } + buf++; + /* tx/rx 4 bytes one time in pio mode */ + consumed +=3D 4; + remain -=3D 4; + } while (remain); + sg_miter.consumed =3D consumed; + data_left -=3D consumed; + } +done: + sg_miter_stop(&sg_miter); +} + +static void spmmc_controller_init(struct spmmc_host *host) +{ + u32 value; + int ret =3D reset_control_assert(host->rstc); + + if (!ret) { + usleep_range(1000, 1250); + ret =3D reset_control_deassert(host->rstc); + } + + value =3D readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); + value &=3D ~SPMMC_MEDIA_TYPE; + value |=3D FIELD_PREP(SPMMC_MEDIA_TYPE, SPMMC_MEDIA_SD); + writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG); +} + +/* + * 1. unmap scatterlist if needed; + * 2. get response & check error conditions; + * 3. notify mmc layer the request is done + */ +static void spmmc_finish_request(struct spmmc_host *host, struct mmc_reque= st *mrq) +{ + struct mmc_command *cmd; + struct mmc_data *data; + + if (!mrq) + return; + + cmd =3D mrq->cmd; + data =3D mrq->data; + + if (data && SPMMC_DMA_MODE =3D=3D host->dmapio_mode) { + dma_unmap_sg(host->mmc->parent, data->sg, data->sg_len, mmc_get_dma_dir(= data)); + host->dma_use_int =3D 0; + } + + spmmc_get_rsp(host, cmd); + spmmc_check_error(host, mrq); + if (mrq->stop) + spmmc_send_stop_cmd(host); + + host->mrq =3D NULL; + mmc_request_done(host->mmc, mrq); +} + +/* Interrupt Service Routine */ +static irqreturn_t spmmc_irq(int irq, void *dev_id) +{ + struct spmmc_host *host =3D dev_id; + u32 value =3D readl(host->base + SPMMC_SD_INT_REG); + + spin_lock(&host->lock); + if ((value & SPMMC_SDINT_SDCMP) && (value & SPMMC_SDINT_SDCMPEN)) { + value &=3D ~SPMMC_SDINT_SDCMPEN; + value |=3D SPMMC_SDINT_SDCMPCLR; + writel(value, host->base + SPMMC_SD_INT_REG); + spmmc_finish_request(host, host->mrq); + } + spin_unlock(&host->lock); + + return IRQ_HANDLED; +} + +static void spmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct spmmc_host *host =3D mmc_priv(mmc); + struct mmc_data *data; + struct mmc_command *cmd; + + host->mrq =3D mrq; + data =3D mrq->data; + cmd =3D mrq->cmd; + + spmmc_prepare_cmd(host, cmd); + /* we need manually read response R2. */ + if (cmd->flags & MMC_RSP_136) { + spmmc_trigger_transaction(host); + spmmc_get_rsp(host, cmd); + spmmc_wait_finish(host); + spmmc_check_error(host, mrq); + host->mrq =3D NULL; + mmc_request_done(host->mmc, mrq); + } else { + if (data) + spmmc_prepare_data(host, data); + + if (host->dmapio_mode =3D=3D SPMMC_PIO_MODE && data) { + u32 value; + /* pio data transfer do not use interrupt */ + value =3D readl(host->base + SPMMC_SD_INT_REG); + value &=3D ~SPMMC_SDINT_SDCMPEN; + writel(value, host->base + SPMMC_SD_INT_REG); + spmmc_trigger_transaction(host); + spmmc_xfer_data_pio(host, data); + spmmc_wait_finish(host); + spmmc_finish_request(host, mrq); + } else { + if (host->dma_use_int) { + spmmc_trigger_transaction(host); + } else { + spmmc_trigger_transaction(host); + spmmc_wait_finish(host); + spmmc_finish_request(host, mrq); + } + } + } +} + +static void spmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct spmmc_host *host =3D (struct spmmc_host *)mmc_priv(mmc); + + spmmc_set_bus_clk(host, ios->clock); + spmmc_set_bus_timing(host, ios->timing); + spmmc_set_bus_width(host, ios->bus_width); + /* ensure mode is correct, because we might have hw reset the controller = */ + spmmc_set_sdmmc_mode(host); +} + +/* + * Return values for the get_cd callback should be: + * 0 for a absent card + * 1 for a present card + * -ENOSYS when not supported (equal to NULL callback) + * or a negative errno value when something bad happened + */ +static int spmmc_get_cd(struct mmc_host *mmc) +{ + int ret =3D 0; + + if (mmc_can_gpio_cd(mmc)) + ret =3D mmc_gpio_get_cd(mmc); + + if (ret < 0) + ret =3D 0; + + return ret; +} + +static int spmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) +{ + struct spmmc_host *host =3D mmc_priv(mmc); + u8 smpl_dly =3D 0, candidate_dly =3D 0; + u32 value; + + host->tuning_info.enable_tuning =3D 0; + do { + value =3D readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); + value &=3D ~SPMMC_SD_READ_RESPONSE_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly); + value &=3D ~SPMMC_SD_READ_DATA_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly); + value &=3D ~SPMMC_SD_READ_CRC_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly); + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); + + if (!mmc_send_tuning(mmc, opcode, NULL)) { + candidate_dly |=3D (1 << smpl_dly); + break; + } + } while (smpl_dly++ <=3D SPMMC_MAX_TUNABLE_DLY); + host->tuning_info.enable_tuning =3D 1; + + if (candidate_dly) { + smpl_dly =3D __find_best_delay(candidate_dly); + value =3D readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG); + value &=3D ~SPMMC_SD_READ_RESPONSE_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly); + value &=3D ~SPMMC_SD_READ_DATA_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly); + value &=3D ~SPMMC_SD_READ_CRC_DELAY; + value |=3D FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly); + writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG); + return 0; + } + + return -EIO; +} + +static const struct mmc_host_ops spmmc_ops =3D { + .request =3D spmmc_request, + .set_ios =3D spmmc_set_ios, + .get_cd =3D spmmc_get_cd, + .execute_tuning =3D spmmc_execute_tuning, +}; + +static irqreturn_t spmmc_func_finish_req(int irq, void *dev_id) +{ + struct spmmc_host *host =3D dev_id; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + spmmc_finish_request(host, host->mrq); + spin_unlock_irqrestore(&host->lock, flags); + + return IRQ_HANDLED; +} + +static int spmmc_drv_probe(struct platform_device *pdev) +{ + struct mmc_host *mmc; + struct resource *res; + struct spmmc_host *host; + int ret =3D 0; + + mmc =3D mmc_alloc_host(sizeof(*host), &pdev->dev); + if (!mmc) { + ret =3D -ENOMEM; + goto probe_free_host; + } + + host =3D mmc_priv(mmc); + host->mmc =3D mmc; + host->dmapio_mode =3D SPMMC_DMA_MODE; + host->dma_int_threshold =3D 1024; + + host->base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(host->base)) + return PTR_ERR(host->base); + + host->clk =3D devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(host->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "clk get fail\n"); + + host->rstc =3D devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(host->rstc)) + return dev_err_probe(&pdev->dev, PTR_ERR(host->rstc), "rst get fail\n"); + + host->irq =3D platform_get_irq(pdev, 0); + if (host->irq <=3D 0) + return host->irq; + + ret =3D devm_request_threaded_irq(&pdev->dev, host->irq, + spmmc_irq, spmmc_func_finish_req, IRQF_SHARED, + NULL, host); + if (ret) + return ret; + + ret =3D clk_prepare_enable(host->clk); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to enable clk\n"); + + ret =3D mmc_of_parse(mmc); + if (ret) + goto probe_free_host; + + spin_lock_init(&host->lock); + mmc->ops =3D &spmmc_ops; + mmc->f_min =3D SPMMC_MIN_CLK; + if (mmc->f_max > SPMMC_MAX_CLK) + mmc->f_max =3D SPMMC_MAX_CLK; + + ret =3D mmc_regulator_get_supply(mmc); + if (ret) + goto probe_free_host; + + if (!mmc->ocr_avail) + mmc->ocr_avail =3D MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->max_seg_size =3D SPMMC_MAX_BLK_COUNT * 512; + mmc->max_segs =3D SPMMC_MAX_DMA_MEMORY_SECTORS; + mmc->max_req_size =3D SPMMC_MAX_BLK_COUNT * 512; + mmc->max_blk_size =3D 512; + mmc->max_blk_count =3D SPMMC_MAX_BLK_COUNT; + + dev_set_drvdata(&pdev->dev, host); + spmmc_controller_init(host); + spmmc_set_sdmmc_mode(host); + host->tuning_info.enable_tuning =3D 1; + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + mmc_add_host(mmc); + + return ret; + +probe_free_host: + if (mmc) + mmc_free_host(mmc); + + return ret; +} + +static int spmmc_drv_remove(struct platform_device *dev) +{ + struct spmmc_host *host =3D platform_get_drvdata(dev); + + mmc_remove_host(host->mmc); + pm_runtime_get_sync(&dev->dev); + clk_disable_unprepare(host->clk); + pm_runtime_put_noidle(&dev->dev); + pm_runtime_disable(&dev->dev); + platform_set_drvdata(dev, NULL); + mmc_free_host(host->mmc); + + return 0; +} + +static int spmmc_pm_runtime_suspend(struct device *dev) +{ + struct spmmc_host *host; + + host =3D dev_get_drvdata(dev); + clk_disable_unprepare(host->clk); + + return 0; +} + +static int spmmc_pm_runtime_resume(struct device *dev) +{ + struct spmmc_host *host; + + host =3D dev_get_drvdata(dev); + + return clk_prepare_enable(host->clk); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(spmmc_pm_ops, spmmc_pm_runtime_suspend, + spmmc_pm_runtime_resume, NULL); + +static const struct of_device_id spmmc_of_table[] =3D { + { + .compatible =3D "sunplus,sp7021-mmc", + }, + {/* sentinel */} +}; +MODULE_DEVICE_TABLE(of, spmmc_of_table); + +static struct platform_driver spmmc_driver =3D { + .probe =3D spmmc_drv_probe, + .remove =3D spmmc_drv_remove, + .driver =3D { + .name =3D "spmmc", + .pm =3D pm_ptr(&spmmc_pm_ops), + .of_match_table =3D spmmc_of_table, + }, +}; +module_platform_driver(spmmc_driver); + +MODULE_AUTHOR("Tony Huang "); +MODULE_AUTHOR("Li-hao Kuo "); +MODULE_DESCRIPTION("Sunplus MMC controller driver"); +MODULE_LICENSE("GPL"); --=20 2.7.4