From nobody Tue Dec 16 10:48:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9C66ECAAA1 for ; Mon, 5 Sep 2022 07:54:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237043AbiIEHyX (ORCPT ); Mon, 5 Sep 2022 03:54:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237001AbiIEHyN (ORCPT ); Mon, 5 Sep 2022 03:54:13 -0400 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EC164505E for ; Mon, 5 Sep 2022 00:54:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1662364381; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UNXvlVjo187MWu3yoYckcXbqqs1lHNuMO52iCAYBAu8=; b=ZGMiSiy4gQaJYliigo/Y/nEdwmaKWrxQLwwt1iSyqlFjWFFy3FLBL+wlVSyYqIs/WEpYus 3a3xHsJWZ0ZYaZ9zdHnddZNSuLMy5TqcnWB1Scup5fUidaDzoB+m7DGDHV7A+H25twFR1B k87S0sK+afZRyx93CD3QuoroMZpLTNooMoT2SMMRD2JcHnLhv2WbUEaXIMSFGqjKWDp6jE 3gK7OT+b9EADUmGArcC4qfZnjVV1KCwGDIFJYG+1qGViAL+Pdcu+25/DhbHvIYGw0RfBb5 qcFpvG9tq9r3rHYSzeOZ4fypL34jJBUy6umPHo3vC+wPMAoLrkyfrx6C4Npv4w== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-292-9FJ67FUwNnqjlk24SeUneg-1; Mon, 05 Sep 2022 03:43:57 -0400 X-MC-Unique: 9FJ67FUwNnqjlk24SeUneg-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Mon, 5 Sep 2022 00:43:54 -0700 From: Rahul Tanwar To: , , CC: , , "Rahul Tanwar" Subject: [PATCH v2 1/5] clk: mxl: Switch from direct readl/writel based IO to regmap based IO Date: Mon, 5 Sep 2022 15:43:44 +0800 Message-ID: <43c6a8ac66b5f7acfb99f919f9c3088a80b55175.1662363020.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Earlier version of driver used direct io remapped register read writes using readl/writel. But we need secure boot access which is only possible when registers are read & written using regmap. This is because the security bus/hook is written & coupled only with regmap layer. Switch the driver from direct readl/writel based register accesses to regmap based register accesses. Additionally, update the license headers to latest status. Signed-off-by: Rahul Tanwar --- drivers/clk/x86/Kconfig | 5 +++-- drivers/clk/x86/clk-cgu-pll.c | 10 +++++---- drivers/clk/x86/clk-cgu.c | 5 +++-- drivers/clk/x86/clk-cgu.h | 38 +++++++++++++++++++---------------- drivers/clk/x86/clk-lgm.c | 13 ++++++++---- 5 files changed, 42 insertions(+), 29 deletions(-) diff --git a/drivers/clk/x86/Kconfig b/drivers/clk/x86/Kconfig index 69642e15fcc1..ced99e082e3d 100644 --- a/drivers/clk/x86/Kconfig +++ b/drivers/clk/x86/Kconfig @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only config CLK_LGM_CGU depends on OF && HAS_IOMEM && (X86 || COMPILE_TEST) + select MFD_SYSCON select OF_EARLY_FLATTREE bool "Clock driver for Lightning Mountain(LGM) platform" help - Clock Generation Unit(CGU) driver for Intel Lightning Mountain(LGM) - network processor SoC. + Clock Generation Unit(CGU) driver for MaxLinear's x86 based + Lightning Mountain(LGM) network processor SoC. diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c index 3179557b5f78..c83083affe88 100644 --- a/drivers/clk/x86/clk-cgu-pll.c +++ b/drivers/clk/x86/clk-cgu-pll.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. - * Zhu YiXin - * Rahul Tanwar + * Zhu Yixin + * Rahul Tanwar */ =20 #include @@ -76,8 +77,9 @@ static int lgm_pll_enable(struct clk_hw *hw) =20 spin_lock_irqsave(&pll->lock, flags); lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); - ret =3D readl_poll_timeout_atomic(pll->membase + pll->reg, - val, (val & 0x1), 1, 100); + ret =3D regmap_read_poll_timeout_atomic(pll->membase, pll->reg, + val, (val & 0x1), 1, 100); + spin_unlock_irqrestore(&pll->lock, flags); =20 return ret; diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index 33de600e0c38..f5f30a18f486 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. - * Zhu YiXin - * Rahul Tanwar + * Zhu Yixin + * Rahul Tanwar */ #include #include diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index 4e22bfb22312..dbcb66468797 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -1,18 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright(c) 2020 Intel Corporation. - * Zhu YiXin - * Rahul Tanwar + * Copyright (C) 2020-2022 MaxLinear, Inc. + * Copyright (C) 2020 Intel Corporation. + * Zhu Yixin + * Rahul Tanwar */ =20 #ifndef __CLK_CGU_H #define __CLK_CGU_H =20 -#include +#include =20 struct lgm_clk_mux { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift; u8 width; @@ -22,7 +23,7 @@ struct lgm_clk_mux { =20 struct lgm_clk_divider { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift; u8 width; @@ -35,7 +36,7 @@ struct lgm_clk_divider { =20 struct lgm_clk_ddiv { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift0; u8 width0; @@ -53,7 +54,7 @@ struct lgm_clk_ddiv { =20 struct lgm_clk_gate { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; u8 shift; unsigned long flags; @@ -77,7 +78,7 @@ enum lgm_clk_type { * @clk_data: array of hw clocks and clk number. */ struct lgm_clk_provider { - void __iomem *membase; + struct regmap *membase; struct device_node *np; struct device *dev; struct clk_hw_onecell_data clk_data; @@ -92,7 +93,7 @@ enum pll_type { =20 struct lgm_clk_pll { struct clk_hw hw; - void __iomem *membase; + struct regmap *membase; unsigned int reg; unsigned long flags; enum pll_type type; @@ -300,29 +301,32 @@ struct lgm_clk_branch { .div =3D _d, \ } =20 -static inline void lgm_set_clk_val(void __iomem *membase, u32 reg, +static inline void lgm_set_clk_val(struct regmap *membase, u32 reg, u8 shift, u8 width, u32 set_val) { u32 mask =3D (GENMASK(width - 1, 0) << shift); - u32 regval; =20 - regval =3D readl(membase + reg); - regval =3D (regval & ~mask) | ((set_val << shift) & mask); - writel(regval, membase + reg); + regmap_update_bits(membase, reg, mask, set_val << shift); } =20 -static inline u32 lgm_get_clk_val(void __iomem *membase, u32 reg, +static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg, u8 shift, u8 width) { u32 mask =3D (GENMASK(width - 1, 0) << shift); u32 val; =20 - val =3D readl(membase + reg); + if (regmap_read(membase, reg, &val)) { + WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg); + return 0; + } + val =3D (val & mask) >> shift; =20 return val; } =20 + + int lgm_clk_register_branches(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list, unsigned int nr_clk); diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c index 020f4e83a5cc..4fa2bcaf71c8 100644 --- a/drivers/clk/x86/clk-lgm.c +++ b/drivers/clk/x86/clk-lgm.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* + * Copyright (C) 2020-2022 MaxLinear, Inc. * Copyright (C) 2020 Intel Corporation. - * Zhu YiXin - * Rahul Tanwar + * Zhu Yixin + * Rahul Tanwar */ #include +#include #include #include #include @@ -433,9 +435,12 @@ static int lgm_cgu_probe(struct platform_device *pdev) =20 ctx->clk_data.num =3D CLK_NR_CLKS; =20 - ctx->membase =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(ctx->membase)) + ctx->membase =3D syscon_node_to_regmap(np); + if (IS_ERR_OR_NULL(ctx->membase)) { + dev_err(dev, "Failed to get clk CGU iomem\n"); return PTR_ERR(ctx->membase); + } + =20 ctx->np =3D np; ctx->dev =3D dev; --=20 2.17.1 From nobody Tue Dec 16 10:48:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B84AECAAA1 for ; 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Mon, 05 Sep 2022 03:44:00 -0400 X-MC-Unique: vspEF-c2PFW8EEfyPL0Edg-2 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Mon, 5 Sep 2022 00:43:57 -0700 From: Rahul Tanwar To: , , CC: , , "Rahul Tanwar" Subject: [PATCH v2 2/5] clk: mxl: Remove unnecessary spinlocks Date: Mon, 5 Sep 2022 15:43:45 +0800 Message-ID: <2602fd05fff85bd35925c1103fc07d128cffb5b1.1662363020.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver is now switched from direct readl/writel based register access to regmap based register acceess. Regmap already has its own lock to serialize the register accesses across multiple cores. Hence, there is no need for additional spinlocks in the driver. Remove all spinlocks which are no longer required. Signed-off-by: Rahul Tanwar --- drivers/clk/x86/clk-cgu-pll.c | 13 ------ drivers/clk/x86/clk-cgu.c | 80 ++++------------------------------- drivers/clk/x86/clk-cgu.h | 6 --- drivers/clk/x86/clk-lgm.c | 1 - 4 files changed, 9 insertions(+), 91 deletions(-) diff --git a/drivers/clk/x86/clk-cgu-pll.c b/drivers/clk/x86/clk-cgu-pll.c index c83083affe88..409dbf55f4ca 100644 --- a/drivers/clk/x86/clk-cgu-pll.c +++ b/drivers/clk/x86/clk-cgu-pll.c @@ -41,13 +41,10 @@ static unsigned long lgm_pll_recalc_rate(struct clk_hw = *hw, unsigned long prate) { struct lgm_clk_pll *pll =3D to_lgm_clk_pll(hw); unsigned int div, mult, frac; - unsigned long flags; =20 - spin_lock_irqsave(&pll->lock, flags); mult =3D lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); div =3D lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); frac =3D lgm_get_clk_val(pll->membase, pll->reg, 2, 24); - spin_unlock_irqrestore(&pll->lock, flags); =20 if (pll->type =3D=3D TYPE_LJPLL) div *=3D 4; @@ -58,12 +55,9 @@ static unsigned long lgm_pll_recalc_rate(struct clk_hw *= hw, unsigned long prate) static int lgm_pll_is_enabled(struct clk_hw *hw) { struct lgm_clk_pll *pll =3D to_lgm_clk_pll(hw); - unsigned long flags; unsigned int ret; =20 - spin_lock_irqsave(&pll->lock, flags); ret =3D lgm_get_clk_val(pll->membase, pll->reg, 0, 1); - spin_unlock_irqrestore(&pll->lock, flags); =20 return ret; } @@ -71,16 +65,13 @@ static int lgm_pll_is_enabled(struct clk_hw *hw) static int lgm_pll_enable(struct clk_hw *hw) { struct lgm_clk_pll *pll =3D to_lgm_clk_pll(hw); - unsigned long flags; u32 val; int ret; =20 - spin_lock_irqsave(&pll->lock, flags); lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 1); ret =3D regmap_read_poll_timeout_atomic(pll->membase, pll->reg, val, (val & 0x1), 1, 100); =20 - spin_unlock_irqrestore(&pll->lock, flags); =20 return ret; } @@ -88,11 +79,8 @@ static int lgm_pll_enable(struct clk_hw *hw) static void lgm_pll_disable(struct clk_hw *hw) { struct lgm_clk_pll *pll =3D to_lgm_clk_pll(hw); - unsigned long flags; =20 - spin_lock_irqsave(&pll->lock, flags); lgm_set_clk_val(pll->membase, pll->reg, 0, 1, 0); - spin_unlock_irqrestore(&pll->lock, flags); } =20 static const struct clk_ops lgm_pll_ops =3D { @@ -123,7 +111,6 @@ lgm_clk_register_pll(struct lgm_clk_provider *ctx, return ERR_PTR(-ENOMEM); =20 pll->membase =3D ctx->membase; - pll->lock =3D ctx->lock; pll->reg =3D list->reg; pll->flags =3D list->flags; pll->type =3D list->type; diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index f5f30a18f486..1f7e93de67bc 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -25,14 +25,10 @@ static struct clk_hw *lgm_clk_register_fixed(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags; =20 - if (list->div_flags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&ctx->lock, flags); + if (list->div_flags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, list->div_width, list->div_val); - spin_unlock_irqrestore(&ctx->lock, flags); - } =20 return clk_hw_register_fixed_rate(NULL, list->name, list->parent_data[0].name, @@ -42,33 +38,27 @@ static struct clk_hw *lgm_clk_register_fixed(struct lgm= _clk_provider *ctx, static u8 lgm_clk_mux_get_parent(struct clk_hw *hw) { struct lgm_clk_mux *mux =3D to_lgm_clk_mux(hw); - unsigned long flags; u32 val; =20 - spin_lock_irqsave(&mux->lock, flags); if (mux->flags & MUX_CLK_SW) val =3D mux->reg; else val =3D lgm_get_clk_val(mux->membase, mux->reg, mux->shift, mux->width); - spin_unlock_irqrestore(&mux->lock, flags); return clk_mux_val_to_index(hw, NULL, mux->flags, val); } =20 static int lgm_clk_mux_set_parent(struct clk_hw *hw, u8 index) { struct lgm_clk_mux *mux =3D to_lgm_clk_mux(hw); - unsigned long flags; u32 val; =20 val =3D clk_mux_index_to_val(NULL, mux->flags, index); - spin_lock_irqsave(&mux->lock, flags); if (mux->flags & MUX_CLK_SW) mux->reg =3D val; else lgm_set_clk_val(mux->membase, mux->reg, mux->shift, mux->width, val); - spin_unlock_irqrestore(&mux->lock, flags); =20 return 0; } @@ -91,7 +81,7 @@ static struct clk_hw * lgm_clk_register_mux(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags, cflags =3D list->mux_flags; + unsigned long cflags =3D list->mux_flags; struct device *dev =3D ctx->dev; u8 shift =3D list->mux_shift; u8 width =3D list->mux_width; @@ -112,7 +102,6 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx, init.num_parents =3D list->num_parents; =20 mux->membase =3D ctx->membase; - mux->lock =3D ctx->lock; mux->reg =3D reg; mux->shift =3D shift; mux->width =3D width; @@ -124,11 +113,8 @@ lgm_clk_register_mux(struct lgm_clk_provider *ctx, if (ret) return ERR_PTR(ret); =20 - if (cflags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&mux->lock, flags); + if (cflags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); - spin_unlock_irqrestore(&mux->lock, flags); - } =20 return hw; } @@ -137,13 +123,10 @@ static unsigned long lgm_clk_divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct lgm_clk_divider *divider =3D to_lgm_clk_divider(hw); - unsigned long flags; unsigned int val; =20 - spin_lock_irqsave(÷r->lock, flags); val =3D lgm_get_clk_val(divider->membase, divider->reg, divider->shift, divider->width); - spin_unlock_irqrestore(÷r->lock, flags); =20 return divider_recalc_rate(hw, parent_rate, val, divider->table, divider->flags, divider->width); @@ -164,7 +147,6 @@ lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned lo= ng rate, unsigned long prate) { struct lgm_clk_divider *divider =3D to_lgm_clk_divider(hw); - unsigned long flags; int value; =20 value =3D divider_get_val(rate, prate, divider->table, @@ -172,10 +154,8 @@ lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned l= ong rate, if (value < 0) return value; =20 - spin_lock_irqsave(÷r->lock, flags); lgm_set_clk_val(divider->membase, divider->reg, divider->shift, divider->width, value); - spin_unlock_irqrestore(÷r->lock, flags); =20 return 0; } @@ -183,12 +163,9 @@ lgm_clk_divider_set_rate(struct clk_hw *hw, unsigned l= ong rate, static int lgm_clk_divider_enable_disable(struct clk_hw *hw, int enable) { struct lgm_clk_divider *div =3D to_lgm_clk_divider(hw); - unsigned long flags; =20 - spin_lock_irqsave(&div->lock, flags); lgm_set_clk_val(div->membase, div->reg, div->shift_gate, div->width_gate, enable); - spin_unlock_irqrestore(&div->lock, flags); return 0; } =20 @@ -214,7 +191,7 @@ static struct clk_hw * lgm_clk_register_divider(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags, cflags =3D list->div_flags; + unsigned long cflags =3D list->div_flags; struct device *dev =3D ctx->dev; struct lgm_clk_divider *div; struct clk_init_data init =3D {}; @@ -237,7 +214,6 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx, init.num_parents =3D 1; =20 div->membase =3D ctx->membase; - div->lock =3D ctx->lock; div->reg =3D reg; div->shift =3D shift; div->width =3D width; @@ -252,11 +228,8 @@ lgm_clk_register_divider(struct lgm_clk_provider *ctx, if (ret) return ERR_PTR(ret); =20 - if (cflags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&div->lock, flags); + if (cflags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(div->membase, reg, shift, width, list->div_val); - spin_unlock_irqrestore(&div->lock, flags); - } =20 return hw; } @@ -265,7 +238,6 @@ static struct clk_hw * lgm_clk_register_fixed_factor(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags; struct clk_hw *hw; =20 hw =3D clk_hw_register_fixed_factor(ctx->dev, list->name, @@ -274,12 +246,9 @@ lgm_clk_register_fixed_factor(struct lgm_clk_provider = *ctx, if (IS_ERR(hw)) return ERR_CAST(hw); =20 - if (list->div_flags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&ctx->lock, flags); + if (list->div_flags & CLOCK_FLAG_VAL_INIT) lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, list->div_width, list->div_val); - spin_unlock_irqrestore(&ctx->lock, flags); - } =20 return hw; } @@ -287,13 +256,10 @@ lgm_clk_register_fixed_factor(struct lgm_clk_provider= *ctx, static int lgm_clk_gate_enable(struct clk_hw *hw) { struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); - unsigned long flags; unsigned int reg; =20 - spin_lock_irqsave(&gate->lock, flags); reg =3D GATE_HW_REG_EN(gate->reg); lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); - spin_unlock_irqrestore(&gate->lock, flags); =20 return 0; } @@ -301,25 +267,19 @@ static int lgm_clk_gate_enable(struct clk_hw *hw) static void lgm_clk_gate_disable(struct clk_hw *hw) { struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); - unsigned long flags; unsigned int reg; =20 - spin_lock_irqsave(&gate->lock, flags); reg =3D GATE_HW_REG_DIS(gate->reg); lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); - spin_unlock_irqrestore(&gate->lock, flags); } =20 static int lgm_clk_gate_is_enabled(struct clk_hw *hw) { struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg, ret; - unsigned long flags; =20 - spin_lock_irqsave(&gate->lock, flags); reg =3D GATE_HW_REG_STAT(gate->reg); ret =3D lgm_get_clk_val(gate->membase, reg, gate->shift, 1); - spin_unlock_irqrestore(&gate->lock, flags); =20 return ret; } @@ -334,7 +294,7 @@ static struct clk_hw * lgm_clk_register_gate(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list) { - unsigned long flags, cflags =3D list->gate_flags; + unsigned long cflags =3D list->gate_flags; const char *pname =3D list->parent_data[0].name; struct device *dev =3D ctx->dev; u8 shift =3D list->gate_shift; @@ -355,7 +315,6 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, init.num_parents =3D pname ? 1 : 0; =20 gate->membase =3D ctx->membase; - gate->lock =3D ctx->lock; gate->reg =3D reg; gate->shift =3D shift; gate->flags =3D cflags; @@ -367,9 +326,7 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, return ERR_PTR(ret); =20 if (cflags & CLOCK_FLAG_VAL_INIT) { - spin_lock_irqsave(&gate->lock, flags); lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); - spin_unlock_irqrestore(&gate->lock, flags); } =20 return hw; @@ -444,24 +401,18 @@ lgm_clk_ddiv_recalc_rate(struct clk_hw *hw, unsigned = long parent_rate) static int lgm_clk_ddiv_enable(struct clk_hw *hw) { struct lgm_clk_ddiv *ddiv =3D to_lgm_clk_ddiv(hw); - unsigned long flags; =20 - spin_lock_irqsave(&ddiv->lock, flags); lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate, ddiv->width_gate, 1); - spin_unlock_irqrestore(&ddiv->lock, flags); return 0; } =20 static void lgm_clk_ddiv_disable(struct clk_hw *hw) { struct lgm_clk_ddiv *ddiv =3D to_lgm_clk_ddiv(hw); - unsigned long flags; =20 - spin_lock_irqsave(&ddiv->lock, flags); lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift_gate, ddiv->width_gate, 0); - spin_unlock_irqrestore(&ddiv->lock, flags); } =20 static int @@ -498,32 +449,25 @@ lgm_clk_ddiv_set_rate(struct clk_hw *hw, unsigned lon= g rate, { struct lgm_clk_ddiv *ddiv =3D to_lgm_clk_ddiv(hw); u32 div, ddiv1, ddiv2; - unsigned long flags; =20 div =3D DIV_ROUND_CLOSEST_ULL((u64)prate, rate); =20 - spin_lock_irqsave(&ddiv->lock, flags); if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { div =3D DIV_ROUND_CLOSEST_ULL((u64)div, 5); div =3D div * 2; } =20 - if (div <=3D 0) { - spin_unlock_irqrestore(&ddiv->lock, flags); + if (div <=3D 0) return -EINVAL; - } =20 - if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2)) { - spin_unlock_irqrestore(&ddiv->lock, flags); + if (lgm_clk_get_ddiv_val(div, &ddiv1, &ddiv2)) return -EINVAL; - } =20 lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift0, ddiv->width0, ddiv1 - 1); =20 lgm_set_clk_val(ddiv->membase, ddiv->reg, ddiv->shift1, ddiv->width1, ddiv2 - 1); - spin_unlock_irqrestore(&ddiv->lock, flags); =20 return 0; } @@ -534,18 +478,15 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned l= ong rate, { struct lgm_clk_ddiv *ddiv =3D to_lgm_clk_ddiv(hw); u32 div, ddiv1, ddiv2; - unsigned long flags; u64 rate64; =20 div =3D DIV_ROUND_CLOSEST_ULL((u64)*prate, rate); =20 /* if predivide bit is enabled, modify div by factor of 2.5 */ - spin_lock_irqsave(&ddiv->lock, flags); if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { div =3D div * 2; div =3D DIV_ROUND_CLOSEST_ULL((u64)div, 5); } - spin_unlock_irqrestore(&ddiv->lock, flags); =20 if (div <=3D 0) return *prate; @@ -559,12 +500,10 @@ lgm_clk_ddiv_round_rate(struct clk_hw *hw, unsigned l= ong rate, do_div(rate64, ddiv2); =20 /* if predivide bit is enabled, modify rounded rate by factor of 2.5 */ - spin_lock_irqsave(&ddiv->lock, flags); if (lgm_get_clk_val(ddiv->membase, ddiv->reg, ddiv->shift2, 1)) { rate64 =3D rate64 * 2; rate64 =3D DIV_ROUND_CLOSEST_ULL(rate64, 5); } - spin_unlock_irqrestore(&ddiv->lock, flags); =20 return rate64; } @@ -601,7 +540,6 @@ int lgm_clk_register_ddiv(struct lgm_clk_provider *ctx, init.num_parents =3D 1; =20 ddiv->membase =3D ctx->membase; - ddiv->lock =3D ctx->lock; ddiv->reg =3D list->reg; ddiv->shift0 =3D list->shift0; ddiv->width0 =3D list->width0; diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index dbcb66468797..0aa0f35d63a0 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -18,7 +18,6 @@ struct lgm_clk_mux { u8 shift; u8 width; unsigned long flags; - spinlock_t lock; }; =20 struct lgm_clk_divider { @@ -31,7 +30,6 @@ struct lgm_clk_divider { u8 width_gate; unsigned long flags; const struct clk_div_table *table; - spinlock_t lock; }; =20 struct lgm_clk_ddiv { @@ -49,7 +47,6 @@ struct lgm_clk_ddiv { unsigned int mult; unsigned int div; unsigned long flags; - spinlock_t lock; }; =20 struct lgm_clk_gate { @@ -58,7 +55,6 @@ struct lgm_clk_gate { unsigned int reg; u8 shift; unsigned long flags; - spinlock_t lock; }; =20 enum lgm_clk_type { @@ -82,7 +78,6 @@ struct lgm_clk_provider { struct device_node *np; struct device *dev; struct clk_hw_onecell_data clk_data; - spinlock_t lock; }; =20 enum pll_type { @@ -97,7 +92,6 @@ struct lgm_clk_pll { unsigned int reg; unsigned long flags; enum pll_type type; - spinlock_t lock; }; =20 /** diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c index 4fa2bcaf71c8..e312af42e97a 100644 --- a/drivers/clk/x86/clk-lgm.c +++ b/drivers/clk/x86/clk-lgm.c @@ -444,7 +444,6 @@ static int lgm_cgu_probe(struct platform_device *pdev) =20 ctx->np =3D np; ctx->dev =3D dev; - spin_lock_init(&ctx->lock); =20 ret =3D lgm_clk_register_plls(ctx, lgm_pll_clks, ARRAY_SIZE(lgm_pll_clks)); --=20 2.17.1 From nobody Tue Dec 16 10:48:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C87ECAAD5 for ; Mon, 5 Sep 2022 07:55:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237001AbiIEHzN (ORCPT ); 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Mon, 05 Sep 2022 03:44:03 -0400 X-MC-Unique: xdhXJq8hOTmBhXYhWCcCPw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Mon, 5 Sep 2022 00:43:59 -0700 From: Rahul Tanwar To: , , CC: , , "Rahul Tanwar" Subject: [PATCH v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver Date: Mon, 5 Sep 2022 15:43:46 +0800 Message-ID: <496372f326760be1b997ae2aabd1999627f7376d.1662363020.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled from EPU (power management IP) in certain power saving modes. If gate clocks are allowed to be enabled/disabled from CGU clk driver, then there arises a conflict where in case clk driver disables a gate clk, and then EPU tries to disable the same gate clk, then it will hang polling for the clk gated successful status. To avoid such a conflict, disable gate clocks enabling/disabling from CGU clk driver. But add a GATE_CLK_HW flag to control this in order to be backward compatible with other SoCs which share the same CGU IP but not the same EPU IP. Signed-off-by: Rahul Tanwar --- drivers/clk/x86/clk-cgu.c | 32 ++++++++++++++++++++++++-------- drivers/clk/x86/clk-cgu.h | 1 + 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index 1f7e93de67bc..d24173cfe0b0 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -258,8 +258,12 @@ static int lgm_clk_gate_enable(struct clk_hw *hw) struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg; =20 - reg =3D GATE_HW_REG_EN(gate->reg); - lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + if (gate->flags & GATE_CLK_HW) { + reg =3D GATE_HW_REG_EN(gate->reg); + lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + } else { + gate->reg =3D 1; + } =20 return 0; } @@ -269,8 +273,12 @@ static void lgm_clk_gate_disable(struct clk_hw *hw) struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg; =20 - reg =3D GATE_HW_REG_DIS(gate->reg); - lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + if (gate->flags & GATE_CLK_HW) { + reg =3D GATE_HW_REG_DIS(gate->reg); + lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + } else { + gate->reg =3D 0; + } } =20 static int lgm_clk_gate_is_enabled(struct clk_hw *hw) @@ -278,8 +286,12 @@ static int lgm_clk_gate_is_enabled(struct clk_hw *hw) struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg, ret; =20 - reg =3D GATE_HW_REG_STAT(gate->reg); - ret =3D lgm_get_clk_val(gate->membase, reg, gate->shift, 1); + if (gate->flags & GATE_CLK_HW) { + reg =3D GATE_HW_REG_STAT(gate->reg); + ret =3D lgm_get_clk_val(gate->membase, reg, gate->shift, 1); + } else { + ret =3D gate->reg; + } =20 return ret; } @@ -315,7 +327,8 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, init.num_parents =3D pname ? 1 : 0; =20 gate->membase =3D ctx->membase; - gate->reg =3D reg; + if (cflags & GATE_CLK_HW) + gate->reg =3D reg; gate->shift =3D shift; gate->flags =3D cflags; gate->hw.init =3D &init; @@ -326,7 +339,10 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, return ERR_PTR(ret); =20 if (cflags & CLOCK_FLAG_VAL_INIT) { - lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); + if (cflags & GATE_CLK_HW) + lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); + else + gate->reg =3D 1; } =20 return hw; diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index 0aa0f35d63a0..73ce84345f81 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -197,6 +197,7 @@ struct lgm_clk_branch { /* clock flags definition */ #define CLOCK_FLAG_VAL_INIT BIT(16) #define MUX_CLK_SW BIT(17) +#define GATE_CLK_HW BIT(18) =20 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ _shift, _width, _cf, _v) \ --=20 2.17.1 From nobody Tue Dec 16 10:48:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5931BECAAA1 for ; Mon, 5 Sep 2022 07:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236417AbiIEHxH (ORCPT ); Mon, 5 Sep 2022 03:53:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236058AbiIEHxD (ORCPT ); Mon, 5 Sep 2022 03:53:03 -0400 X-Greylist: delayed 346 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 05 Sep 2022 00:53:02 PDT Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.129.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4240913CDC for ; Mon, 5 Sep 2022 00:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1662364381; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=m+UK/3xmvV65NQU0nckZ1VWPUugzCRzrBeOVEtHB3BM=; b=gmgunwUWUBAu8zuRyXzOtUua3D7bN4yBkVVgxo/++XljQ51NzPEqFwJhqsZepV4Y49RjNR Urwwjg+iLwf/JOolesYooIUE3QWzTjspppW2OocsmZ0ZAnYDbr2MeSQP9mI4n+XR2GmEfd dWSpkmPBzUNpy+JwwgHGHBgO9tLHYl2tbucYRc/09wJ4ygQDd0igysUSKZd4b8bQ3HZrQq NV8vHBamJI8c36BtCAog0CTG6vYyAIe/aGLmOxwAeyMVvBYeeQvmmES1DM5FHaTAPnLddY vMMVOUHjufLUKnL6hXhae9Vnb3DhdcyGmMNyNXx8GgNlXIGD5uqJfdIxVRaozw== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-230-8p819PzjPSCMsQ4KzKoqSg-1; Mon, 05 Sep 2022 03:44:05 -0400 X-MC-Unique: 8p819PzjPSCMsQ4KzKoqSg-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Mon, 5 Sep 2022 00:44:02 -0700 From: Rahul Tanwar To: , , CC: , , "Rahul Tanwar" Subject: [PATCH v2 4/5] clk: mxl: Add validation for register reads/writes Date: Mon, 5 Sep 2022 15:43:47 +0800 Message-ID: <09c3b98ba9f74719b02e1b5153c3e639cb8d34ca.1662363020.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some clocks support parent clock dividers but they do not support clock gating (clk enable/disable). Such types of clocks might call API's for get/set_reg_val routines with width as 0 during clk_prepare_enable() call. Handle such cases by first validating width during clk_prepare_enable() while still supporting clk_set_rate() correctly. Signed-off-by: Rahul Tanwar --- drivers/clk/x86/clk-cgu.h | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index 73ce84345f81..46daf9ebd6c9 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -299,29 +299,51 @@ struct lgm_clk_branch { static inline void lgm_set_clk_val(struct regmap *membase, u32 reg, u8 shift, u8 width, u32 set_val) { - u32 mask =3D (GENMASK(width - 1, 0) << shift); + u32 mask; =20 + /* + * Some clocks support parent clock dividers but they do not + * support clock gating (clk enable/disable). Such types of + * clocks might call this function with width as 0 during + * clk_prepare_enable() call. Handle such cases by not doing + * anything during clk_prepare_enable() but handle clk_set_rate() + * correctly + */ + if (!width) + return; + + mask =3D (GENMASK(width - 1, 0) << shift); regmap_update_bits(membase, reg, mask, set_val << shift); } =20 static inline u32 lgm_get_clk_val(struct regmap *membase, u32 reg, u8 shift, u8 width) { - u32 mask =3D (GENMASK(width - 1, 0) << shift); + u32 mask; u32 val; =20 + /* + * Some clocks support parent clock dividers but they do not + * support clock gating (clk enable/disable). Such types of + * clocks might call this function with width as 0 during + * clk_prepare_enable() call. Handle such cases by not doing + * anything during clk_prepare_enable() but handle clk_set_rate() + * correctly + */ + if (!width) + return 0; + if (regmap_read(membase, reg, &val)) { WARN_ONCE(1, "Failed to read clk reg: 0x%x\n", reg); return 0; } =20 + mask =3D (GENMASK(width - 1, 0) << shift); val =3D (val & mask) >> shift; =20 return val; } =20 - - int lgm_clk_register_branches(struct lgm_clk_provider *ctx, const struct lgm_clk_branch *list, unsigned int nr_clk); --=20 2.17.1 From nobody Tue Dec 16 10:48:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F119ECAAA1 for ; Mon, 5 Sep 2022 07:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237069AbiIEHzW (ORCPT ); Mon, 5 Sep 2022 03:55:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235698AbiIEHzI (ORCPT ); Mon, 5 Sep 2022 03:55:08 -0400 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E5AD11C25 for ; Mon, 5 Sep 2022 00:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1662364501; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BtUJUYZOy4dsKmtYSOJkIch/jexIUqRsQ+FbLNIyJJQ=; b=HvvjpPNYr6G2Rg53atVCceL0cWusJNbrtwFjF2G5ko0pnAp41yA8up0Vwq9UmtdEzvE4xr pL/xXI8woEf+/m+NhAezPe7W4OW6drCdEsRUZqTI7u4V/dxr4sgFsonuKrrqo66jOgcnG+ RpkI3K7XQpvWNToYGjK2vFTN3/pG3t14TywMdWEyf2qrKkxow8f/DpNrf+Pweb9k23zCiQ RNz5K62VAQQs+JgX16i/itTNxe5duBuocCZBmzVt5K4XiXuz5uikpfnd82iJDB4oDSYRf9 3EE4R8L2rZubCxT3X7qPbabWxE5HQ2/4QkXMBNdU6GDKrIk1ZbTsS4DOlTaiGQ== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-78-H49kdtHfNy6Rs7NwcPrkMA-1; Mon, 05 Sep 2022 03:44:08 -0400 X-MC-Unique: H49kdtHfNy6Rs7NwcPrkMA-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Mon, 5 Sep 2022 00:44:05 -0700 From: Rahul Tanwar To: , , CC: , , "Rahul Tanwar" Subject: [PATCH v2 5/5] clk: mxl: Add a missing flag to allow parent clock rate change Date: Mon, 5 Sep 2022 15:43:48 +0800 Message-ID: <112a3d6f959fdb14a853897fe4b171d50eab7e55.1662363020.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" One of the clock entry "dcl" clk's rate can only be changed by changing its parent's clock rate. But it was missing to have CLK_SET_RATE_PARENT flag as enabled. Add/enable CLK_SET_RATE_PARENT flag for dcl clk in order to allow its clk rate to be changed via its parent's clk. Signed-off-by: Rahul Tanwar --- drivers/clk/x86/clk-lgm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c index e312af42e97a..34e16ea90596 100644 --- a/drivers/clk/x86/clk-lgm.c +++ b/drivers/clk/x86/clk-lgm.c @@ -255,7 +255,7 @@ static const struct lgm_clk_branch lgm_branch_clks[] = =3D { LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1, 8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2), LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0), - LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR, + LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR, 25, 3, 0, 0, 0, 0, dcl_div), LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR, 0, 1, CLK_MUX_ROUND_CLOSEST, 0), --=20 2.17.1