From nobody Sat Apr 18 14:08:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5E31C433EF for ; Wed, 13 Jul 2022 06:53:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234366AbiGMGx1 (ORCPT ); Wed, 13 Jul 2022 02:53:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234329AbiGMGxS (ORCPT ); Wed, 13 Jul 2022 02:53:18 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FDCEE0F43 for ; Tue, 12 Jul 2022 23:53:13 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id 89-20020a17090a09e200b001ef7638e536so2098828pjo.3 for ; Tue, 12 Jul 2022 23:53:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T+FjPu7CEqaUGA6dxu9j75NgS+pDMgasoBPZEY/Bx7k=; b=cYYSIeYjXyC4rOlRSy9otHxWGaGXrKaKc9UWGl6Sy9rOnCdzfM2DCRQsfX/gBwcGUK 3M3estnxsHdKoxhk3gq6DQpQMhwq9kd/wx5rjobfW1vFa+lv9n/Vx4WpWxcD2Gqx4z53 4LZ85rOe81sI31zna5LCxxC8Ghjow0AASSDWBP/L86in7wArTg/9BybWEbUz14YSbt6Z 59kXI5GBv/4pUIc7MewQBk1GkraxyOKs6kMMyHvokZu0rAZMw1xfgZI5nXZHpUfHhbsW X0JmQVn+5G3INxq7fAQR23crw2TJ95UKDTzPyOfj1V4JobgN0XZA0bvOt5G/eiIiO6Gp CRtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T+FjPu7CEqaUGA6dxu9j75NgS+pDMgasoBPZEY/Bx7k=; b=siPyGObEh+KqBpj3kZ2LIcvu4Ki1y3zsfaDkdGKpRgG0qATTW5798ONtAKmmecXDdZ rMhvrf8myKCy0lr4J6EIxTQKlv+qG94HESBD+JpByY8tRdYofG7zn52l2GKQKAqV6cFQ cKgWLt/TPMu4imeFEOxYgoJO5ySpQsu6hrutnVl4HP/5U/hvsj8TCSq8bqnafQcGPaAN YZlfyLJR2EB/dstqDITH6c76YSpi8/Rh5Q4MfBygO/WW5EFz91zWi9rUEQPA84KMhBTa nIUFfKzySGRpT4ppJX7wmLKEAk/13dq8TpH8eLso9mDrfIaX3Wuwe7NcY7DxP1xcXtX5 OoVQ== X-Gm-Message-State: AJIora9WbL3mzHamBCmUlgzEPqY8BGWmAacBrvCLGagf1R8PjBt2YuCg YFHONFtygLkS98dBNgIeJVVDSw== X-Google-Smtp-Source: AGRyM1vmdjxZHvTZxuwKbMysmWcTakqw7XDsOepkHN5uT1Wo8RRxsHlUMzGkSjnB/ALTdBEKWw/ilw== X-Received: by 2002:a17:903:41cd:b0:16b:f00c:5927 with SMTP id u13-20020a17090341cd00b0016bf00c5927mr1729670ple.49.1657695192984; Tue, 12 Jul 2022 23:53:12 -0700 (PDT) Received: from localhost ([122.171.18.80]) by smtp.gmail.com with ESMTPSA id 70-20020a621549000000b0050dc76281d3sm8141359pfv.173.2022.07.12.23.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 23:53:12 -0700 (PDT) From: Viresh Kumar To: Bjorn Andersson , Manivannan Sadhasivam , Andy Gross , "Rafael J. Wysocki" , Viresh Kumar Cc: Vincent Guittot , Johan Hovold , Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/4] dt-bindings: cpufreq-qcom-hw: Move clocks to CPU nodes Date: Wed, 13 Jul 2022 12:22:56 +0530 Message-Id: <035fe13689dad6d3867a1d33f7d5e91d4637d14a.1657695140.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" cpufreq-hw is a hardware engine, which takes care of frequency management for CPUs. The engine manages the clocks for CPU devices, but it isn't the end consumer of the clocks, which are the CPUs in this case. For this reason, it looks incorrect to keep the clock related properties in the cpufreq-hw node. They should really be present at the end user, i.e. the CPUs. The case was simple currently as all the devices, i.e. the CPUs, that the engine manages share the same clock names. What if the clock names are different for different CPUs or clusters ? How will keeping the clock properties in the cpufreq-hw node work in that case ? This design creates further problems for frameworks like OPP, which expects all such details (clocks) to be present in the end device node itself, instead of another related node. Move the clocks properties to the node that uses them instead. Signed-off-by: Viresh Kumar --- .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 2f1b8b6852a0..2ef4eeeca9b9 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -42,24 +42,12 @@ description: | - const: freq-domain1 - const: freq-domain2 =20 - clocks: - items: - - description: XO Clock - - description: GPLL0 Clock - - clock-names: - items: - - const: xo - - const: alternate - '#freq-domain-cells': const: 1 =20 required: - compatible - reg - - clocks - - clock-names - '#freq-domain-cells' =20 additionalProperties: false @@ -81,6 +69,8 @@ additionalProperties: false reg =3D <0x0 0x0>; enable-method =3D "psci"; next-level-cache =3D <&L2_0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; @@ -97,6 +87,8 @@ additionalProperties: false reg =3D <0x0 0x100>; enable-method =3D "psci"; next-level-cache =3D <&L2_100>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; @@ -110,6 +102,8 @@ additionalProperties: false reg =3D <0x0 0x200>; enable-method =3D "psci"; next-level-cache =3D <&L2_200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; @@ -123,6 +117,8 @@ additionalProperties: false reg =3D <0x0 0x300>; enable-method =3D "psci"; next-level-cache =3D <&L2_300>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; @@ -136,6 +132,8 @@ additionalProperties: false reg =3D <0x0 0x400>; enable-method =3D "psci"; next-level-cache =3D <&L2_400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; @@ -149,6 +147,8 @@ additionalProperties: false reg =3D <0x0 0x500>; enable-method =3D "psci"; next-level-cache =3D <&L2_500>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; @@ -162,6 +162,8 @@ additionalProperties: false reg =3D <0x0 0x600>; enable-method =3D "psci"; next-level-cache =3D <&L2_600>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; @@ -175,6 +177,8 @@ additionalProperties: false reg =3D <0x0 0x700>; enable-method =3D "psci"; next-level-cache =3D <&L2_700>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; L2_700: l2-cache { compatible =3D "cache"; @@ -192,9 +196,6 @@ additionalProperties: false reg =3D <0x17d43000 0x1400>, <0x17d45800 0x1400>; reg-names =3D "freq-domain0", "freq-domain1"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; - #freq-domain-cells =3D <1>; }; }; --=20 2.31.1.272.g89b43f80a514 From nobody Sat Apr 18 14:08:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34A37C433EF for ; Wed, 13 Jul 2022 06:53:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234430AbiGMGxa (ORCPT ); Wed, 13 Jul 2022 02:53:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234364AbiGMGxU (ORCPT ); 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Tue, 12 Jul 2022 23:53:16 -0700 (PDT) From: Viresh Kumar To: Bjorn Andersson , Manivannan Sadhasivam , Andy Gross , Rob Herring , Krzysztof Kozlowski Cc: Viresh Kumar , Vincent Guittot , Johan Hovold , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/4] arm64: dts: qcom: Move clocks to CPU nodes Date: Wed, 13 Jul 2022 12:22:57 +0530 Message-Id: <25855e87505d1969fb3fba3661cbf31e44cb2747.1657695140.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The clock specific properties must be part the consumer nodes, i.e. the CPUs here, instead of the node that manages the frequency engine. Move the clocks properties to the CPU node instead. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++++++++++++++++-- arch/arm64/boot/dts/qcom/sdm845.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++++++++++++++-- arch/arm64/boot/dts/qcom/sm8150.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/qcom/sm8250.dtsi | 18 ++++++++++++++++-- arch/arm64/boot/dts/qcom/sm8350.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 ++++++++++++++++-- 8 files changed, 128 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qco= m/sc7180.dtsi index 5dcaac23a138..4c9a5f5e4ab4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -138,6 +138,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -164,6 +166,8 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; next-level-cache =3D <&L2_100>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -186,6 +190,8 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; next-level-cache =3D <&L2_200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -208,6 +214,8 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; next-level-cache =3D <&L2_300>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -230,6 +238,8 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; next-level-cache =3D <&L2_400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -252,6 +262,8 @@ &LITTLE_CPU_SLEEP_1 capacity-dmips-mhz =3D <415>; dynamic-power-coefficient =3D <137>; next-level-cache =3D <&L2_500>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -274,6 +286,8 @@ &BIG_CPU_SLEEP_1 capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <480>; next-level-cache =3D <&L2_600>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -296,6 +310,8 @@ &BIG_CPU_SLEEP_1 capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <480>; next-level-cache =3D <&L2_700>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu6_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -3538,9 +3554,6 @@ cpufreq_hw: cpufreq@18323000 { reg =3D <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; reg-names =3D "freq-domain0", "freq-domain1"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; - #freq-domain-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index e66fc67de206..f7600dbdd1e1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -172,6 +172,8 @@ CPU0: cpu@0 { &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -195,6 +197,8 @@ CPU1: cpu@100 { &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_100>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -215,6 +219,8 @@ CPU2: cpu@200 { &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -235,6 +241,8 @@ CPU3: cpu@300 { &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_300>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -255,6 +263,8 @@ CPU4: cpu@400 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -275,6 +285,8 @@ CPU5: cpu@500 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_500>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -295,6 +307,8 @@ CPU6: cpu@600 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_600>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -315,6 +329,8 @@ CPU7: cpu@700 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; next-level-cache =3D <&L2_700>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; @@ -4915,8 +4931,6 @@ cpufreq_hw: cpufreq@18591000 { reg =3D <0 0x18591000 0 0x1000>, <0 0x18592000 0 0x1000>, <0 0x18593000 0 0x1000>; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names =3D "xo", "alternate"; #freq-domain-cells =3D <1>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qco= m/sdm845.dtsi index 0692ae0e60a4..3154a8f67f76 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -202,6 +202,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz =3D <611>; dynamic-power-coefficient =3D <290>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -227,6 +229,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz =3D <611>; dynamic-power-coefficient =3D <290>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -249,6 +253,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz =3D <611>; dynamic-power-coefficient =3D <290>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -271,6 +277,8 @@ &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; capacity-dmips-mhz =3D <611>; dynamic-power-coefficient =3D <290>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -293,6 +301,8 @@ CPU4: cpu@400 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; dynamic-power-coefficient =3D <442>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -315,6 +325,8 @@ CPU5: cpu@500 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; dynamic-power-coefficient =3D <442>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -337,6 +349,8 @@ CPU6: cpu@600 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; dynamic-power-coefficient =3D <442>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -359,6 +373,8 @@ CPU7: cpu@700 { &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; dynamic-power-coefficient =3D <442>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EB= I1 3>, @@ -5022,9 +5038,6 @@ cpufreq_hw: cpufreq@17d43000 { =20 interrupts-extended =3D <&lmh_cluster0 0>, <&lmh_cluster1 0>; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; - #freq-domain-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qco= m/sm6350.dtsi index d4f8f33f3f0c..645fb73fdad2 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -43,6 +43,8 @@ CPU0: cpu@0 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&L2_0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_0: l2-cache { @@ -62,6 +64,8 @@ CPU1: cpu@100 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&L2_100>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_100: l2-cache { @@ -78,6 +82,8 @@ CPU2: cpu@200 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&L2_200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_200: l2-cache { @@ -94,6 +100,8 @@ CPU3: cpu@300 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&L2_300>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_300: l2-cache { @@ -110,6 +118,8 @@ CPU4: cpu@400 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&L2_400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_400: l2-cache { @@ -126,6 +136,8 @@ CPU5: cpu@500 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <100>; next-level-cache =3D <&L2_500>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_500: l2-cache { @@ -143,6 +155,8 @@ CPU6: cpu@600 { capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <703>; next-level-cache =3D <&L2_600>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; L2_600: l2-cache { @@ -159,6 +173,8 @@ CPU7: cpu@700 { capacity-dmips-mhz =3D <1894>; dynamic-power-coefficient =3D <703>; next-level-cache =3D <&L2_700>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; L2_700: l2-cache { @@ -1462,8 +1478,6 @@ cpufreq_hw: cpufreq@18323000 { compatible =3D "qcom,cpufreq-hw"; reg =3D <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; reg-names =3D "freq-domain0", "freq-domain1"; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; =20 #freq-domain-cells =3D <1>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 8ea44c4b56b4..bb38e36ae659 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -51,6 +51,8 @@ CPU0: cpu@0 { capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; next-level-cache =3D <&L2_0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -75,6 +77,8 @@ CPU1: cpu@100 { capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; next-level-cache =3D <&L2_100>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -97,6 +101,8 @@ CPU2: cpu@200 { capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; next-level-cache =3D <&L2_200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -118,6 +124,8 @@ CPU3: cpu@300 { capacity-dmips-mhz =3D <488>; dynamic-power-coefficient =3D <232>; next-level-cache =3D <&L2_300>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -139,6 +147,8 @@ CPU4: cpu@400 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <369>; next-level-cache =3D <&L2_400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -160,6 +170,8 @@ CPU5: cpu@500 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <369>; next-level-cache =3D <&L2_500>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -181,6 +193,8 @@ CPU6: cpu@600 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <369>; next-level-cache =3D <&L2_600>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -202,6 +216,8 @@ CPU7: cpu@700 { capacity-dmips-mhz =3D <1024>; dynamic-power-coefficient =3D <421>; next-level-cache =3D <&L2_700>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 2>; operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -4102,9 +4118,6 @@ cpufreq_hw: cpufreq@18323000 { reg-names =3D "freq-domain0", "freq-domain1", "freq-domain2"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; - #freq-domain-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index cf0c97bd5ad3..29c496e85dda 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -101,6 +101,8 @@ CPU0: cpu@0 { next-level-cache =3D <&L2_0>; power-domains =3D <&CPU_PD0>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -125,6 +127,8 @@ CPU1: cpu@100 { next-level-cache =3D <&L2_100>; power-domains =3D <&CPU_PD1>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -146,6 +150,8 @@ CPU2: cpu@200 { next-level-cache =3D <&L2_200>; power-domains =3D <&CPU_PD2>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -167,6 +173,8 @@ CPU3: cpu@300 { next-level-cache =3D <&L2_300>; power-domains =3D <&CPU_PD3>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; operating-points-v2 =3D <&cpu0_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -188,6 +196,8 @@ CPU4: cpu@400 { next-level-cache =3D <&L2_400>; power-domains =3D <&CPU_PD4>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -209,6 +219,8 @@ CPU5: cpu@500 { next-level-cache =3D <&L2_500>; power-domains =3D <&CPU_PD5>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -231,6 +243,8 @@ CPU6: cpu@600 { next-level-cache =3D <&L2_600>; power-domains =3D <&CPU_PD6>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; operating-points-v2 =3D <&cpu4_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -252,6 +266,8 @@ CPU7: cpu@700 { next-level-cache =3D <&L2_700>; power-domains =3D <&CPU_PD7>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 2>; operating-points-v2 =3D <&cpu7_opp_table>; interconnects =3D <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, @@ -5020,8 +5036,6 @@ cpufreq_hw: cpufreq@18591000 { reg-names =3D "freq-domain0", "freq-domain1", "freq-domain2"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; - clock-names =3D "xo", "alternate"; interrupts =3D , , ; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qco= m/sm8350.dtsi index 743cba9b683c..c7e9447f0388 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -66,6 +66,8 @@ CPU0: cpu@0 { reg =3D <0x0 0x0>; enable-method =3D "psci"; next-level-cache =3D <&L2_0>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; power-domains =3D <&CPU_PD0>; power-domain-names =3D "psci"; @@ -85,6 +87,8 @@ CPU1: cpu@100 { reg =3D <0x0 0x100>; enable-method =3D "psci"; next-level-cache =3D <&L2_100>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; power-domains =3D <&CPU_PD1>; power-domain-names =3D "psci"; @@ -101,6 +105,8 @@ CPU2: cpu@200 { reg =3D <0x0 0x200>; enable-method =3D "psci"; next-level-cache =3D <&L2_200>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; power-domains =3D <&CPU_PD2>; power-domain-names =3D "psci"; @@ -117,6 +123,8 @@ CPU3: cpu@300 { reg =3D <0x0 0x300>; enable-method =3D "psci"; next-level-cache =3D <&L2_300>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; power-domains =3D <&CPU_PD3>; power-domain-names =3D "psci"; @@ -133,6 +141,8 @@ CPU4: cpu@400 { reg =3D <0x0 0x400>; enable-method =3D "psci"; next-level-cache =3D <&L2_400>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; power-domains =3D <&CPU_PD4>; power-domain-names =3D "psci"; @@ -149,6 +159,8 @@ CPU5: cpu@500 { reg =3D <0x0 0x500>; enable-method =3D "psci"; next-level-cache =3D <&L2_500>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; power-domains =3D <&CPU_PD5>; power-domain-names =3D "psci"; @@ -166,6 +178,8 @@ CPU6: cpu@600 { reg =3D <0x0 0x600>; enable-method =3D "psci"; next-level-cache =3D <&L2_600>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; power-domains =3D <&CPU_PD6>; power-domain-names =3D "psci"; @@ -182,6 +196,8 @@ CPU7: cpu@700 { reg =3D <0x0 0x700>; enable-method =3D "psci"; next-level-cache =3D <&L2_700>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 2>; power-domains =3D <&CPU_PD7>; power-domain-names =3D "psci"; @@ -2074,9 +2090,6 @@ cpufreq_hw: cpufreq@18591000 { <0 0x18593000 0 0x1000>; reg-names =3D "freq-domain0", "freq-domain1", "freq-domain2"; =20 - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names =3D "xo", "alternate"; - #freq-domain-cells =3D <1>; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 7d08fad76371..229cf5eb6447 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -48,6 +48,8 @@ CPU0: cpu@0 { next-level-cache =3D <&L2_0>; power-domains =3D <&CPU_PD0>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_0: l2-cache { @@ -67,6 +69,8 @@ CPU1: cpu@100 { next-level-cache =3D <&L2_100>; power-domains =3D <&CPU_PD1>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_100: l2-cache { @@ -83,6 +87,8 @@ CPU2: cpu@200 { next-level-cache =3D <&L2_200>; power-domains =3D <&CPU_PD2>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_200: l2-cache { @@ -99,6 +105,8 @@ CPU3: cpu@300 { next-level-cache =3D <&L2_300>; power-domains =3D <&CPU_PD3>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; L2_300: l2-cache { @@ -115,6 +123,8 @@ CPU4: cpu@400 { next-level-cache =3D <&L2_400>; power-domains =3D <&CPU_PD4>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; L2_400: l2-cache { @@ -131,6 +141,8 @@ CPU5: cpu@500 { next-level-cache =3D <&L2_500>; power-domains =3D <&CPU_PD5>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; L2_500: l2-cache { @@ -148,6 +160,8 @@ CPU6: cpu@600 { next-level-cache =3D <&L2_600>; power-domains =3D <&CPU_PD6>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; L2_600: l2-cache { @@ -164,6 +178,8 @@ CPU7: cpu@700 { next-level-cache =3D <&L2_700>; power-domains =3D <&CPU_PD7>; power-domain-names =3D "psci"; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; qcom,freq-domain =3D <&cpufreq_hw 2>; #cooling-cells =3D <2>; L2_700: l2-cache { @@ -2998,8 +3014,6 @@ cpufreq_hw: cpufreq@17d91000 { <0 0x17d92000 0 0x1000>, <0 0x17d93000 0 0x1000>; reg-names =3D "freq-domain0", "freq-domain1", "freq-domain2"; - clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names =3D "xo", "alternate"; interrupts =3D , , ; --=20 2.31.1.272.g89b43f80a514 From nobody Sat Apr 18 14:08:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 108C7C43334 for ; Wed, 13 Jul 2022 06:53:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234459AbiGMGxd (ORCPT ); Wed, 13 Jul 2022 02:53:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234339AbiGMGxW (ORCPT ); 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Tue, 12 Jul 2022 23:53:19 -0700 (PDT) From: Viresh Kumar To: Bjorn Andersson , Manivannan Sadhasivam , Andy Gross , "Rafael J. Wysocki" , Viresh Kumar Cc: Vincent Guittot , Johan Hovold , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 3/4] cpufreq: qcom-cpufreq-hw: Clocks are moved to CPU nodes Date: Wed, 13 Jul 2022 12:22:58 +0530 Message-Id: X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The clocks are not in the cpufreq-hw node anymore, and are moved to the respective CPU nodes. Make changes accordingly here. Signed-off-by: Viresh Kumar --- drivers/cpufreq/qcom-cpufreq-hw.c | 43 +++++++++++++++++-------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 0253731d6d25..05fce4a559ca 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -57,9 +57,10 @@ struct qcom_cpufreq_data { struct cpufreq_policy *policy; =20 bool per_core_dcvs; + unsigned long cpu_hw_rate; + unsigned long xo_rate; }; =20 -static unsigned long cpu_hw_rate, xo_rate; static bool icc_scaling_enabled; =20 static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy, @@ -209,9 +210,9 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_= dev, volt =3D FIELD_GET(LUT_VOLT, data) * 1000; =20 if (src) - freq =3D xo_rate * lval / 1000; + freq =3D drv_data->xo_rate * lval / 1000; else - freq =3D cpu_hw_rate / 1000; + freq =3D drv_data->cpu_hw_rate / 1000; =20 if (freq !=3D prev_freq && core_count !=3D LUT_TURBO_IND) { if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) { @@ -293,7 +294,7 @@ static unsigned long qcom_lmh_get_throttle_freq(struct = qcom_cpufreq_data *data) else lval =3D readl_relaxed(data->base + data->soc_data->reg_domain_state) & = 0xff; =20 - return lval * xo_rate; + return lval * data->xo_rate; } =20 static void qcom_lmh_dcvs_notify(struct qcom_cpufreq_data *data) @@ -480,6 +481,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_poli= cy *policy) struct device_node *cpu_np; struct device *cpu_dev; struct resource *res; + struct clk *clk; void __iomem *base; struct qcom_cpufreq_data *data; int ret, index; @@ -527,6 +529,24 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_pol= icy *policy) goto unmap_base; } =20 + clk =3D clk_get(cpu_dev, "xo"); + if (IS_ERR(clk)) { + ret =3D PTR_ERR(clk); + goto error; + } + + data->xo_rate =3D clk_get_rate(clk); + clk_put(clk); + + clk =3D clk_get(cpu_dev, "alternate"); + if (IS_ERR(clk)) { + ret =3D PTR_ERR(clk); + goto error; + } + + data->cpu_hw_rate =3D clk_get_rate(clk) / CLK_HW_DIV; + clk_put(clk); + data->soc_data =3D of_device_get_match_data(&pdev->dev); data->base =3D base; data->res =3D res; @@ -637,23 +657,8 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = =3D { static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { struct device *cpu_dev; - struct clk *clk; int ret; =20 - clk =3D clk_get(&pdev->dev, "xo"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - xo_rate =3D clk_get_rate(clk); - clk_put(clk); - - clk =3D clk_get(&pdev->dev, "alternate"); - if (IS_ERR(clk)) - return PTR_ERR(clk); - - cpu_hw_rate =3D clk_get_rate(clk) / CLK_HW_DIV; - clk_put(clk); - cpufreq_qcom_hw_driver.driver_data =3D pdev; =20 /* Check for optional interconnect paths on CPU0 */ --=20 2.31.1.272.g89b43f80a514 From nobody Sat Apr 18 14:08:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AC8DC433EF for ; Wed, 13 Jul 2022 06:53:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234481AbiGMGxg (ORCPT ); Wed, 13 Jul 2022 02:53:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234402AbiGMGxX (ORCPT ); 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Tue, 12 Jul 2022 23:53:21 -0700 (PDT) From: Viresh Kumar To: Bjorn Andersson , Manivannan Sadhasivam , Andy Gross , "Rafael J. Wysocki" , Viresh Kumar Cc: Vincent Guittot , Johan Hovold , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 4/4] cpufreq: qcom-cpufreq-hw: Register config_clks helper Date: Wed, 13 Jul 2022 12:22:59 +0530 Message-Id: <5f8db633c179608214c5e17a6927715f7acda993.1657695140.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.31.1.272.g89b43f80a514 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There is a corner case with Qcom, where we want to skip clk configuration that happens via dev_pm_opp_set_opp(), but still want the OPP core to read the "opp-hz" property so we can find the right OPP via freq finding helpers. The OPP core provides support for the platforms to provide config_clks helpers now, lets use that to provide an empty callback to skip clock configuration. The "table" wasn't getting freed properly on error, fix it as well which we are updating the code. Signed-off-by: Viresh Kumar --- drivers/cpufreq/qcom-cpufreq-hw.c | 32 ++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 05fce4a559ca..8d055a5f6575 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -59,6 +59,7 @@ struct qcom_cpufreq_data { bool per_core_dcvs; unsigned long cpu_hw_rate; unsigned long xo_rate; + int opp_token; }; =20 static bool icc_scaling_enabled; @@ -162,6 +163,15 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct= cpufreq_policy *policy, return policy->freq_table[index].frequency; } =20 +static int qcom_cpufreq_hw_config_clks_nop(struct device *dev, + struct opp_table *opp_table, + struct dev_pm_opp *opp, void *data, + bool scaling_down) +{ + /* We want to skip clk configuration via dev_pm_opp_set_opp() */ + return 0; +} + static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev, struct cpufreq_policy *policy) { @@ -173,11 +183,23 @@ static int qcom_cpufreq_hw_read_lut(struct device *cp= u_dev, int ret; struct qcom_cpufreq_data *drv_data =3D policy->driver_data; const struct qcom_cpufreq_soc_data *soc_data =3D drv_data->soc_data; + const char * const clk_names[] =3D { "xo", NULL }; + struct dev_pm_opp_config config =3D { + .clk_names =3D clk_names, + .config_clks =3D qcom_cpufreq_hw_config_clks_nop, + }; =20 table =3D kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) return -ENOMEM; =20 + ret =3D dev_pm_opp_set_config(cpu_dev, &config); + if (ret < 0) { + dev_err(cpu_dev, "Failed to set OPP config: %d\n", ret); + goto free_table; + } + drv_data->opp_token =3D ret; + ret =3D dev_pm_opp_of_add_table(cpu_dev); if (!ret) { /* Disable all opps and cross-validate against LUT later */ @@ -192,7 +214,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_= dev, } } else if (ret !=3D -ENODEV) { dev_err(cpu_dev, "Invalid opp table in device tree\n"); - return ret; + goto clear_config; } else { policy->fast_switch_possible =3D true; icc_scaling_enabled =3D false; @@ -260,6 +282,13 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu= _dev, dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); =20 return 0; + +clear_config: + dev_pm_opp_clear_config(drv_data->opp_token); + +free_table: + kfree(table); + return ret; } =20 static void qcom_get_related_cpus(int index, struct cpumask *m) @@ -614,6 +643,7 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_poli= cy *policy) dev_pm_opp_remove_all_dynamic(cpu_dev); dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); qcom_cpufreq_hw_lmh_exit(data); + dev_pm_opp_clear_config(data->opp_token); kfree(policy->freq_table); kfree(data); iounmap(base); --=20 2.31.1.272.g89b43f80a514