From nobody Sun Apr 19 02:19:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD197C43334 for ; Thu, 7 Jul 2022 22:30:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237053AbiGGWa1 (ORCPT ); Thu, 7 Jul 2022 18:30:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236730AbiGGWaX (ORCPT ); Thu, 7 Jul 2022 18:30:23 -0400 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF94F65D67 for ; Thu, 7 Jul 2022 15:30:21 -0700 (PDT) Received: by mail-qt1-x832.google.com with SMTP id he28so24906620qtb.13 for ; Thu, 07 Jul 2022 15:30:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cp4kFfIV9vxNzkxwPVJY1RIkCxRVw29SgQ0nN5WqYjM=; b=jJNz4QmfJij1m5k1Z3WHbkakIK/EEmazjOfG3VCc25VR3Ml74OCYQ4y1ulHaZfPNao 7WKFNeHCSYyiKJIZ5DxPBPf6QA/DMC7UBXohxvoKjcQaLewy2umh5vP4CQ07irJqcEVX LOjAzOH87+b+lQZPAs75S8ZoFvszBFrPvoaCqNUhGZ8FCCcQ0J1DzJyqiKDM87rLRYBb Aqy1O0jXjy+Qwzzw0f8S0/3nxvf6ZbgSOls+K2iBPKLYUnwkIQA4PJSlt+hw/viG+P2O x1I3kbfiy3YHiidJqDHDilEvV/livKcnNTx5AfoJEYjWXUUzirTyrkmEF6E7cp7Qp0Wu EKxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cp4kFfIV9vxNzkxwPVJY1RIkCxRVw29SgQ0nN5WqYjM=; b=Cj2ixqx1bYrKBVbCGKFHNuFTgelocnotxlyQZdH9ajpUwoysoU9GA2i0hm0KrxB6A+ Zej40wv1FHbFGM1ct8k+E/csZSWjXma00xzF9TrH7tfbiiBNHKlo2IdPZqY5M0y6c1wf KFVrezcZKfOFgPvy7rumAFL+FIy1twfG/D8ivzyFfYR2b4f056pRFuwYr20BfAR/qw2k oUPf5yHEmUFmBundTgCSchGFxoTSPsjn3aPXN/UM0wCgJoPc3RMajRa4/1JYFFwtqHwp H57G4LE9qnN79kXCD74SNdV78v31I0+C7sOVeANQwdHrEJbwrM6DoQkZKDYRVnit0+OM gCVA== X-Gm-Message-State: AJIora/Gc/zL5KkhNdJF3txKZOm+DjksqXHKv/STOVeU37HhM0HjfEY8 pgiQirEZz4hzfIqFIotL5gJc7Q== X-Google-Smtp-Source: AGRyM1tD+9XRXBAxNRSxuANjBn7f6MK39Wmp4MU3un44jgsVmGtk/ufdzQsOFPhp8SlWwyk9bYXc0A== X-Received: by 2002:a05:6214:21ec:b0:470:3f54:e846 with SMTP id p12-20020a05621421ec00b004703f54e846mr328601qvj.58.1657233020932; Thu, 07 Jul 2022 15:30:20 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id e22-20020ac84b56000000b0031e9bd3586esm1527747qts.79.2022.07.07.15.30.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:30:20 -0700 (PDT) From: William Breathitt Gray To: jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray , Fred Eckert Subject: [PATCH v2 1/2] iio: adc: stx104: Implement and utilize register structures Date: Thu, 7 Jul 2022 13:21:24 -0400 Message-Id: <8cb91d5b53e57b066120e42ea07000d6c7ef5543.1657213745.git.william.gray@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. Tested-by: Fred Eckert Signed-off-by: William Breathitt Gray --- drivers/iio/adc/stx104.c | 74 +++++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 7552351bfed9..48a91a95e597 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #define STX104_OUT_CHAN(chan) { \ .type =3D IIO_VOLTAGE, \ @@ -44,14 +45,36 @@ static unsigned int num_stx104; module_param_hw_array(base, uint, ioport, &num_stx104, 0); MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); =20 +/** + * struct stx104_reg - device register structure + * @ssr_ad: Software Strobe Register and ADC Data + * @achan: ADC Channel + * @dio: Digital I/O + * @dac: DAC Channels + * @cir_asr: Clear Interrupts and ADC Status + * @acr: ADC Control + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB + * @acfg: ADC Configuration + */ +struct stx104_reg { + u16 ssr_ad; + u8 achan; + u8 dio; + u16 dac[2]; + u8 cir_asr; + u8 acr; + u8 pccr_fsh; + u8 acfg; +}; + /** * struct stx104_iio - IIO device private data structure * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @reg: I/O address offset for the device registers */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - void __iomem *base; + struct stx104_reg __iomem *reg; }; =20 /** @@ -64,7 +87,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - void __iomem *base; + u8 __iomem *base; unsigned int out_state; }; =20 @@ -72,6 +95,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct stx104_iio *const priv =3D iio_priv(indio_dev); + struct stx104_reg __iomem *const reg =3D priv->reg; unsigned int adc_config; int adbu; int gain; @@ -79,7 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config =3D ioread8(priv->base + 11); + adc_config =3D ioread8(®->acfg); gain =3D adc_config & 0x3; =20 *val =3D 1 << gain; @@ -91,24 +115,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } =20 /* select ADC channel */ - iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), ®->achan); =20 - /* trigger ADC sample capture and wait for completion */ - iowrite8(0, priv->base); - while (ioread8(priv->base + 8) & BIT(7)); + /* trigger ADC sample capture by writing to the 8-bit + * Software Strobe Register and wait for completion + */ + iowrite8(0, ®->ssr_ad); + while (ioread8(®->cir_asr) & BIT(7)); =20 - *val =3D ioread16(priv->base); + *val =3D ioread16(®->ssr_ad); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config =3D ioread8(priv->base + 11); + adc_config =3D ioread8(®->acfg); adbu =3D !(adc_config & BIT(2)); =20 *val =3D -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config =3D ioread8(priv->base + 11); + adc_config =3D ioread8(®->acfg); adbu =3D !(adc_config & BIT(2)); gain =3D adc_config & 0x3; =20 @@ -130,16 +156,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - iowrite8(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); break; case 2: - iowrite8(1, priv->base + 11); + iowrite8(1, &priv->reg->acfg); break; case 4: - iowrite8(2, priv->base + 11); + iowrite8(2, &priv->reg->acfg); break; case 8: - iowrite8(3, priv->base + 11); + iowrite8(3, &priv->reg->acfg); break; default: return -EINVAL; @@ -153,7 +179,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; =20 priv->chan_out_states[chan->channel] =3D val; - iowrite16(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, &priv->reg->dac[chan->channel]); =20 return 0; } @@ -307,15 +333,15 @@ static int stx104_probe(struct device *dev, unsigned = int id) } =20 priv =3D iio_priv(indio_dev); - priv->base =3D devm_ioport_map(dev, base[id], STX104_EXTENT); - if (!priv->base) + priv->reg =3D devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->reg) return -ENOMEM; =20 indio_dev->info =3D &stx104_info; indio_dev->modes =3D INDIO_DIRECT_MODE; =20 /* determine if differential inputs */ - if (ioread8(priv->base + 8) & BIT(5)) { + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { indio_dev->num_channels =3D ARRAY_SIZE(stx104_channels_diff); indio_dev->channels =3D stx104_channels_diff; } else { @@ -326,14 +352,14 @@ static int stx104_probe(struct device *dev, unsigned = int id) indio_dev->name =3D dev_name(dev); =20 /* configure device for software trigger operation */ - iowrite8(0, priv->base + 9); + iowrite8(0, &priv->reg->acr); =20 /* initialize gain setting to x1 */ - iowrite8(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); =20 /* initialize DAC output to 0V */ - iowrite16(0, priv->base + 4); - iowrite16(0, priv->base + 6); + iowrite16(0, &priv->reg->dac[0]); + iowrite16(0, &priv->reg->dac[1]); =20 stx104gpio->chip.label =3D dev_name(dev); stx104gpio->chip.parent =3D dev; @@ -348,7 +374,7 @@ static int stx104_probe(struct device *dev, unsigned in= t id) stx104gpio->chip.get_multiple =3D stx104_gpio_get_multiple; stx104gpio->chip.set =3D stx104_gpio_set; stx104gpio->chip.set_multiple =3D stx104_gpio_set_multiple; - stx104gpio->base =3D priv->base + 3; + stx104gpio->base =3D &priv->reg->dio; stx104gpio->out_state =3D 0x0; =20 spin_lock_init(&stx104gpio->lock); --=20 2.36.1 From nobody Sun Apr 19 02:19:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5BB6CCA479 for ; Thu, 7 Jul 2022 22:30:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237060AbiGGWa2 (ORCPT ); Thu, 7 Jul 2022 18:30:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236968AbiGGWaX (ORCPT ); Thu, 7 Jul 2022 18:30:23 -0400 Received: from mail-qk1-x72d.google.com (mail-qk1-x72d.google.com [IPv6:2607:f8b0:4864:20::72d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E53E65D6C for ; Thu, 7 Jul 2022 15:30:22 -0700 (PDT) Received: by mail-qk1-x72d.google.com with SMTP id p17so2272788qkj.10 for ; Thu, 07 Jul 2022 15:30:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P0huPK9KiXPSzKRvofQEoWP6lAVCb1L8ZpIn1irvpaA=; b=cuxEEJ9uKCVcmMW3kl6SLihJr0SFCrAjwla+Uo7x/U6u4p2J4VifxF77scHlGYxtwe YX8xIFRq2GzFoBdqMlsQF7B+dziAliLavNwWDCwtTb6RzbH907henIcTA/PnmNBUx5y/ 1dJHPcHhiwhQAEsTi7kArqc+eSYEeuTxJp4Hr4SsDQDapNBIEX6jEH0xnEdtB1mkvIap b++lnisujfJnPTTlMTIZN/QMl/Zgx32wkaWLCGFTq8aRY66PQ9Pqd7HbX9JwzNXssU7j yNQS5ioDNo5UAZ+9yQl8ejQc/ON0rf8WZu97d9ZdEiueUQHr1k8Bk1JxWP7BeAjlo0ix MW3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P0huPK9KiXPSzKRvofQEoWP6lAVCb1L8ZpIn1irvpaA=; b=XRsu1u0lgfeSKHzObwOuEbywtxFsb+Gl4ZoyPsGgPmtDOQlgMHOZH5dF+fqr0mWdlK UVUvwbnBNmvDYRkH7snjgywoRElFQ9oRqM38kqNb3RbgHEWlRQpn0eLQ/bb0m8G+5Y6u AGF3sWFuUYx5z74OF34gNOrbFAP5g3NNfeX57MaLkPPy7lZfxr2E7Rr0qT3HtGA12KSv kytb6bAlqz7mdlshTJV6ZSL2YzR7f6k+Veb6IOmrGjJ3QVZoJZr0nwGEPHeT/aNdS+WG 999W2Cv5NaUczElSVx+V7rdfvlj1zv2pqeuoLEQXZ27gQIUc4p+znM+wXD3yQeXirfDq iQSw== X-Gm-Message-State: AJIora/DLJyOry1/ipq3/OY2A2k46qQ69IOpEUBX2ZK5kQV7J+FQ0MKI 45L19zGFbYCoFupNVHbFKqWZXw== X-Google-Smtp-Source: AGRyM1vFVx06LAXB2Ym9DnYEKLlpHi2LYmNjtiQMQgryzVtfSwj0E1SRl7ximirhjWgsXPF1NidtrA== X-Received: by 2002:a05:620a:2907:b0:6b1:17a5:a326 with SMTP id m7-20020a05620a290700b006b117a5a326mr180249qkp.373.1657233021636; Thu, 07 Jul 2022 15:30:21 -0700 (PDT) Received: from fedora.attlocal.net (69-109-179-158.lightspeed.dybhfl.sbcglobal.net. [69.109.179.158]) by smtp.gmail.com with ESMTPSA id e22-20020ac84b56000000b0031e9bd3586esm1527747qts.79.2022.07.07.15.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jul 2022 15:30:21 -0700 (PDT) From: William Breathitt Gray To: jic23@kernel.org Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, William Breathitt Gray Subject: [PATCH v2 2/2] iio: dac: cio-dac: Cleanup indexing for DAC writes Date: Thu, 7 Jul 2022 13:21:25 -0400 Message-Id: X-Mailer: git-send-email 2.36.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Simplify DAC write code by defining base member as u16 __iomem *; DAC registers are 16-bit so this allows us to index each DAC channel directly in a loop rather than calculating the offsets by multipling by 2 each time. Signed-off-by: William Breathitt Gray --- drivers/iio/dac/cio-dac.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iio/dac/cio-dac.c b/drivers/iio/dac/cio-dac.c index 8080984dcb03..791dd999cf29 100644 --- a/drivers/iio/dac/cio-dac.c +++ b/drivers/iio/dac/cio-dac.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 #define CIO_DAC_NUM_CHAN 16 =20 @@ -37,11 +38,11 @@ MODULE_PARM_DESC(base, "Measurement Computing CIO-DAC b= ase addresses"); /** * struct cio_dac_iio - IIO device private data structure * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @base: base memory address of the DAC device */ struct cio_dac_iio { int chan_out_states[CIO_DAC_NUM_CHAN]; - void __iomem *base; + u16 __iomem *base; }; =20 static int cio_dac_read_raw(struct iio_dev *indio_dev, @@ -61,7 +62,6 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { struct cio_dac_iio *const priv =3D iio_priv(indio_dev); - const unsigned int chan_addr_offset =3D 2 * chan->channel; =20 if (mask !=3D IIO_CHAN_INFO_RAW) return -EINVAL; @@ -71,7 +71,7 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, return -EINVAL; =20 priv->chan_out_states[chan->channel] =3D val; - iowrite16(val, priv->base + chan_addr_offset); + iowrite16(val, priv->base + chan->channel); =20 return 0; } @@ -117,7 +117,7 @@ static int cio_dac_probe(struct device *dev, unsigned i= nt id) indio_dev->name =3D dev_name(dev); =20 /* initialize DAC outputs to 0V */ - for (i =3D 0; i < 32; i +=3D 2) + for (i =3D 0; i < CIO_DAC_NUM_CHAN; i++) iowrite16(0, priv->base + i); =20 return devm_iio_device_register(dev, indio_dev); --=20 2.36.1