From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2468BC433FE for ; Wed, 11 May 2022 08:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243875AbiEKIcK (ORCPT ); Wed, 11 May 2022 04:32:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238144AbiEKIbm (ORCPT ); Wed, 11 May 2022 04:31:42 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 698203134D for ; Wed, 11 May 2022 01:31:31 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id 204so1380720pfx.3 for ; Wed, 11 May 2022 01:31:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=xQ+/39AkE91LiVQ4Kr8wAA4c9UriWAJqTaLbb/7ZPVs=; b=SfpCeNotyMV4WtU4qnoNenmfbtHMUNvrX4pnIiOvIGTqAQAaXZ/jGZzwDQBZ8ygJc2 TLnaW+J8N+713J2VFcZHm01b+3Up8pZC1pM0BTk4kO6gyONiOpX3Pkuau+2cZY9llWmj d0DdSlvrKLHfRH5NCzmwQQaEzTeVucMJSJ7gm4nmwJ7+dc3FlENOFcWkpnhYGibD9V/i FG0BsVfs7fKzU2MdbfHlc13e0MZOCKIayq82xy74sZCwBaOxH5Tlci+oX9ZzNsTjyYvI pr3Kuowifkn/6Yx6HumbY49exSgGILh/7/RAmVmIASfQeMMATBf7qsL0JD2wNxkrHUl7 t/uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=xQ+/39AkE91LiVQ4Kr8wAA4c9UriWAJqTaLbb/7ZPVs=; b=Zye3FOmG5S8D40aDwPG5gCsgHbyD6zccd21rgmwhiuLrXe58wpWoV/XO3eqGcR0gAA pk7+fqIlarfFQlqWRfWtGfBWjIZpzS+4AOEF/uanPOq+N7a3MFwbNPSqXjQuSp3TLHbe 3EHSO4+l91pnCw6jS28OQ312DECpj72VWD08QzhpUdbUWCDTirW+HdnpyCJ9vx6QOUAb DztsI7HJA0UKN1ebKxzb2SFvBlairHORySpMoWOk0rYVCNTZjiWYLJpSENxkKrDbCe/J g2mZi9a5CjwBfwLnSq+r8Q9r1xg7eCvvraALoseWWX7ldgL1G4aZ2WPunMbNPDHn2v7o heeA== X-Gm-Message-State: AOAM530xXD1mxb3QbIhciVpzKPqcCTrL0F2elUXOouXIsVzZWX9Wo/eO 5iLWeA+whAAsl/GzmzH2fnr8Jw== X-Google-Smtp-Source: ABdhPJx14OOqONpi9lA4QVGlDX8spXGW/IUI+yFob384ZCn8UeBWK1FuA2bgig7NAFiQb5KBMGjw3g== X-Received: by 2002:aa7:962e:0:b0:50d:5ed8:aa23 with SMTP id r14-20020aa7962e000000b0050d5ed8aa23mr24006586pfg.43.1652257890964; Wed, 11 May 2022 01:31:30 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:30 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 01/16] riscv: Rename __switch_to_aux -> fpu Date: Wed, 11 May 2022 08:31:11 +0000 Message-Id: <7bf1e003db9845e2a13eff15c33e3a490d34810a.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Guo Ren The name of __switch_to_aux is not clear and rename it with the determine function: __switch_to_fpu. Next we could add other regs' switch. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Signed-off-by: Greentime Hu Reviewed-by: Anup Patel Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/switch_to.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 0a3f4f95c555..ec83770b3d98 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -45,7 +45,7 @@ static inline void fstate_restore(struct task_struct *tas= k, } } =20 -static inline void __switch_to_aux(struct task_struct *prev, +static inline void __switch_to_fpu(struct task_struct *prev, struct task_struct *next) { struct pt_regs *regs; @@ -65,7 +65,7 @@ static __always_inline bool has_fpu(void) static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) #define fstate_restore(task, regs) do { } while (0) -#define __switch_to_aux(__prev, __next) do { } while (0) +#define __switch_to_fpu(__prev, __next) do { } while (0) #endif =20 extern struct task_struct *__switch_to(struct task_struct *, @@ -76,7 +76,7 @@ do { \ struct task_struct *__prev =3D (prev); \ struct task_struct *__next =3D (next); \ if (has_fpu()) \ - __switch_to_aux(__prev, __next); \ + __switch_to_fpu(__prev, __next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A83AC433EF for ; Wed, 11 May 2022 08:32:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243846AbiEKIcV (ORCPT ); Wed, 11 May 2022 04:32:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243725AbiEKIbq (ORCPT ); Wed, 11 May 2022 04:31:46 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2AA631509 for ; Wed, 11 May 2022 01:31:32 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d22so1183472plr.9 for ; Wed, 11 May 2022 01:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=JRX/iLnU0PEl4aE1jsRvHTuo999D/a+QvZpCGEgPlUA=; b=HAJWgvIRoqs0LfgalWP6ojZO1g0sEnjUIfCygsOcXzR06mAxirp7FsF1rIPz8xH0TJ 6QsOm/LPEddHAO1rPR6C1P0qVYnfEaOEq9u6XnbvJdfGD5ewDaY8kEgX1D3+A5pxOeUm InWSlP3RoygZr7h5hwVCVIiSevSmzaY9psUk9V+iuUhrhPZHWEsZXWEtDPb4R4jOk+yf 8sGmPstZ4OThvmH0GMvS0A9RIcU3oIU6fDlFPdvfOkw1gXc1q0Kol19+GikYAl1Ufzy4 TKI7aV/WyUFKaPykbHiXZeRjqn+Bwi0EdFA9/+5fsahSFUh1lwf3opCPCxV8ijiIU/Up NEAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=JRX/iLnU0PEl4aE1jsRvHTuo999D/a+QvZpCGEgPlUA=; b=X7cy5UUbBJEl+MT1SIxD/NJ4ixANboHscmJ+8jsKg8ad/BVwdmzoUB0QmYKhg7qWc3 RCEVrc0ZuPMEIFTZXdt5dguHBPKBXasxiuhACQKnk9pt5LGpnHFIiwVtMBHt7V/2f3OC 7QFwU/OmibGaYN6jQ63BUQBudgQkKOyFwVQUK1KFts12bpCD+c03ZLBYomRRJAVYYgo/ ZstvT+Gx4MwFTvXy2S4lsfkkDEozn7bSdcYbfI8JQFU8PGhfXQWJndz2ddyH+UBFsz5X lCT/sze2Cirfirom0LxAk6TdyU3g3SOfyMaKUJLYYaeYyUmuvlMKhVNTTBCbpewJr/Pv HtxA== X-Gm-Message-State: AOAM532z8JBs1dyXILjPlgtThAu/BRiK6GbjO084VJNTpr9oz3esZmED X376vc+DwOyecv4THibH8QBOCQ== X-Google-Smtp-Source: ABdhPJwsXQV+fb5RuleuyZPN6gdlX4DQrCU1gxu8pD+8g8dT4KUeC1ecnrXP925EDhqQm1GhsYAz1w== X-Received: by 2002:a17:90b:4f87:b0:1dd:100b:7342 with SMTP id qe7-20020a17090b4f8700b001dd100b7342mr4146651pjb.64.1652257892511; Wed, 11 May 2022 01:31:32 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:32 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 02/16] riscv: Extending cpufeature.c to detect V-extension Date: Wed, 11 May 2022 08:31:12 +0000 Message-Id: <7fcce42051191f2c90f536d0bdbc57da1ee1d9c2.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Guo Ren Current cpufeature.c doesn't support detecting V-extension, because "rv64" also contain a 'v' letter and we need to skip it. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Anup Patel Reviewed-by: Greentime Hu Signed-off-by: Greentime Hu Reviewed-by: Palmer Dabbelt --- arch/riscv/include/uapi/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/= asm/hwcap.h index 46dc3f5ee99f..c52bb7bbbabe 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -21,5 +21,6 @@ #define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) =20 #endif /* _UAPI_ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..92a8fd6bd3ed 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -76,6 +76,7 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f'] =3D isa2hwcap['F'] =3D COMPAT_HWCAP_ISA_F; isa2hwcap['d'] =3D isa2hwcap['D'] =3D COMPAT_HWCAP_ISA_D; isa2hwcap['c'] =3D isa2hwcap['C'] =3D COMPAT_HWCAP_ISA_C; + isa2hwcap['v'] =3D isa2hwcap['V'] =3D COMPAT_HWCAP_ISA_V; =20 elf_hwcap =3D 0; =20 --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A44DC433F5 for ; Wed, 11 May 2022 08:33:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242989AbiEKIdu (ORCPT ); Wed, 11 May 2022 04:33:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243726AbiEKIbq (ORCPT ); Wed, 11 May 2022 04:31:46 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC7A334653 for ; Wed, 11 May 2022 01:31:34 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id 7so1164388pga.12 for ; Wed, 11 May 2022 01:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=Enn39BPEC4WUCYgELDojANydnjOiUN1oJPfCEc+x7uM=; b=Gp1gHM2j10a2iPLDhakfJsNgJKi88y9NRLaUJBNlnW78v2BGEQ6XPJOGBfu8m0uRGL ibNSkQX5XwNmXbNfZ/MftsJHoyONfRJ4hQWYcLl30YYlJYJ+Xg7pEcTzQDyCeTdhUTHh DWq8wd8Ezo9GwqLFMGv0oTzGHGR98VaxEGfsgKtehrYnB9nk3Hg1QLDYQmB7C8nyDlUU 6XHZsSNESqI2r/wwwmz8exjfeW12g77zkQUDVncUsUKqXO2Jtg9tihNhKjZYCY9Dtqij 0/WesLi+oyRtzIZUrxVWn8YdkRHR/wbZwgGn1vGnUclXV7MdLcIijK0Qp6+gxp8U+pnM xenw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Enn39BPEC4WUCYgELDojANydnjOiUN1oJPfCEc+x7uM=; b=nk+ILKJmWh0WwoF2GDpW9r3cAE6g608k6UPkT/fouWOkidJWXuHNVj2kOvwziERw0F +BsssrJPvA8/3+eFcjPphhrMVNxMdLuiMnLnvYGtLiuNJukhO5slP9rPDhXbLe7zGPjN TimBQa/xWfxjFBB1D7PJBdbd54j30ET6UTQlE4bF8BoLZAojlJiI+xsOpzcpwQuX1mGN q8zVgMMen8bX/ktjTPkR4pqHtTApLzn6lmVAXgE7plLFrOGZ3B7DbXHWb6ie5EAtw4Zn rHNlJHtOsXqY8SfJoxwW1VFIWAxHmtK7oqAbNWlR/2/TfCJkUedpH2EeD/z/YnCkQVFR FkVw== X-Gm-Message-State: AOAM530R8467ARVBVmfNtlrm+5KB3JtuCggMJq7pRnl9Wy5bNTUOl/aU nqGXGuRIm4J3YSPkdlihfB22Xg== X-Google-Smtp-Source: ABdhPJzLN/nX3jESsXExXLfGAfX6dzBT5Ut7+OTmuducCoEMrkV+w/HchNMuYIp4KSucZL/AdZONwQ== X-Received: by 2002:a05:6a00:2484:b0:510:7f57:30b7 with SMTP id c4-20020a056a00248400b005107f5730b7mr23823891pfv.70.1652257894092; Wed, 11 May 2022 01:31:34 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:33 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 03/16] riscv: Add new csr defines related to vector extension Date: Wed, 11 May 2022 08:31:13 +0000 Message-Id: <5b13445101fcdef8706aaba6e5a480e31ae56e03.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Follow the riscv vector spec to add new csr numbers. [guoren@linux.alibaba.com: first porting for new vector related csr] Acked-by: Guo Ren Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index e935f27b10fd..ac95578a2908 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -24,6 +24,12 @@ #define SR_FS_CLEAN _AC(0x00004000, UL) #define SR_FS_DIRTY _AC(0x00006000, UL) =20 +#define SR_VS _AC(0x00000600, UL) /* Vector Status */ +#define SR_VS_OFF _AC(0x00000000, UL) +#define SR_VS_INITIAL _AC(0x00000200, UL) +#define SR_VS_CLEAN _AC(0x00000400, UL) +#define SR_VS_DIRTY _AC(0x00000600, UL) + #define SR_XS _AC(0x00018000, UL) /* Extension Status */ #define SR_XS_OFF _AC(0x00000000, UL) #define SR_XS_INITIAL _AC(0x00008000, UL) @@ -31,9 +37,9 @@ #define SR_XS_DIRTY _AC(0x00018000, UL) =20 #ifndef CONFIG_64BIT -#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */ #else -#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */ #endif =20 /* SATP flags */ @@ -268,6 +274,12 @@ #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 =20 +#define CSR_VSTART 0x8 +#define CSR_VCSR 0xf +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 +#define CSR_VLENB 0xc22 + #ifdef CONFIG_RISCV_M_MODE # define CSR_STATUS CSR_MSTATUS # define CSR_IE CSR_MIE --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79550C433FE for ; Wed, 11 May 2022 08:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243935AbiEKIca (ORCPT ); Wed, 11 May 2022 04:32:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243815AbiEKIbq (ORCPT ); Wed, 11 May 2022 04:31:46 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 597A13525C for ; Wed, 11 May 2022 01:31:36 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d22so1183588plr.9 for ; Wed, 11 May 2022 01:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=vOP9ZS/vxkzOlI/l+cYdq2hR42ZqOFcbpjPtOsjjFaA=; b=f/GBF7F+MFK3EAYxoYQRrccahir05NtthLiHYzXGNTNWj3phkyDZ2fKkhIvoEhMKex GFha3bwBcWHrhhkSK7v/OBVw7NoZItkcqrRCD7K8PUQDf897gbKw8a7aaNpYm/HzIUt5 ug3QcVV4xJ7gZw71SUTKUsLxKtD0rHn9SG7HJxEEtqm2ZpVQLdsDqma4TVsMEiIVrEo8 E19T2gxzZrFQcfhx+qYSHH4PgZ8VhbFqiISaXwOJe2jUnp+qcTS+zwMcOjFMYGOPEU11 mQEaVkOo5xqgqVDA9l5sPh1NpI7Cwv84vnYKUr0jICaWf9sQ3/Jj2f6ToVVjM7cwMKmH pIWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=vOP9ZS/vxkzOlI/l+cYdq2hR42ZqOFcbpjPtOsjjFaA=; b=QvWtBG5bJ5/+0yz2pLx2qBZeskBzzl3mDv5droLCzW47NeHhi4bj+APgjIB+NSScPF O2KsU+iMKwmez6/W1Pa4UZ7bViJ9iaWa6EtvyQWaz7tLSS2rfg+dqZ1SwbFnBp1+gVVB V1V17zCCh4fNZEfQa4hHL8gnYF4W3nRvOOuEasSTgFb4FPEQymYFxYtowKvBvYH6vlvg +moOWHa8LiRSPBzzV3KUNelRbFRTc0sJ+OiakNqDvMyUW3eZNRd8mSbgjMevZsigPTm4 393TiEmXXfNG2ljEVG99Kc7qLs/LcLhz29FnrDU4OJJxc27oFmp7OeUNqglRePr3M53U YYsA== X-Gm-Message-State: AOAM532ccUhacpJIjeTi0AI3CTH/FWa9X8BE4WnwcXVxg0g8xJ84XCpp 5mxY97d86xOi6jt6rFnZOw7+TQ== X-Google-Smtp-Source: ABdhPJzd9MohPSdgpI7PT06NrpVeiGGVvF1d4vkuVIARh6Sr2k+nuPxNbBaG8oTBR6ik6brdH9/xHw== X-Received: by 2002:a17:902:b48f:b0:15e:da68:8f12 with SMTP id y15-20020a170902b48f00b0015eda688f12mr24076205plr.27.1652257895794; Wed, 11 May 2022 01:31:35 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:35 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 04/16] riscv: Add vector feature to compile Date: Wed, 11 May 2022 08:31:14 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Guo Ren This patch adds a new config option which could enable assembler's vector feature. Signed-off-by: Guo Ren Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu --- arch/riscv/Kconfig | 10 ++++++++++ arch/riscv/Makefile | 1 + 2 files changed, 11 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 00fd9c548f26..f54f37cc746b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -343,6 +343,16 @@ config FPU =20 If you don't know what to do here, say Y. =20 +config VECTOR + bool "VECTOR support" + depends on GCC_VERSION >=3D 120000 || CLANG_VERSION >=3D 130000 + default n + help + Say N here if you want to disable all vector related procedure + in the kernel. + + If you don't know what to do here, say Y. + endmenu =20 menu "Kernel features" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 7d81102cffd4..1f19bdac6767 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -50,6 +50,7 @@ riscv-march-$(CONFIG_ARCH_RV32I) :=3D rv32ima riscv-march-$(CONFIG_ARCH_RV64I) :=3D rv64ima riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c +riscv-march-$(CONFIG_VECTOR) :=3D $(riscv-march-y)v =20 # Newer binutils versions default to ISA spec version 20191213 which moves= some # instructions from the I extension to the Zicsr and Zifencei extensions. --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B8F1C433EF for ; Wed, 11 May 2022 08:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243893AbiEKIcZ (ORCPT ); Wed, 11 May 2022 04:32:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243805AbiEKIbq (ORCPT ); Wed, 11 May 2022 04:31:46 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E024C2FE52 for ; Wed, 11 May 2022 01:31:37 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id x52so1346577pfu.11 for ; Wed, 11 May 2022 01:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=CNcmhvwD3MIc3ZF4wDh+JNST4g3yed3GkIbTz0xMpAM=; b=UmNqaGT3mFMRhnwCYlyTXysoWEtZ9BqkFF/06pf0pJGYPLbs8ck752Y3MC1HwFrn0H ik2ZHFXfIEK1XPvZXcKTV3JeOo+TNE3AsgA8C4ugJqTJNFmaK4T5yCjln+9bx1gEF5fv lbZPJ8C60NC4Mo2RsBLwixQ0G9eQLm+HYgflqYCZxdwBeLaXxdO4PUXqH5jXKMXwjaWC UOD4V/5fd+LfazcG6uuCI67YVCbiGLzhRHvkwPAhXbBKdKonvGQqaWe2O2iyLbr7bMjE p+hlZSkiCQwrGIisKemcEaQpLsHBrKafUAncEzv9O8vWnhF77PE4QwKR1TwAZESCPAMD NTmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=CNcmhvwD3MIc3ZF4wDh+JNST4g3yed3GkIbTz0xMpAM=; b=Vk2RsapN/WVSj8pxne2RhgTRXyxxaT6F/1grr+aeQN0q7dJjXIoUEEaV1nZhlIwrCK BfuDO1gyWWXbChCZQi6WMDMGd1rgiLzmwtbdXgOdR1cxHlkxS0joAlQlafKDQb4+IwQk AT3NqQjTzIdU2DIfSNDfFJWz6DWbxyunUr1uZVB7QeZdHiRDeVqCh7fV8/iIQCVMtkWm 808DCHuszjIaghYEU5y+tpXyRHoiBKukQMGbY8B4CbMrsLAJIYjtJswB9TSbXE7ov1vN mqLxpp32fNW6uiyq7akV4W4QBoXiP5bpyXIxUjB/fP+A8FGy/WQi+QsMocmk3dLVwhx/ Gj0w== X-Gm-Message-State: AOAM530t60+PuDqg05GuOhMxTW1KC+Fd8IVPIRAa09mCAU85rL8o4h4b fKpuPfYLcnsLlO9/I9RGbsNicQ== X-Google-Smtp-Source: ABdhPJx0UeFG4yjq9tUcou7zoqQkI5qhd4fok9z2NTAu6A0LqYB7M0mYqan+bac+lsNQPdt+0XUneQ== X-Received: by 2002:a05:6a00:13aa:b0:50e:f00:9e1d with SMTP id t42-20020a056a0013aa00b0050e0f009e1dmr24311637pfg.38.1652257897380; Wed, 11 May 2022 01:31:37 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:37 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 05/16] riscv: Add has_vector/riscv_vsize to save vector features. Date: Wed, 11 May 2022 08:31:15 +0000 Message-Id: <221f72a2ee62cd5350edb5d6a7e8ebb17a7bc321.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@linux.alibaba.com: add has_vector checking] Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h | 14 +++++ arch/riscv/kernel/cpufeature.c | 17 ++++++ arch/riscv/kernel/riscv_ksyms.c | 6 +++ arch/riscv/kernel/vector.S | 93 +++++++++++++++++++++++++++++++++ 4 files changed, 130 insertions(+) create mode 100644 arch/riscv/include/asm/vector.h create mode 100644 arch/riscv/kernel/vector.S diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h new file mode 100644 index 000000000000..16304b0c6a6f --- /dev/null +++ b/arch/riscv/include/asm/vector.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2020 SiFive + */ + +#ifndef __ASM_RISCV_VECTOR_H +#define __ASM_RISCV_VECTOR_H + +#include + +void rvv_enable(void); +void rvv_disable(void); + +#endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 92a8fd6bd3ed..f2dec6cb60ed 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -24,6 +24,11 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __re= ad_mostly; #ifdef CONFIG_FPU __ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_fpu); #endif +#ifdef CONFIG_VECTOR +#include +__ro_after_init DEFINE_STATIC_KEY_FALSE(cpu_hwcap_vector); +unsigned long riscv_vsize __read_mostly; +#endif =20 /** * riscv_isa_extension_base() - Get base extension word @@ -76,7 +81,9 @@ void __init riscv_fill_hwcap(void) isa2hwcap['f'] =3D isa2hwcap['F'] =3D COMPAT_HWCAP_ISA_F; isa2hwcap['d'] =3D isa2hwcap['D'] =3D COMPAT_HWCAP_ISA_D; isa2hwcap['c'] =3D isa2hwcap['C'] =3D COMPAT_HWCAP_ISA_C; +#ifdef CONFIG_VECTOR isa2hwcap['v'] =3D isa2hwcap['V'] =3D COMPAT_HWCAP_ISA_V; +#endif =20 elf_hwcap =3D 0; =20 @@ -237,4 +244,14 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) static_branch_enable(&cpu_hwcap_fpu); #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + static_branch_enable(&cpu_hwcap_vector); + /* There are 32 vector registers with vlenb length. */ + rvv_enable(); + riscv_vsize =3D csr_read(CSR_VLENB) * 32; + rvv_disable(); + } +#endif } diff --git a/arch/riscv/kernel/riscv_ksyms.c b/arch/riscv/kernel/riscv_ksym= s.c index 5ab1c7e1a6ed..3489d2a20ca3 100644 --- a/arch/riscv/kernel/riscv_ksyms.c +++ b/arch/riscv/kernel/riscv_ksyms.c @@ -15,3 +15,9 @@ EXPORT_SYMBOL(memmove); EXPORT_SYMBOL(__memset); EXPORT_SYMBOL(__memcpy); EXPORT_SYMBOL(__memmove); + +#ifdef CONFIG_VECTOR +#include +EXPORT_SYMBOL(rvv_enable); +EXPORT_SYMBOL(rvv_disable); +#endif diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S new file mode 100644 index 000000000000..9f7dc70c4443 --- /dev/null +++ b/arch/riscv/kernel/vector.S @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2019 Alibaba Group Holding Limited + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +#include +#include +#include + +#define vstatep a0 +#define datap a1 +#define x_vstart t0 +#define x_vtype t1 +#define x_vl t2 +#define x_vcsr t3 +#define incr t4 +#define status t5 + +ENTRY(__vstate_save) + li status, SR_VS + csrs CSR_STATUS, status + + csrr x_vstart, CSR_VSTART + csrr x_vtype, CSR_VTYPE + csrr x_vl, CSR_VL + csrr x_vcsr, CSR_VCSR + vsetvli incr, x0, e8, m8, ta, ma + vse8.v v0, (datap) + add datap, datap, incr + vse8.v v8, (datap) + add datap, datap, incr + vse8.v v16, (datap) + add datap, datap, incr + vse8.v v24, (datap) + + REG_S x_vstart, RISCV_V_STATE_VSTART(vstatep) + REG_S x_vtype, RISCV_V_STATE_VTYPE(vstatep) + REG_S x_vl, RISCV_V_STATE_VL(vstatep) + REG_S x_vcsr, RISCV_V_STATE_VCSR(vstatep) + + csrc CSR_STATUS, status + ret +ENDPROC(__vstate_save) + +ENTRY(__vstate_restore) + li status, SR_VS + csrs CSR_STATUS, status + + vsetvli incr, x0, e8, m8, ta, ma + vle8.v v0, (datap) + add datap, datap, incr + vle8.v v8, (datap) + add datap, datap, incr + vle8.v v16, (datap) + add datap, datap, incr + vle8.v v24, (datap) + + REG_L x_vstart, RISCV_V_STATE_VSTART(vstatep) + REG_L x_vtype, RISCV_V_STATE_VTYPE(vstatep) + REG_L x_vl, RISCV_V_STATE_VL(vstatep) + REG_L x_vcsr, RISCV_V_STATE_VCSR(vstatep) + vsetvl x0, x_vl, x_vtype + csrw CSR_VSTART, x_vstart + csrw CSR_VCSR, x_vcsr + + csrc CSR_STATUS, status + ret +ENDPROC(__vstate_restore) + +ENTRY(rvv_enable) + li status, SR_VS + csrs CSR_STATUS, status + ret +ENDPROC(rvv_enable) + +ENTRY(rvv_disable) + li status, SR_VS + csrc CSR_STATUS, status + ret +ENDPROC(rvv_disable) --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ABE0C433F5 for ; Wed, 11 May 2022 08:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233119AbiEKIdk (ORCPT ); Wed, 11 May 2022 04:33:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243810AbiEKIbq (ORCPT ); Wed, 11 May 2022 04:31:46 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 964513916D for ; Wed, 11 May 2022 01:31:39 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id x23so1356073pff.9 for ; Wed, 11 May 2022 01:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=9DDx0IFq0rFZB0Z2ZzpiVoBVEGPTvAItk8MwFiFZRtc=; b=YpPl60Nhwk/OdiyJpYlA8Ekm9d8dlN/g8aKTGRzi0aZV1mrWvjSDLrHaHAGKTSQATO ypdpf4/+azIERpDxCu3B3iePwgaZakOuCOmYsn5lzEVtNGup2fLSjyFdiJzZ+X/VS7mD EszWsPHKq8OYHgl3nhr3KcWsRDJ5xis7H/6viosa0QuMQrnmyht6rFxY7H7gRbrQ8GoE Qg/F3iZCG1yc/vyWCTgRMm1ssexS09M7Zyn2598mD1fxhkH+EFpA8mOTJv9YYlBu8PVl 1OuHZrAfVE3zHuNhqelPjdxBuEn/5LGrkSIaJqvoidRRK3rPsnKlnryskXBwi11miqzd w9qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=9DDx0IFq0rFZB0Z2ZzpiVoBVEGPTvAItk8MwFiFZRtc=; b=MQCbhb2Pnm9iWd4/NHgoIJK72wWcjgfMwQaGqrCd62tMdp2Nsxo+nZIJ+rRFRCYBsh bFDZbPI2zuh0eah1h8rRe1qKk2k6r0QYpiiTIEJHGNu38xajigMPTmRGodj+8rqhaNtV nyc/QtQRdiZFeshovx/Bb6UGArBjvmXv6M2w0YJWlwPDV9j2c7+UWZE6QOd/8BebBzZL wDCISFybEvWpngBKV5mkktLTP1aLZ7AYxL16pF1ungaUkOPqnG4QLUeRxIS8awV233wi kHhY3AuhkjT0uG3K/eawUp40eEvnjbJfeozLKinJSJikFoFqOoghRkLb1djBo+C8QU5w U/zg== X-Gm-Message-State: AOAM533z9XTDoswsJ7BnmEgyq2ics9THWOUTpm/I3EbjMa3D/WtSem5A sd51jL0Hg9Mjyen5NFmkn5JFYA== X-Google-Smtp-Source: ABdhPJxk2oyoniPig7GOpPAx4ynn5C0XjJmrO3QMW/2MjdeED1m2F1kmN59hoKaQCiyREsETUSB+3A== X-Received: by 2002:a63:5cb:0:b0:3da:fe5d:4448 with SMTP id 194-20020a6305cb000000b003dafe5d4448mr4670383pgf.583.1652257899093; Wed, 11 May 2022 01:31:39 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:38 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 06/16] riscv: Reset vector register Date: Wed, 11 May 2022 08:31:16 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Guo Ren Reset vector registers at boot-time and disable vector instructions execution for kernel mode. Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Han-Kuan Chen Signed-off-by: Han-Kuan Chen Co-developed-by: Greentime Hu Signed-off-by: Greentime Hu Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/entry.S | 6 +++--- arch/riscv/kernel/head.S | 35 +++++++++++++++++++++++++++++------ 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index c8b9ce274b9a..559f1418e980 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -77,10 +77,10 @@ _save_context: * Disable user-mode memory access as it should only be set in the * actual user copy routines. * - * Disable the FPU to detect illegal usage of floating point in kernel - * space. + * Disable the FPU/Vector to detect illegal usage of floating point + * or vector in kernel space. */ - li t0, SR_SUM | SR_FS + li t0, SR_SUM | SR_FS | SR_VS =20 REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 893b8bb69391..2877af90b025 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -139,10 +139,10 @@ secondary_start_sbi: .option pop =20 /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS | SR_VS csrc CSR_STATUS, t0 =20 /* Set trap vector to spin forever to help debug */ @@ -233,10 +233,10 @@ pmp_done: .option pop =20 /* - * Disable FPU to detect illegal usage of - * floating point in kernel space + * Disable FPU & VECTOR to detect illegal usage of + * floating point or vector in kernel space */ - li t0, SR_FS + li t0, SR_FS | SR_VS csrc CSR_STATUS, t0 =20 #ifdef CONFIG_RISCV_BOOT_SPINWAIT @@ -429,6 +429,29 @@ ENTRY(reset_regs) csrw fcsr, 0 /* note that the caller must clear SR_FS */ #endif /* CONFIG_FPU */ + +#ifdef CONFIG_VECTOR + csrr t0, CSR_MISA + li t1, COMPAT_HWCAP_ISA_V + and t0, t0, t1 + beqz t0, .Lreset_regs_done + + /* + * Clear vector registers and reset vcsr + * VLMAX has a defined value, VLEN is a constant, + * and this form of vsetvli is defined to set vl to VLMAX. + */ + li t1, SR_VS + csrs CSR_STATUS, t1 + csrs CSR_VCSR, x0 + vsetvli t1, x0, e8, m8, ta, ma + vmv.v.i v0, 0 + vmv.v.i v8, 0 + vmv.v.i v16, 0 + vmv.v.i v24, 0 + /* note that the caller must clear SR_VS */ +#endif /* CONFIG_VECTOR */ + .Lreset_regs_done: ret END(reset_regs) --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F68CC4332F for ; Wed, 11 May 2022 08:34:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243964AbiEKIch (ORCPT ); Wed, 11 May 2022 04:32:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243731AbiEKIbq (ORCPT ); Wed, 11 May 2022 04:31:46 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BEEC3B3C2 for ; Wed, 11 May 2022 01:31:41 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id gj17-20020a17090b109100b001d8b390f77bso4278931pjb.1 for ; Wed, 11 May 2022 01:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=/ojtaq0pVTISiVB+t5H7Gtqn9qT+yiZRc8EYMYytpr0=; b=D1p70MhwIuPllZCRHztQBSDqpmMGP0lmYpciM3ZdGEM0H1RHycrby4c4kHVhvjsScp 1pJu9uzHt+ntZZ48Tm2pMH+pl9nSJnNIrjC+ItTs+LCxOIPu67a1PmsiqShdXZOXbN8g 2k9IFwmsVcRFPyrMP+n6R4fpoDl3EHpGz+RUlTzgA1/FX+7EHILH9y/uyJ0mUzVw9QD6 aIa0CqGiGgaL1P08hjhMI8dJJCbBj3TlSAYAX8Wr//UToiMDl6aACJ4pEhsMGtsJ1HJI gh0kfq5WriFOuyj2z/MOOAKzgWbF1AFF/mYR/GvcQAW5CWbxygEtEyO3EVPgviT/uI4J pdCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=/ojtaq0pVTISiVB+t5H7Gtqn9qT+yiZRc8EYMYytpr0=; b=t3lO9nDN3Ys0GJL6QFwwTImJZAY55N0MDKeVe5U61NhQDRWQO0wbbNWjJiYhYC9GHA MZ0/DBDz1qO4Ao3/ARe/XFcpkZBC7zhiweDZqF78xwEweNdr8FrrAkTCPKjRcDVEW0+J JveiF8fBwCtpEbINjWKQ/MTqMvOY1QnGCARXl+xVmFJaeJ1XBZ/CH77f6C1nudAwyClG EwW8LwSf/j1HfVeEW44sc+AulsuWEc9NICO5kG4uehQgKZDmFhuKXoPTtvXX03d7mjuZ 53FgUQKv1IzBmNsEJOKGsNxM4yf1zFWce8kif96ihOvSvKET42lCWKLbUXdRNghrWp7W w5zQ== X-Gm-Message-State: AOAM53156YJs+Mn1nEkBSPAjlePG1R3XwBzVQUaw53BCYYKvi2rJqR/O 0ydCrWkez2FrjcDbTrRJbU1+/g== X-Google-Smtp-Source: ABdhPJyBwuSNtM5/ptBpzBtWQ0GULx0806sbKBjU++Ipvid80IN1LkB54oBCdLtT6xip2SfKgAaWuQ== X-Received: by 2002:a17:902:da8b:b0:15e:aba7:43fe with SMTP id j11-20020a170902da8b00b0015eaba743femr24282811plx.9.1652257900729; Wed, 11 May 2022 01:31:40 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:40 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 07/16] riscv: Add vector struct and assembler definitions Date: Wed, 11 May 2022 08:31:17 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add vector state context struct in struct thread and asm-offsets.c definitions. The vector registers will be saved in datap pointer of __riscv_v_state. It will be dynamically allocated in kernel space. It will be put right after the __riscv_v_state data structure in user space. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/uapi/asm/ptrace.h | 17 +++++++++++++++++ arch/riscv/kernel/asm-offsets.c | 6 ++++++ 3 files changed, 24 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 0749924d9e55..91f1c318328e 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -35,6 +35,7 @@ struct thread_struct { unsigned long s[12]; /* s[0]: frame pointer */ struct __riscv_d_ext_state fstate; unsigned long bad_cause; + struct __riscv_v_state vstate; }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi= /asm/ptrace.h index 882547f6bd5c..6ee1ca2edfa7 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -77,6 +77,23 @@ union __riscv_fp_state { struct __riscv_q_ext_state q; }; =20 +struct __riscv_v_state { + unsigned long vstart; + unsigned long vl; + unsigned long vtype; + unsigned long vcsr; + void *datap; + /* + * In signal handler, datap will be set a correct user stack offset + * and vector registers will be copied to the address of datap + * pointer. + * + * In ptrace syscall, datap will be set to zero and the vector + * registers will be copied to the address right after this + * structure. + */ +}; + #endif /* __ASSEMBLY__ */ =20 #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index df9444397908..37e3e6a8d877 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -75,6 +75,12 @@ void asm_offsets(void) OFFSET(TSK_STACK_CANARY, task_struct, stack_canary); #endif =20 + OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart); + OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl); + OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype); + OFFSET(RISCV_V_STATE_VCSR, __riscv_v_state, vcsr); + OFFSET(RISCV_V_STATE_DATAP, __riscv_v_state, datap); + DEFINE(PT_SIZE, sizeof(struct pt_regs)); OFFSET(PT_EPC, pt_regs, epc); OFFSET(PT_RA, pt_regs, ra); --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DDBCC433F5 for ; Wed, 11 May 2022 08:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243691AbiEKIcq (ORCPT ); Wed, 11 May 2022 04:32:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243738AbiEKIbr (ORCPT ); Wed, 11 May 2022 04:31:47 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8878B853 for ; Wed, 11 May 2022 01:31:42 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id c1-20020a17090a558100b001dca2694f23so1430230pji.3 for ; Wed, 11 May 2022 01:31:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=lIPaVi/iw25tEhFvwxekxmoPFpktE2S3CDH6g+AQZN8=; b=gnEVGhBZjcBviXMolR/BZI6SoUJ16vvpJefyHkk8X+xTDu2A7c4prdPtGwDQDyEEjC /6I3ZM2hJXlRWfEy4vcXooF97elXNWlcR3ydaLHRc6QZp5McK/fzEp8QAcJtbtlFTfiF pYQRK/rGhcXGKnmDVHaqcsuhdTWMd7+9pJWIqO4fZmmrUbJBVKEJCHDLprc7eXbwJk5y wKBnf/4x6xeNqQDQ3ewDs2ZAg81eQimmoawgMML1QdluTOE5nNVefaQSZyJ40qZiACzk 3s/M4MqftlnmkBTYRa9dtVsGmr/HFogGJgmXoE50BI9XDjDPVZYpZ5/iJKTqs4FAV90A 6Tzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=lIPaVi/iw25tEhFvwxekxmoPFpktE2S3CDH6g+AQZN8=; b=yIc6SOB2R6n/9yXPjgwJ5bKQ3ym36tZX4A31ETy+o37Dc2Dl0quCGurXlL/3xdbsWU M+BaTOeLXdGlZWnO3KshdLw4vVpj/1Oa3T4nzzvWy/ByCKAWWuFrJM82XLb/GL0MowNd rjSmrKtqb1e8aZWUR2QWPanIsHyj0AwOyXMIdF6ikTgv6vjWvl4JdnyKJkktXCtpoo48 HdyvFj46CyrEZls1VrCv7xpHGz/a0Prfbympayhk6JVyE+jIGuQCdk2IdVuqbMl251xS 51Rb4SFJPDcN8Ah0kMZQr2It5sEuQVH9zM0v2d7G2n3ytnIjMZXCLKtu1ZUU4dyOJMLw zguQ== X-Gm-Message-State: AOAM532gaqkwRJK+B7Dt36kOzsvGVw7KJye1JbB1wD+S2G0FMHeWigBk PIYczq7ju9LZ6O9oXhv6w3wgDg== X-Google-Smtp-Source: ABdhPJysgdpEVFclbE6bwwFMoHRNXpqhpUG5+igm4bsD4AFK7iqJyo7JpNOED7VBkorad+uhynRZcw== X-Received: by 2002:a17:903:2091:b0:15c:b49b:664d with SMTP id d17-20020a170903209100b0015cb49b664dmr24482576plc.151.1652257902351; Wed, 11 May 2022 01:31:42 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:42 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 08/16] riscv: Add task switch support for vector Date: Wed, 11 May 2022 08:31:18 +0000 Message-Id: <3f544b952369e55f72a8771d0bec387c2ff49ae0.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds task switch support for vector. It supports partial lazy save and restore mechanism. It also supports all lengths of vlen. [guoren@linux.alibaba.com: First available porting to support vector context switching] [nick.knight@sifive.com: Rewrite vector.S to support dynamic vlen, xlen and code refine] [vincent.chen@sifive.com: Fix the might_sleep issue in vstate_save, vstate_restore] [andrew@sifive.com: Optimize task switch codes of vector] [ruinland.tsai@sifive.com: Fix the arch_release_task_struct free wrong datap issue] Suggested-by: Andrew Waterman Co-developed-by: Nick Knight Signed-off-by: Nick Knight Co-developed-by: Guo Ren Signed-off-by: Guo Ren Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Co-developed-by: Ruinland Tsai Signed-off-by: Ruinland Tsai Signed-off-by: Greentime Hu Reported-by: kernel test robot --- arch/riscv/include/asm/switch_to.h | 66 ++++++++++++++++++++++++++++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/process.c | 43 +++++++++++++++++++ 3 files changed, 110 insertions(+) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index ec83770b3d98..6836c51885ce 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -7,10 +7,12 @@ #define _ASM_RISCV_SWITCH_TO_H =20 #include +#include #include #include #include #include +#include =20 #ifdef CONFIG_FPU extern void __fstate_save(struct task_struct *save_to); @@ -68,6 +70,68 @@ static __always_inline bool has_fpu(void) { return false= ; } #define __switch_to_fpu(__prev, __next) do { } while (0) #endif =20 +#ifdef CONFIG_VECTOR +extern struct static_key_false cpu_hwcap_vector; +static __always_inline bool has_vector(void) +{ + return static_branch_likely(&cpu_hwcap_vector); +} +extern unsigned long riscv_vsize; +extern void __vstate_save(struct __riscv_v_state *save_to, void *datap); +extern void __vstate_restore(struct __riscv_v_state *restore_from, void *d= atap); + +static inline void __vstate_clean(struct pt_regs *regs) +{ + regs->status =3D (regs->status & ~(SR_VS)) | SR_VS_CLEAN; +} + +static inline void vstate_off(struct task_struct *task, + struct pt_regs *regs) +{ + regs->status =3D (regs->status & ~SR_VS) | SR_VS_OFF; +} + +static inline void vstate_save(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) =3D=3D SR_VS_DIRTY) { + struct __riscv_v_state *vstate =3D &(task->thread.vstate); + + __vstate_save(vstate, vstate->datap); + __vstate_clean(regs); + } +} + +static inline void vstate_restore(struct task_struct *task, + struct pt_regs *regs) +{ + if ((regs->status & SR_VS) !=3D SR_VS_OFF) { + struct __riscv_v_state *vstate =3D &(task->thread.vstate); + + __vstate_restore(vstate, vstate->datap); + __vstate_clean(regs); + } +} + +static inline void __switch_to_vector(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs =3D task_pt_regs(prev); + if (unlikely(regs->status & SR_SD)) + vstate_save(prev, regs); + vstate_restore(next, task_pt_regs(next)); +} + +#else +static __always_inline bool has_vector(void) { return false; } +#define riscv_vsize (0) +#define vstate_save(task, regs) do { } while (0) +#define vstate_restore(task, regs) do { } while (0) +#define __switch_to_vector(__prev, __next) do { } while (0) +#endif + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); =20 @@ -77,6 +141,8 @@ do { \ struct task_struct *__next =3D (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ + if (has_vector()) \ + __switch_to_vector(__prev, __next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 87adbe47bc15..5dc550a9fb45 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ =20 obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o +obj-$(CONFIG_VECTOR) +=3D vector.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D cpu_ops.o diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 504b496787aa..64568a465c6e 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -96,6 +96,25 @@ void start_thread(struct pt_regs *regs, unsigned long pc, */ fstate_restore(current, regs); } + + if (has_vector()) { + struct __riscv_v_state *vstate =3D &(current->thread.vstate); + + /* Enable vector and allocate memory for vector registers. */ + if (!vstate->datap) { + vstate->datap =3D kzalloc(riscv_vsize, GFP_KERNEL); + if (WARN_ON(!vstate->datap)) + return; + } + regs->status |=3D SR_VS_INITIAL; + + /* + * Restore the initial value to the vector register + * before starting the user program. + */ + vstate_restore(current, regs); + } + regs->epc =3D pc; regs->sp =3D sp; } @@ -111,15 +130,29 @@ void flush_thread(void) fstate_off(current, task_pt_regs(current)); memset(¤t->thread.fstate, 0, sizeof(current->thread.fstate)); #endif +#ifdef CONFIG_VECTOR + /* Reset vector state */ + vstate_off(current, task_pt_regs(current)); + memset(¤t->thread.vstate, 0, RISCV_V_STATE_DATAP); +#endif } =20 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src) { fstate_save(src, task_pt_regs(src)); *dst =3D *src; + dst->thread.vstate.datap =3D NULL; + return 0; } =20 +void arch_release_task_struct(struct task_struct *tsk) +{ + /* Free the vector context of datap. */ + if (has_vector() && tsk->thread.vstate.datap) + kfree(tsk->thread.vstate.datap); +} + int copy_thread(unsigned long clone_flags, unsigned long usp, unsigned lon= g arg, struct task_struct *p, unsigned long tls) { @@ -136,7 +169,17 @@ int copy_thread(unsigned long clone_flags, unsigned lo= ng usp, unsigned long arg, p->thread.ra =3D (unsigned long)ret_from_kernel_thread; p->thread.s[0] =3D usp; /* fn */ p->thread.s[1] =3D arg; + p->thread.vstate.datap =3D NULL; } else { + /* Allocate the datap for the user process if datap is NULL */ + if (has_vector() && !p->thread.vstate.datap) { + void *datap =3D kzalloc(riscv_vsize, GFP_KERNEL); + /* Failed to allocate memory. */ + if (!datap) + return -ENOMEM; + p->thread.vstate.datap =3D datap; + memset(&p->thread.vstate, 0, RISCV_V_STATE_DATAP); + } *childregs =3D *(current_pt_regs()); if (usp) /* User fork */ childregs->sp =3D usp; --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 494AFC433F5 for ; Wed, 11 May 2022 08:33:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243995AbiEKIdA (ORCPT ); Wed, 11 May 2022 04:33:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243758AbiEKIbt (ORCPT ); Wed, 11 May 2022 04:31:49 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 791AF2AC7F for ; Wed, 11 May 2022 01:31:44 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id a191so1195818pge.2 for ; Wed, 11 May 2022 01:31:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=hn9a0/YIZzR3pf/XVlEiVrwG/Xe5Ymt+E9Xn6o6kKJM=; b=KIPMNaSvgyCbpsbGTq8d2mWXUto29HB+ZCEjfgcJ5KcgD2LiZxHLHCkSel9nGFEsyx eZ2jkyCn/Z2XTf1Y8TxPRhlAZvyxtpLW//MXf4FtyuinEWaVckfOp08GzRcMRdGYt8O0 ZXzDROyJEnE4pBy3QQdrCkCF6mWdVNNah9ICken2EGT5rGV0B7Nn1v1ZMx2TapOq7hCK kUBeCKzLSC2VI5s/s6WIsPX0rlbeJIwyjiCjJjI+Ia8mFDpjZ0Cd2H+FaluqLmVdfzjE F84cvF3uM7gN9/pEWvggRVqkXuGPt6chyKZ7YngU3hlSFmG9ch35Q0aRloeECr+Zlz1d W9ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=hn9a0/YIZzR3pf/XVlEiVrwG/Xe5Ymt+E9Xn6o6kKJM=; b=mE/pHVI7OFdg2e2XHHLBI565q1GRu2sNn+kx12JIsUqURslnsnKeUJAyCLEGqto9uH q8+45mYFJcDbBttPDlN0NeUzslEx387aPgPWwiDydQUIlJkVpdfDcWpUW13ZfMCC71bT I9frSHAlY0FBeKPW5sklJ0sFN7Lew818ALc1SMhczT80OzFvwPSrjGq0AWIUXuAxMB3B GGAbkWgtW8xdQ1ibwX+75drVXFuXHf6pW8ani+QpQKRT/x9pKmCDE4Sy9aK6DlGa1mkt FgzMLu0Y25bLvg1geAYeGVdSeet3zkHaS7yLzP2stJ6YdPwnHz9iVxGznmvZ6pj0/cHc EXXA== X-Gm-Message-State: AOAM533bncScreiZTTdy/D7YjLl7YBDJyEQBMXgfHELudtAFa/S81bzs o9FkxlfbIVntamEI50wAu74pFQ== X-Google-Smtp-Source: ABdhPJxp+ISq3NZJ3C2Q/F96qDWvW8mSZfGkeL0XXlKA3QTGQuIjYnlS+xXGaaee3syOfYi3VlYuvw== X-Received: by 2002:a05:6a00:2310:b0:505:a8ac:40e7 with SMTP id h16-20020a056a00231000b00505a8ac40e7mr24183433pfh.11.1652257903964; Wed, 11 May 2022 01:31:43 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:43 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 09/16] riscv: Add ptrace vector support Date: Wed, 11 May 2022 08:31:19 +0000 Message-Id: <33d5a0f0e3a689831be52d3cfcf4720115edb868.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds ptrace support for riscv vector. The vector registers will be saved in datap pointer of __riscv_v_state. This pointer will be set right after the __riscv_v_state data structure then it will be put in ubuf for ptrace system call to get or set. It will check if the datap got from ubuf is set to the correct address or not when the ptrace system call is trying to set the vector registers. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/uapi/asm/ptrace.h | 6 +++ arch/riscv/kernel/ptrace.c | 71 ++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 1 + 3 files changed, 78 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi= /asm/ptrace.h index 6ee1ca2edfa7..2491875be80d 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -94,6 +94,12 @@ struct __riscv_v_state { */ }; =20 +/* + * According to spec: The number of bits in a single vector register, + * VLEN >=3D ELEN, which must be a power of 2, and must be no greater than + * 2^16 =3D 65536bits =3D 8192bytes + */ +#define RISCV_MAX_VLENB (8192) #endif /* __ASSEMBLY__ */ =20 #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index 793c7da0554b..6f5d88220c84 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -26,6 +26,9 @@ enum riscv_regset { #ifdef CONFIG_FPU REGSET_F, #endif +#ifdef CONFIG_VECTOR + REGSET_V, +#endif }; =20 static int riscv_gpr_get(struct task_struct *target, @@ -82,6 +85,64 @@ static int riscv_fpr_set(struct task_struct *target, } #endif =20 +#ifdef CONFIG_VECTOR +static int riscv_vr_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct __riscv_v_state *vstate =3D &target->thread.vstate; + + /* + * Ensure the vector registers have been saved to the memory before + * copying them to membuf. + */ + if (target =3D=3D current) + vstate_save(current, task_pt_regs(current)); + + /* Copy vector header from vstate. */ + membuf_write(&to, vstate, RISCV_V_STATE_DATAP); + membuf_zero(&to, sizeof(void *)); +#if __riscv_xlen =3D=3D 32 + membuf_zero(&to, sizeof(__u32)); +#endif + + /* Copy all the vector registers from vstate. */ + return membuf_write(&to, vstate->datap, riscv_vsize); +} + +static int riscv_vr_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret, size; + struct __riscv_v_state *vstate =3D &target->thread.vstate; + + /* Copy rest of the vstate except datap and __padding. */ + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0, + RISCV_V_STATE_DATAP); + if (unlikely(ret)) + return ret; + + /* Skip copy datap. */ + size =3D sizeof(vstate->datap); + count -=3D size; + ubuf +=3D size; +#if __riscv_xlen =3D=3D 32 + /* Skip copy _padding. */ + size =3D sizeof(vstate->__padding); + count -=3D size; + ubuf +=3D size; +#endif + + /* Copy all the vector registers. */ + pos =3D 0; + ret =3D user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap, + 0, riscv_vsize); + return ret; +} +#endif + static const struct user_regset riscv_user_regset[] =3D { [REGSET_X] =3D { .core_note_type =3D NT_PRSTATUS, @@ -101,6 +162,16 @@ static const struct user_regset riscv_user_regset[] = =3D { .set =3D riscv_fpr_set, }, #endif +#ifdef CONFIG_VECTOR + [REGSET_V] =3D { + .core_note_type =3D NT_RISCV_VECTOR, + .align =3D 16, + .n =3D (32 * RISCV_MAX_VLENB)/sizeof(__u32), + .size =3D sizeof(__u32), + .regset_get =3D riscv_vr_get, + .set =3D riscv_vr_set, + }, +#endif }; =20 static const struct user_regset_view riscv_user_native_view =3D { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 7ce993e6786c..b4e8d7dde15b 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -436,6 +436,7 @@ typedef struct elf64_shdr { #define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */ #define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */ #define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */ +#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */ =20 /* Note types with note name "GNU" */ #define NT_GNU_PROPERTY_TYPE_0 5 --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE72DC433F5 for ; Wed, 11 May 2022 08:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243715AbiEKIcv (ORCPT ); Wed, 11 May 2022 04:32:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243828AbiEKIbt (ORCPT ); Wed, 11 May 2022 04:31:49 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18D9C27CD5 for ; Wed, 11 May 2022 01:31:46 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id l11-20020a17090a49cb00b001d923a9ca99so1450242pjm.1 for ; Wed, 11 May 2022 01:31:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=knp0cFUX68YXmasBp7zCeiKDqtafu8GC4P5SG+qc96s=; b=H6IZ3cvzvAlN+sUIDWTQC6TuSPON8N+diUcE7N3L7rxqyJ5+7Nzh9ovpvYbD2DW/J6 rOw1wLx64shfJ7SCj2dtxpvX3x3ML9h9rpmO2oHyHemeMsj1+eiXaxzBOFAnW0oAgMwx jDidZSUQjvuhPB/frAmyKDscP1YuEfTMs8frFrY+zn/TtyG4jW39js+/sP1nfDgQCeD1 C7aTgixJbkFzhdz58DjORfRxSGdHTyZGJqgEw65FtIanuzTtdNYJ+2Q8pLMG/VKUKj9S YHHv8cPGuOt/bM5uu+zqPk6ssgsZ14mbk3X0HS21I41FzvOAdumThc1Gq/PPS1APEl8V Vamg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=knp0cFUX68YXmasBp7zCeiKDqtafu8GC4P5SG+qc96s=; b=UaaHmx4JqDrA+8hWkh+oF0aXe9alqHIHB9unqZZvnAHf3jvIRuNhcZSPyzxjfB5KN3 xcEjMM54IpPlMrJNGiYjvLuYQm/bpw18zqufWP9uCWSngZlrI0YA6oST69JWG7HYVByx kRmhDLQlggg26ztAbveg+Ipf7O+FUeNWnP1ciHG+moJLGku+DbBuvr0ZlI8vS31kfnsa vgFZdZTyMrUnDN3AuD46wTaYcz1osjbgxPakHrCxykyyhcgODhqbldiqejrKDZvnNr3g 3r9BXZAtiy/zyNtwoAAG6XBpNApkkphJNJ0MYesDUIMnMhpp40LL5Zv0eOFRHK9RJsBM r7RA== X-Gm-Message-State: AOAM530/qupVyA8b8CdwxSqb/q60KbkxOactYa3zH0TLHgNVQqfEdC+5 /ALiKbA4D2DV59T+UcsNX+Z/Hw== X-Google-Smtp-Source: ABdhPJzLDEDEZBimm9+VXNZCVWI58MveCHWQ80jkKxcXiRXLgAomiTeX4iswid/G5PPyhxFV9VXxJw== X-Received: by 2002:a17:902:8f8d:b0:15b:7b98:22e6 with SMTP id z13-20020a1709028f8d00b0015b7b9822e6mr24318754plo.102.1652257905563; Wed, 11 May 2022 01:31:45 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:45 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 10/16] riscv: Add sigcontext save/restore for vector Date: Wed, 11 May 2022 08:31:20 +0000 Message-Id: <055b74196f945ab09c97e229ad54b2c07e55bf90.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds sigcontext save/restore for vector. The vector registers will be saved in datap pointer. The datap pointer will be allocated dynamically when the task needs in kernel space. The datap pointer will be set right after the __riscv_v_state data structure to save all the vector registers in the signal handler stack. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/uapi/asm/sigcontext.h | 24 ++++ arch/riscv/kernel/asm-offsets.c | 2 + arch/riscv/kernel/setup.c | 4 + arch/riscv/kernel/signal.c | 165 ++++++++++++++++++++++- 4 files changed, 191 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/uapi/asm/sigcontext.h b/arch/riscv/include/= uapi/asm/sigcontext.h index 84f2dfcfdbce..b8a0fd7d7cfc 100644 --- a/arch/riscv/include/uapi/asm/sigcontext.h +++ b/arch/riscv/include/uapi/asm/sigcontext.h @@ -8,6 +8,23 @@ =20 #include =20 +/* The Magic number for signal context frame header. */ +#define RVV_MAGIC 0x53465457 +#define END_MAGIC 0x0 + +/* The size of END signal context header. */ +#define END_HDR_SIZE 0x0 + +struct __riscv_ctx_hdr { + __u32 magic; + __u32 size; +}; + +struct __sc_riscv_v_state { + struct __riscv_ctx_hdr head; + struct __riscv_v_state v_state; +} __attribute__((aligned(16))); + /* * Signal context structure * @@ -17,6 +34,13 @@ struct sigcontext { struct user_regs_struct sc_regs; union __riscv_fp_state sc_fpregs; + /* + * 4K + 128 reserved for vector state and future expansion. + * This space is enough to store the vector context whose VLENB + * is less or equal to 128. + * (The size of the vector context is 4144 byte as VLENB is 128) + */ + __u8 __reserved[4224] __attribute__((__aligned__(16))); }; =20 #endif /* _UAPI_ASM_RISCV_SIGCONTEXT_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index 37e3e6a8d877..80316ef7bb78 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -75,6 +75,8 @@ void asm_offsets(void) OFFSET(TSK_STACK_CANARY, task_struct, stack_canary); #endif =20 + OFFSET(RISCV_V_STATE_MAGIC, __riscv_ctx_hdr, magic); + OFFSET(RISCV_V_STATE_SIZE, __riscv_ctx_hdr, size); OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart); OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl); OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype); diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 834eb652a7b9..36b55669b2da 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -260,6 +260,8 @@ static void __init parse_dtb(void) #endif } =20 +extern void __init init_rt_signal_env(void); + void __init setup_arch(char **cmdline_p) { parse_dtb(); @@ -295,6 +297,8 @@ void __init setup_arch(char **cmdline_p) #endif =20 riscv_fill_hwcap(); + + init_rt_signal_env(); } =20 static int __init topology_init(void) diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 9f4e59f80551..21b48bddeb8f 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -18,15 +18,16 @@ #include =20 extern u32 __user_rt_sigreturn[2]; +static size_t rvv_sc_size; =20 #define DEBUG_SIG 0 =20 struct rt_sigframe { struct siginfo info; - struct ucontext uc; #ifndef CONFIG_MMU u32 sigreturn_code[2]; #endif + struct ucontext uc; }; =20 #ifdef CONFIG_FPU @@ -83,16 +84,155 @@ static long save_fp_state(struct pt_regs *regs, #define restore_fp_state(task, regs) (0) #endif =20 +#ifdef CONFIG_VECTOR +static long restore_v_state(struct pt_regs *regs, void **sc_reserved_ptr) +{ + long err; + struct __sc_riscv_v_state __user *state =3D (struct __sc_riscv_v_state *)= (*sc_reserved_ptr); + void *datap; + __u32 magic; + __u32 size; + + /* Get magic number and check it. */ + err =3D __get_user(magic, &state->head.magic); + err =3D __get_user(size, &state->head.size); + if (unlikely(err)) + return err; + + if (magic !=3D RVV_MAGIC || size !=3D rvv_sc_size) + return -EINVAL; + + /* Copy everything of __sc_riscv_v_state except datap. */ + err =3D __copy_from_user(¤t->thread.vstate, &state->v_state, + RISCV_V_STATE_DATAP); + if (unlikely(err)) + return err; + + /* Copy the pointer datap itself. */ + err =3D __get_user(datap, &state->v_state.datap); + if (unlikely(err)) + return err; + + + /* Copy the whole vector content from user space datap. */ + err =3D __copy_from_user(current->thread.vstate.datap, datap, riscv_vsize= ); + if (unlikely(err)) + return err; + + vstate_restore(current, regs); + + /* Move sc_reserved_ptr to point the next signal context frame. */ + *sc_reserved_ptr +=3D size; + + return err; +} + +static long save_v_state(struct pt_regs *regs, void **sc_reserved_free_ptr) +{ + /* + * Put __sc_riscv_v_state to the user's signal context space pointed + * by sc_reserved_free_ptr and the datap point the address right + * after __sc_riscv_v_state. + */ + struct __sc_riscv_v_state __user *state =3D (struct __sc_riscv_v_state *) + (*sc_reserved_free_ptr); + void *datap =3D state + 1; + long err; + + *sc_reserved_free_ptr +=3D rvv_sc_size; + + err =3D __put_user(RVV_MAGIC, &state->head.magic); + err =3D __put_user(rvv_sc_size, &state->head.size); + + vstate_save(current, regs); + /* Copy everything of vstate but datap. */ + err =3D __copy_to_user(&state->v_state, ¤t->thread.vstate, + RISCV_V_STATE_DATAP); + if (unlikely(err)) + return err; + + /* Copy the pointer datap itself. */ + err =3D __put_user(datap, &state->v_state.datap); + if (unlikely(err)) + return err; + + /* Copy the whole vector content to user space datap. */ + err =3D __copy_to_user(datap, current->thread.vstate.datap, riscv_vsize); + + return err; +} +#else +#define save_v_state(task, regs) (0) +#define restore_v_state(task, regs) (0) +#endif + static long restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc) { long err; + void *sc_reserved_ptr =3D sc->__reserved; /* sc_regs is structured the same as the start of pt_regs */ err =3D __copy_from_user(regs, &sc->sc_regs, sizeof(sc->sc_regs)); /* Restore the floating-point state. */ if (has_fpu()) err |=3D restore_fp_state(regs, &sc->sc_fpregs); + + while (1 && !err) { + __u32 magic, size; + struct __riscv_ctx_hdr *head =3D (struct __riscv_ctx_hdr *)sc_reserved_p= tr; + + err |=3D __get_user(magic, &head->magic); + err |=3D __get_user(size, &head->size); + if (err) + goto done; + + switch (magic) { + case 0: + if (size) + goto invalid; + goto done; + case RVV_MAGIC: + if (!has_vector()) + goto invalid; + if (size !=3D rvv_sc_size) + goto invalid; + err |=3D restore_v_state(regs, &sc_reserved_ptr); + break; + default: + goto invalid; + } + } +done: return err; + +invalid: + return -EINVAL; +} + +static size_t cal_rt_frame_size(void) +{ + struct rt_sigframe __user *frame; + static size_t frame_size; + size_t total_context_size =3D 0; + size_t sc_reserved_size =3D sizeof(frame->uc.uc_mcontext.__reserved); + + if (frame_size) + goto done; + + frame_size =3D sizeof(*frame); + + if (has_vector()) + total_context_size +=3D rvv_sc_size; + /* Preserved a __riscv_ctx_hdr for END signal context header. */ + total_context_size +=3D sizeof(struct __riscv_ctx_hdr); + + if (total_context_size > sc_reserved_size) + frame_size +=3D (total_context_size - sc_reserved_size); + + frame_size =3D round_up(frame_size, 16); +done: + return frame_size; + } =20 SYSCALL_DEFINE0(rt_sigreturn) @@ -101,13 +241,14 @@ SYSCALL_DEFINE0(rt_sigreturn) struct rt_sigframe __user *frame; struct task_struct *task; sigset_t set; + size_t frame_size =3D cal_rt_frame_size(); =20 /* Always make any pending restarted system calls return -EINTR */ current->restart_block.fn =3D do_no_restart_syscall; =20 frame =3D (struct rt_sigframe __user *)regs->sp; =20 - if (!access_ok(frame, sizeof(*frame))) + if (!access_ok(frame, frame_size)) goto badframe; =20 if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set))) @@ -140,11 +281,20 @@ static long setup_sigcontext(struct rt_sigframe __use= r *frame, { struct sigcontext __user *sc =3D &frame->uc.uc_mcontext; long err; + void *sc_reserved_free_ptr =3D sc->__reserved; + /* sc_regs is structured the same as the start of pt_regs */ err =3D __copy_to_user(&sc->sc_regs, regs, sizeof(sc->sc_regs)); /* Save the floating-point state. */ if (has_fpu()) err |=3D save_fp_state(regs, &sc->sc_fpregs); + /* Save the vector state. */ + if (has_vector()) + err |=3D save_v_state(regs, &sc_reserved_free_ptr); + + /* Put END __riscv_ctx_hdr at the end. */ + err =3D __put_user(END_MAGIC, &((struct __riscv_ctx_hdr *)sc_reserved_fre= e_ptr)->magic); + err =3D __put_user(END_HDR_SIZE, &((struct __riscv_ctx_hdr *)sc_reserved_= free_ptr)->size); return err; } =20 @@ -176,9 +326,10 @@ static int setup_rt_frame(struct ksignal *ksig, sigset= _t *set, { struct rt_sigframe __user *frame; long err =3D 0; + size_t frame_size =3D cal_rt_frame_size(); =20 - frame =3D get_sigframe(ksig, regs, sizeof(*frame)); - if (!access_ok(frame, sizeof(*frame))) + frame =3D get_sigframe(ksig, regs, frame_size); + if (!access_ok(frame, frame_size)) return -EFAULT; =20 err |=3D copy_siginfo_to_user(&frame->info, &ksig->info); @@ -321,3 +472,9 @@ asmlinkage __visible void do_notify_resume(struct pt_re= gs *regs, if (thread_info_flags & _TIF_NOTIFY_RESUME) resume_user_mode_work(regs); } + +void init_rt_signal_env(void); +void __init init_rt_signal_env(void) +{ + rvv_sc_size =3D sizeof(struct __sc_riscv_v_state) + riscv_vsize; +} --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68BD7C433F5 for ; Wed, 11 May 2022 08:33:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243847AbiEKIdF (ORCPT ); Wed, 11 May 2022 04:33:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243784AbiEKIbu (ORCPT ); Wed, 11 May 2022 04:31:50 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEC523E5CF for ; Wed, 11 May 2022 01:31:47 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id s16so1191692pgs.3 for ; Wed, 11 May 2022 01:31:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=Bis4bioW3cxmD3BG+PfyKzJ7bNrywOfCUDLOAVw8vgY=; b=WFvGr2NIbgp9U7DdxGvBxhPMhkRduVkZt3qfSQUEoHHWUuo+s1RlCNMCF1UQvLDGIq 4d8ZN1Ch5Sgk//2OOmGOqcpfq2sMM2m1+7mAMI7pSRwoxz/tkqc727e8x5cg/P3oUCrF IpU3KY2c6aT0gTnOCTaprnqjeyBxggJML8ES/33iB1M3x3g+22qo3VknBmLk0RIwvex5 6rNxQ1F8Nut4FEMvJocsnYwfzKGPyR4T+b1CpcObi3pyMJVEyNxcdA+Tkv/j9vITCSZe eVOGTqdbLzd0mXqQpW7/0oSThc4TlPSX9ddVGNP9OzUNcm6N65j0VqD0HIW1SL6rij8B uY3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=Bis4bioW3cxmD3BG+PfyKzJ7bNrywOfCUDLOAVw8vgY=; b=jHt6XumRMCZKvHj57mRcfxdo8/QLrHsXnl0zhrJ+ZEuydV3L0dZS2RK9knOXokZRz9 0ABpmoBCVZ+j1/LXFPck3A2KwBgdMqghuO3s+lWT7+qloJLnuVWUN2KOjOndpY5Enu12 haqEOJAAvBxF9HQ5iHmo60HD8Ez2HiHGckiJTl1XtVwMsxbP+ebUrQ14FFOMXaMSv0LF m/Wali8PlN7WDPoMIZYRPBIDTcWChIeXdQ4wQcvwDVDBsF+aFm7mxK9eBpd605nA1G5I QBJuM0y35bOkL7LYg5tdzK0ZJtJwj7wMSYMCDq2kBnOslPMhzSckWxaX/ZoGCLgGKTKs W59A== X-Gm-Message-State: AOAM531Kq8jbPZNXzI6eayq0UMaoaz9lhood7t+C0BIoa1lragBRdP9H w+AlDkJGfIN/LInFnd+JxObQIbFP0Y9MdQ== X-Google-Smtp-Source: ABdhPJzGFAiZqmtdDQLQBNejJetP3TJC7Wth4JnHEHTZUfXINsdVxm4agg4p2YW0MjZZggWoz6xxSw== X-Received: by 2002:a05:6a00:2402:b0:4e1:46ca:68bd with SMTP id z2-20020a056a00240200b004e146ca68bdmr23835090pfh.70.1652257907223; Wed, 11 May 2022 01:31:47 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:46 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 11/16] riscv: signal: Report signal frame size to userspace via auxv Date: Wed, 11 May 2022 08:31:21 +0000 Message-Id: <75ba9c8da9f2304335bb50fe57f12952b09d5258.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vincent Chen The vector register belongs to the signal context. They need to be stored and restored as entering and leaving the signal handler. According to the V-extension specification, the maximum length of the vector registers can be 2^(XLEN-1). Hence, if userspace refers to the MINSIGSTKSZ to create a sigframe, it may not be enough. To resolve this problem, this patch refers to the commit 94b07c1f8c39c ("arm64: signal: Report signal frame size to userspace via auxv") to enable userspace to know the minimum required sigframe size through the auxiliary vector and use it to allocate enough memory for signal context. Signed-off-by: Greentime Hu Signed-off-by: Vincent Chen --- arch/riscv/include/asm/elf.h | 41 +++++++++++++++++----------- arch/riscv/include/asm/processor.h | 2 ++ arch/riscv/include/uapi/asm/auxvec.h | 1 + arch/riscv/kernel/signal.c | 8 ++++++ 4 files changed, 36 insertions(+), 16 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f53c40026c7a..72e02a31a279 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -61,22 +61,31 @@ extern unsigned long elf_hwcap; #define ELF_PLATFORM (NULL) =20 #ifdef CONFIG_MMU -#define ARCH_DLINFO \ -do { \ - NEW_AUX_ENT(AT_SYSINFO_EHDR, \ - (elf_addr_t)current->mm->context.vdso); \ - NEW_AUX_ENT(AT_L1I_CACHESIZE, \ - get_cache_size(1, CACHE_TYPE_INST)); \ - NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ - get_cache_geometry(1, CACHE_TYPE_INST)); \ - NEW_AUX_ENT(AT_L1D_CACHESIZE, \ - get_cache_size(1, CACHE_TYPE_DATA)); \ - NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ - get_cache_geometry(1, CACHE_TYPE_DATA)); \ - NEW_AUX_ENT(AT_L2_CACHESIZE, \ - get_cache_size(2, CACHE_TYPE_UNIFIED)); \ - NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ - get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ +#define ARCH_DLINFO \ +do { \ + NEW_AUX_ENT(AT_SYSINFO_EHDR, \ + (elf_addr_t)current->mm->context.vdso); \ + NEW_AUX_ENT(AT_L1I_CACHESIZE, \ + get_cache_size(1, CACHE_TYPE_INST)); \ + NEW_AUX_ENT(AT_L1I_CACHEGEOMETRY, \ + get_cache_geometry(1, CACHE_TYPE_INST)); \ + NEW_AUX_ENT(AT_L1D_CACHESIZE, \ + get_cache_size(1, CACHE_TYPE_DATA)); \ + NEW_AUX_ENT(AT_L1D_CACHEGEOMETRY, \ + get_cache_geometry(1, CACHE_TYPE_DATA)); \ + NEW_AUX_ENT(AT_L2_CACHESIZE, \ + get_cache_size(2, CACHE_TYPE_UNIFIED)); \ + NEW_AUX_ENT(AT_L2_CACHEGEOMETRY, \ + get_cache_geometry(2, CACHE_TYPE_UNIFIED)); \ + /* \ + * Should always be nonzero unless there's a kernel bug. \ + * If we haven't determined a sensible value to give to \ + * userspace, omit the entry: \ + */ \ + if (likely(signal_minsigstksz)) \ + NEW_AUX_ENT(AT_MINSIGSTKSZ, signal_minsigstksz); \ + else \ + NEW_AUX_ENT(AT_IGNORE, 0); \ } while (0) #define ARCH_HAS_SETUP_ADDITIONAL_PAGES struct linux_binprm; diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 91f1c318328e..ea2518f092e1 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_PROCESSOR_H =20 #include +#include =20 #include =20 @@ -82,6 +83,7 @@ int riscv_of_parent_hartid(struct device_node *node); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struc= t *src); =20 +extern unsigned long signal_minsigstksz __ro_after_init; #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/include/uapi/asm/auxvec.h b/arch/riscv/include/uapi= /asm/auxvec.h index 32c73ba1d531..6610d24e6662 100644 --- a/arch/riscv/include/uapi/asm/auxvec.h +++ b/arch/riscv/include/uapi/asm/auxvec.h @@ -33,5 +33,6 @@ =20 /* entries in ARCH_DLINFO */ #define AT_VECTOR_SIZE_ARCH 7 +#define AT_MINSIGSTKSZ 51 =20 #endif /* _UAPI_ASM_RISCV_AUXVEC_H */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 21b48bddeb8f..8e7f20cb0404 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -473,8 +473,16 @@ asmlinkage __visible void do_notify_resume(struct pt_r= egs *regs, resume_user_mode_work(regs); } =20 +unsigned long __ro_after_init signal_minsigstksz; + void init_rt_signal_env(void); void __init init_rt_signal_env(void) { rvv_sc_size =3D sizeof(struct __sc_riscv_v_state) + riscv_vsize; + /* + * Determine the stack space required for guaranteed signal delivery. + * The signal_minsigstksz will be populated into the AT_MINSIGSTKSZ entry + * in the auxiliary array at process startup. + */ + signal_minsigstksz =3D cal_rt_frame_size(); } --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E6B1C433EF for ; Wed, 11 May 2022 08:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244028AbiEKIdK (ORCPT ); Wed, 11 May 2022 04:33:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243754AbiEKIbv (ORCPT ); Wed, 11 May 2022 04:31:51 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F3C04093F for ; Wed, 11 May 2022 01:31:49 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id l11so1158766pgt.13 for ; Wed, 11 May 2022 01:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=d5eGDjeX0WtjJYLoK9lC54oqBkAZccKKssb+x5eT3io=; b=iYnGe0exDgqdywSyQuhIdvBf1RHggnu0dObhEnYBHQQbM+yKgqsGRyX/Atehe9eZvg esCKpjWakevIWleCN227lTxkCCAVereCYJU+L7wzGM043jalATLmQoLyINCAqdRMalAe lKcOdAP/C1kCxzQysxFlKZTCkSmIO1Mr37aBmjfJdnrDbi8dr5Y7P+xLPCrw03+tladG 5ceOWLZ5L0q2roUvAcxbpplc/DFLtkTyo8a/c7+q/XIG5BNzLk2lKfWPODtJQFdfVZZH ti81Nt7aUw+u7q7y5K61cSzyd7fCKO5Gsq6ilottjhhOVApowJXqVoCMK3pJkMduhbAU Mk4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=d5eGDjeX0WtjJYLoK9lC54oqBkAZccKKssb+x5eT3io=; b=NODVr4VErlzZ2bC2IOPcCMnPz+xCOOweHA0jWfoGSyMds0gVoiKZsoIRvANUYcU1CM VqDEZRQBenNoWziIlRPK89wyRmDLIPe8p5CMZ7hB+dk52OFijddxkGgWHMgiUlEQh0GY DszP35FgA2HO+seDJGVUM3XmdN1LQSt+rN16baWOjD4Aet5/zXkxNJNDS/ttnRyjYoM3 1MyonbwJxmZ7IMcJCEHjKIUNIziroAGuw9MxUlGOMjn3oPrlx/LOp1eQ/GaRDbZh2Nlk o8HvXHg/K1O1XbRb3S/3aGDUEgx1u4cMgZVNTZ7N6h34qB0HC9CmJ9RgLiT/epjePmBR npnA== X-Gm-Message-State: AOAM533L0DRuazYrfI9e4bVll78VvRjcGafXh8MdXhtZjbX5Mk+aVH9k 2yFJHTJ4Saub8/MJM5PVMfssZQ== X-Google-Smtp-Source: ABdhPJwnl1e2LpNP9+Zb6r9uJS8eacajAP/kxi21W/XBa1rqykPdAQz9wzaoJJVrVjjhqftovsXiYQ== X-Received: by 2002:a65:6946:0:b0:39d:a0c3:71f with SMTP id w6-20020a656946000000b0039da0c3071fmr19681317pgq.160.1652257909109; Wed, 11 May 2022 01:31:49 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:48 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 12/16] riscv: Add support for kernel mode vector Date: Wed, 11 May 2022 08:31:22 +0000 Message-Id: <444ffca9e0697166191f2d3d37522038574f3e39.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add kernel_rvv_begin() and kernel_rvv_end() function declarations and corresponding definitions in kernel_mode_vector.c These are needed to wrap uses of vector in kernel mode. Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/vector.h | 3 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/kernel_mode_vector.c | 132 +++++++++++++++++++++++++ arch/riscv/kernel/vector.S | 9 ++ 4 files changed, 145 insertions(+) create mode 100644 arch/riscv/kernel/kernel_mode_vector.c diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vecto= r.h index 16304b0c6a6f..a59841cc81fb 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -10,5 +10,8 @@ =20 void rvv_enable(void); void rvv_disable(void); +void kernel_rvv_begin(void); +void kernel_rvv_end(void); +void vector_flush_cpu_state(void); =20 #endif /* ! __ASM_RISCV_VECTOR_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 5dc550a9fb45..68a6fb0fdac8 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -41,6 +41,7 @@ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ obj-$(CONFIG_RISCV_M_MODE) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_VECTOR) +=3D vector.o +obj-$(CONFIG_VECTOR) +=3D kernel_mode_vector.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D cpu_ops.o diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/ker= nel_mode_vector.c new file mode 100644 index 000000000000..0277168af0c5 --- /dev/null +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2012 ARM Ltd. + * Author: Catalin Marinas + * Copyright (C) 2017 Linaro Ltd. + * Copyright (C) 2021 SiFive + */ +#include +#include +#include +#include +#include + +#include +#include + +DECLARE_PER_CPU(bool, vector_context_busy); +DEFINE_PER_CPU(bool, vector_context_busy); + +/* + * may_use_vector - whether it is allowable at this time to issue vector + * instructions or access the vector register file + * + * Callers must not assume that the result remains true beyond the next + * preempt_enable() or return from softirq context. + */ +static __must_check inline bool may_use_vector(void) +{ + /* + * vector_context_busy is only set while preemption is disabled, + * and is clear whenever preemption is enabled. Since + * this_cpu_read() is atomic w.r.t. preemption, vector_context_busy + * cannot change under our feet -- if it's set we cannot be + * migrated, and if it's clear we cannot be migrated to a CPU + * where it is set. + */ + return !in_irq() && !irqs_disabled() && !in_nmi() && + !this_cpu_read(vector_context_busy); +} + +/* + * Claim ownership of the CPU vector context for use by the calling contex= t. + * + * The caller may freely manipulate the vector context metadata until + * put_cpu_vector_context() is called. + */ +static void get_cpu_vector_context(void) +{ + bool busy; + + preempt_disable(); + busy =3D __this_cpu_xchg(vector_context_busy, true); + + WARN_ON(busy); +} + +/* + * Release the CPU vector context. + * + * Must be called from a context in which get_cpu_vector_context() was + * previously called, with no call to put_cpu_vector_context() in the + * meantime. + */ +static void put_cpu_vector_context(void) +{ + bool busy =3D __this_cpu_xchg(vector_context_busy, false); + + WARN_ON(!busy); + preempt_enable(); +} + +/* + * kernel_rvv_begin(): obtain the CPU vector registers for use by the call= ing + * context + * + * Must not be called unless may_use_vector() returns true. + * Task context in the vector registers is saved back to memory as necessa= ry. + * + * A matching call to kernel_rvv_end() must be made before returning from = the + * calling context. + * + * The caller may freely use the vector registers until kernel_rvv_end() is + * called. + */ +void kernel_rvv_begin(void) +{ + if (WARN_ON(!has_vector())) + return; + + WARN_ON(!may_use_vector()); + + /* Acquire kernel mode vector */ + get_cpu_vector_context(); + + /* Save vector state, if any */ + vstate_save(current, task_pt_regs(current)); + + /* Enable vector */ + rvv_enable(); + + /* Invalidate vector regs */ + vector_flush_cpu_state(); +} +EXPORT_SYMBOL_GPL(kernel_rvv_begin); + +/* + * kernel_rvv_end(): give the CPU vector registers back to the current task + * + * Must be called from a context in which kernel_rvv_begin() was previously + * called, with no call to kernel_rvv_end() in the meantime. + * + * The caller must not use the vector registers after this function is cal= led, + * unless kernel_rvv_begin() is called again in the meantime. + */ +void kernel_rvv_end(void) +{ + if (WARN_ON(!has_vector())) + return; + + /* Invalidate vector regs */ + vector_flush_cpu_state(); + + /* Restore vector state, if any */ + vstate_restore(current, task_pt_regs(current)); + + /* disable vector */ + rvv_disable(); + + /* release kernel mode vector */ + put_cpu_vector_context(); +} +EXPORT_SYMBOL_GPL(kernel_rvv_end); diff --git a/arch/riscv/kernel/vector.S b/arch/riscv/kernel/vector.S index 9f7dc70c4443..9c2de823c0d9 100644 --- a/arch/riscv/kernel/vector.S +++ b/arch/riscv/kernel/vector.S @@ -91,3 +91,12 @@ ENTRY(rvv_disable) csrc CSR_STATUS, status ret ENDPROC(rvv_disable) + +ENTRY(vector_flush_cpu_state) + vsetvli t0, x0, e8, m8, ta, ma + vmv.v.i v0, 0 + vmv.v.i v8, 0 + vmv.v.i v16, 0 + vmv.v.i v24, 0 + ret +ENDPROC(vector_flush_cpu_state) --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76906C433F5 for ; Wed, 11 May 2022 08:33:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238408AbiEKId2 (ORCPT ); Wed, 11 May 2022 04:33:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243842AbiEKIbx (ORCPT ); Wed, 11 May 2022 04:31:53 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4FEF4130E for ; Wed, 11 May 2022 01:31:51 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id q76so1168640pgq.10 for ; Wed, 11 May 2022 01:31:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=p1pBW1G0xf+nuHQeCYtlJM/ltXiGJIWoD7vDEEsgp4w=; b=WDIcU8bjpBGvAlkTDqgBOmYbiNsSiBNbDZF3wLdzgCr6ACi1CJQw5lvUk4mVQ3jZPG zqch3k0NX6mq72w13vNYULGE9N43XVtl22wqzxEY7sWjF1DweqWQzYfyb4JuNTyD06Ce nszmu2H6sdp+CzvOEl2G8xJB6TV5B9vrP1Xv9B8xaFVrbxJ/8psDZA8wz9Gu7+YCkjg4 i9P/bxF99NpWssE77t5A5M+KLIo7j4QsVaiIMZ5etgZyqKC28D1JfjSzjcTJYchsQwWe gqbSjpTODDEILDVh9tnAwH3ubh1hKeKDnNKyZ110Axd4MCVREtpyvImghTPUWjly/UrS G5oA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=p1pBW1G0xf+nuHQeCYtlJM/ltXiGJIWoD7vDEEsgp4w=; b=eKPCKUpa2YnOpY+tNDzEDIoIaiiI1NoJLUnzkUlk1IB7i1jrW2oYW/KgxfdiCd3B33 /4Z+y5GrfpZsempL8cIllS91ndMCxZ5oEoFBbKg0IS2wInrwmDCeqo7yLn+JmB9iSrb+ oylqnUrScxz8uPbHQIfhHczZCk2V0iydmy532tXKKw3TfTJNfNmULJZTZpRgrWGaLtVI SLIKMJTGWlPmOQ5tzIvFc8Gk/Ah0ySgaC0fXO2TqlmLfQJD2fXKu6VhYfFqvAsYhH40U OsRSQy4FW3EFzm0+Gwz6jt6pvUVL6S7IXx80OhalOCA4mEGGbLoGTI5mXapNThUHNSqE gLDw== X-Gm-Message-State: AOAM531u23d+XY3ICF5c9ex8tI+MPfadlWHdeChzbJZpkmhPGqdMXopO XNouPLB9T/B1RynEmgUYAGwpxw== X-Google-Smtp-Source: ABdhPJyDvWf/WS9fKbB9NiiG/YzFYnTHR8XFEkmyHpLk0Zno8zCPZD4WsMMxgDoffXFPgK1E6als1g== X-Received: by 2002:a63:8948:0:b0:3da:ec12:1b1c with SMTP id v69-20020a638948000000b003daec121b1cmr5526407pgd.598.1652257910737; Wed, 11 May 2022 01:31:50 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:50 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 13/16] riscv: Add vector extension XOR implementation Date: Wed, 11 May 2022 08:31:23 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds support for vector optimized XOR and it is tested in qemu. Co-developed-by: Han-Kuan Chen Signed-off-by: Han-Kuan Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/xor.h | 82 ++++++++++++++++++++++++++++++++++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/xor.S | 81 +++++++++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+) create mode 100644 arch/riscv/include/asm/xor.h create mode 100644 arch/riscv/lib/xor.S diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h new file mode 100644 index 000000000000..d1f2eeb14afb --- /dev/null +++ b/arch/riscv/include/asm/xor.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2021 SiFive + */ + +#include +#include +#ifdef CONFIG_VECTOR +#include +#include + +void xor_regs_2_(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2); +void xor_regs_3_(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2, + const unsigned long * __restrict p3); +void xor_regs_4_(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2, + const unsigned long * __restrict p3, + const unsigned long * __restrict p4); +void xor_regs_5_(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2, + const unsigned long * __restrict p3, + const unsigned long * __restrict p4, + const unsigned long * __restrict p5); + +static void xor_rvv_2(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2) +{ + kernel_rvv_begin(); + xor_regs_2_(bytes, p1, p2); + kernel_rvv_end(); +} + +static void xor_rvv_3(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2, + const unsigned long * __restrict p3) +{ + kernel_rvv_begin(); + xor_regs_3_(bytes, p1, p2, p3); + kernel_rvv_end(); +} + +static void xor_rvv_4(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2, + const unsigned long * __restrict p3, + const unsigned long * __restrict p4) +{ + kernel_rvv_begin(); + xor_regs_4_(bytes, p1, p2, p3, p4); + kernel_rvv_end(); +} + +static void xor_rvv_5(unsigned long bytes, unsigned long * __restrict p1, + const unsigned long * __restrict p2, + const unsigned long * __restrict p3, + const unsigned long * __restrict p4, + const unsigned long * __restrict p5) +{ + kernel_rvv_begin(); + xor_regs_5_(bytes, p1, p2, p3, p4, p5); + kernel_rvv_end(); +} + +static struct xor_block_template xor_block_rvv =3D { + .name =3D "rvv", + .do_2 =3D xor_rvv_2, + .do_3 =3D xor_rvv_3, + .do_4 =3D xor_rvv_4, + .do_5 =3D xor_rvv_5 +}; + +#undef XOR_TRY_TEMPLATES +#define XOR_TRY_TEMPLATES \ + do { \ + xor_speed(&xor_block_8regs); \ + xor_speed(&xor_block_32regs); \ + if (has_vector()) { \ + xor_speed(&xor_block_rvv);\ + } \ + } while (0) +#endif diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 25d5c9664e57..acd87ac86d24 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -7,3 +7,4 @@ lib-$(CONFIG_MMU) +=3D uaccess.o lib-$(CONFIG_64BIT) +=3D tishift.o =20 obj-$(CONFIG_FUNCTION_ERROR_INJECTION) +=3D error-inject.o +lib-$(CONFIG_VECTOR) +=3D xor.o diff --git a/arch/riscv/lib/xor.S b/arch/riscv/lib/xor.S new file mode 100644 index 000000000000..3bc059e18171 --- /dev/null +++ b/arch/riscv/lib/xor.S @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2021 SiFive + */ +#include +#include +#include + +ENTRY(xor_regs_2_) + vsetvli a3, a0, e8, m8, ta, ma + vle8.v v0, (a1) + vle8.v v8, (a2) + sub a0, a0, a3 + vxor.vv v16, v0, v8 + add a2, a2, a3 + vse8.v v16, (a1) + add a1, a1, a3 + bnez a0, xor_regs_2_ + ret +END(xor_regs_2_) +EXPORT_SYMBOL(xor_regs_2_) + +ENTRY(xor_regs_3_) + vsetvli a4, a0, e8, m8, ta, ma + vle8.v v0, (a1) + vle8.v v8, (a2) + sub a0, a0, a4 + vxor.vv v0, v0, v8 + vle8.v v16, (a3) + add a2, a2, a4 + vxor.vv v16, v0, v16 + add a3, a3, a4 + vse8.v v16, (a1) + add a1, a1, a4 + bnez a0, xor_regs_3_ + ret +END(xor_regs_3_) +EXPORT_SYMBOL(xor_regs_3_) + +ENTRY(xor_regs_4_) + vsetvli a5, a0, e8, m8, ta, ma + vle8.v v0, (a1) + vle8.v v8, (a2) + sub a0, a0, a5 + vxor.vv v0, v0, v8 + vle8.v v16, (a3) + add a2, a2, a5 + vxor.vv v0, v0, v16 + vle8.v v24, (a4) + add a3, a3, a5 + vxor.vv v16, v0, v24 + add a4, a4, a5 + vse8.v v16, (a1) + add a1, a1, a5 + bnez a0, xor_regs_4_ + ret +END(xor_regs_4_) +EXPORT_SYMBOL(xor_regs_4_) + +ENTRY(xor_regs_5_) + vsetvli a6, a0, e8, m8, ta, ma + vle8.v v0, (a1) + vle8.v v8, (a2) + sub a0, a0, a6 + vxor.vv v0, v0, v8 + vle8.v v16, (a3) + add a2, a2, a6 + vxor.vv v0, v0, v16 + vle8.v v24, (a4) + add a3, a3, a6 + vxor.vv v0, v0, v24 + vle8.v v8, (a5) + add a4, a4, a6 + vxor.vv v16, v0, v8 + add a5, a5, a6 + vse8.v v16, (a1) + add a1, a1, a6 + bnez a0, xor_regs_5_ + ret +END(xor_regs_5_) +EXPORT_SYMBOL(xor_regs_5_) --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AE36C433F5 for ; Wed, 11 May 2022 08:34:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236818AbiEKIeE (ORCPT ); Wed, 11 May 2022 04:34:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243851AbiEKIby (ORCPT ); Wed, 11 May 2022 04:31:54 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E2014161F for ; Wed, 11 May 2022 01:31:53 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id j6so1342087pfe.13 for ; Wed, 11 May 2022 01:31:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=x6ToxOR7YfZxDHTS67U76S1k5UUycsNd/uMEmp36m6E=; b=VJW9tSadeCifXTSdxhfEPeWI4fmioJpfsAgUeEhgGTlogv/K4ujejUPly/Cl2QSK1G NlwZ2g3QTBsmoNm1akHbtZkL/AUmUSISj2dqsBrd3osoqB0a6ze17V2FZS7Pt99rAecC /5JAwlfta5wfTLVUz/+oJXyKOQ6/n8f+CdFhSaivIc8hwSgKlBtW+UYj5IgVtl61UFMC UMggQKUx5Ai28e6DJdlissZ0g+vzTygRMdmmZ7G6jm0B/Dy5sZa2p1YO7mHAqbqOeYgr OToNGNj4ximPHXedlAxGrQNc+/oqfay6+pTxvUVFTgkVQek2yFgCSRB/V0/RqPQTILR1 AjNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=x6ToxOR7YfZxDHTS67U76S1k5UUycsNd/uMEmp36m6E=; b=bIigw0RT8a9huGZMyfWt7vwuL7EQAKuXoYwlQpLI8FetM+Hj0IQnKRQhZZu+k4ULBh VrtC3e0S2R/EF6C6unec+hS9NGeoxmTjDeD+uYvQ+ffl2A4ZsNotSHLL6+1BVU7fJWIl 8drZWcbDRIFOl7zJfpu1mYVfXGj5Q9FjWjUVuaQPbtKkPMSLp/y/OpSJzE+uf+/lI63W jwlG8o5HLjw/BCbXoQ9UgBBjI9trQ4nI9rRG7tzdXg1MVvD69LyUwUOqBSMrfhwUc7WX ni80LGW2AcUDx4cw4P48NdxNijJmd9LN/vGZeiXVZ0019Fy/ZwRM4FhUwQ6qJPYqdJzY C98g== X-Gm-Message-State: AOAM531QgqnLe8yYuFEWM1rb+Cz8iW10w96jxEgY7tD3gXUSVfwBEd7C 7NAa+ocvPswWlJSuYj+QzVJC1Q== X-Google-Smtp-Source: ABdhPJx15RGqfuPuZb8T8Y8dM3Hj7bcyXhoTbZu79yl5bVMGa2Ii0EiR3p7uOOyPV5w4bDico4Q6dA== X-Received: by 2002:a05:6a00:2282:b0:50e:552:973a with SMTP id f2-20020a056a00228200b0050e0552973amr23550542pfe.79.1652257912480; Wed, 11 May 2022 01:31:52 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:52 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 14/16] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Date: Wed, 11 May 2022 08:31:24 +0000 Message-Id: <3929aa1c47484a6bbc96a46158e412664233bbc4.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Panic log: [ 0.018707] Unable to handle kernel NULL pointer dereference at virtual = address 0000000000000000 [ 0.023060] Oops [#1] [ 0.023214] Modules linked in: [ 0.023725] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.14.0 #33 [ 0.023955] Hardware name: SiFive,FU800 (DT) [ 0.024150] epc : __vstate_save+0x1c/0x48 [ 0.024654] ra : arch_dup_task_struct+0x70/0x108 [ 0.024815] epc : ffffffff80005ad8 ra : ffffffff800035a8 sp : ffffffff81= 203d50 [ 0.025020] gp : ffffffff812e8290 tp : ffffffff8120bdc0 t0 : 0000000000= 000000 [ 0.025216] t1 : 0000000000000000 t2 : 0000000000000000 s0 : ffffffff81= 203d80 [ 0.025424] s1 : ffffffff8120bdc0 a0 : ffffffff8120c820 a1 : 0000000000= 000000 [ 0.025659] a2 : 0000000000001000 a3 : 0000000000000000 a4 : 0000000000= 000600 [ 0.025869] a5 : ffffffff8120cdc0 a6 : ffffffe00160b400 a7 : ffffffff80= a1fe60 [ 0.026069] s2 : ffffffe0016b8000 s3 : ffffffff81204000 s4 : 0000000000= 004000 [ 0.026267] s5 : 0000000000000000 s6 : ffffffe0016b8000 s7 : ffffffe001= 6b9000 [ 0.026475] s8 : ffffffff81203ee0 s9 : 0000000000800300 s10: ffffffff81= 2e9088 [ 0.026689] s11: ffffffd004008000 t3 : 0000000000000000 t4 : 0000000000= 000100 [ 0.026900] t5 : 0000000000000600 t6 : ffffffe00167bcc4 [ 0.027057] status: 8000000000000720 badaddr: 0000000000000000 cause: 00= 0000000000000f [ 0.027344] [] __vstate_save+0x1c/0x48 [ 0.027567] [] copy_process+0x266/0x11a0 [ 0.027739] [] kernel_clone+0x90/0x2aa [ 0.027915] [] kernel_thread+0x76/0x92 [ 0.028075] [] rest_init+0x26/0xfc [ 0.028242] [] arch_call_rest_init+0x10/0x18 [ 0.028423] [] start_kernel+0x5ce/0x5fe [ 0.029188] ---[ end trace 9a59af33f7ba3df4 ]--- [ 0.029479] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.029907] ---[ end Kernel panic - not syncing: Attempted to kill the i= dle task! ]--- The NULL pointer accessing caused the kernel panic. There is a NULL pointer is because in vstate_save() function it will check (regs->status & SR_VS) =3D=3D SR_VS_DIRTY and this is true, but it shouldn't be true because vector is not used here. Since vector is not used, datap won't be allocated so it is NULL. The reason why regs->status is set to a wrong value is because pt_regs->status is put in stack and it is polluted after setup_vm() called. In prologue of setup_vm(), we can observe it will save s2 to stack however s2 is meaningless here because the caller is assembly code and s2 is just some value from previous stage. The compiler will base on calling convention to save the register to stack. Then 0x80008638 in s2 is saved to stack. It might be any value. In this failure case it is 0x80008638 and it will accidentally cause SR_VS_DIRTY to call the vstate_save() function. (gdb) info addr setup_vm Symbol "setup_vm" is a function at address 0xffffffff80802c8a. (gdb) va2pa 0xffffffff80802c8a $64 =3D 0x80a02c8a (gdb) x/10i 0x80a02c8a 0x80a02c8a: addi sp,sp,-48 0x80a02c8c: li a3,-1 0x80a02c8e: auipc a5,0xff7fd 0x80a02c92: addi a5,a5,882 0x80a02c96: sd s0,32(sp) 0x80a02c98: sd s2,16(sp) <-- store to stack After returning from setup_vm() (gdb) x/20i 0x0000000080201138 0x80201138: mv a0,s1 0x8020113a: auipc ra,0x802 0x8020113e: jalr -1200(ra) <-- jump to setup_vm() 0x80201142: auipc a0,0xa03 (gdb) p/x $sp $70 =3D 0x81404000 (gdb) p/x *(struct pt_regs*)($sp-0x120) $71 =3D { epc =3D 0x0, ra =3D 0x0, sp =3D 0x0, gp =3D 0x0, tp =3D 0x0, t0 =3D 0x0, t1 =3D 0x0, t2 =3D 0x0, s0 =3D 0x0, s1 =3D 0x0, a0 =3D 0x0, a1 =3D 0x0, a2 =3D 0x0, a3 =3D 0x81403f90, a4 =3D 0x80c04000, a5 =3D 0x1, a6 =3D 0xffffffff81337000, a7 =3D 0x81096700, s2 =3D 0x81400000, s3 =3D 0xffffffff81200000, s4 =3D 0x81403fd0, s5 =3D 0x80a02c6c, s6 =3D 0x8000000000006800, s7 =3D 0x0, s8 =3D 0xfffffffffffffff3, s9 =3D 0x80c01000, s10 =3D 0x81096700, s11 =3D 0x82200000, t3 =3D 0x81404000, t4 =3D 0x80a02dea, t5 =3D 0x0, t6 =3D 0x82200000, status =3D 0x80008638, <- Wrong value in stack!!! badaddr =3D 0x82200000, cause =3D 0x0, orig_a0 =3D 0x80201142 } (gdb) p/x $pc $72 =3D 0x80201142 (gdb) p/x sizeof(struct pt_regs) $73 =3D 0x120 Co-developed-by: ShihPo Hung Signed-off-by: ShihPo Hung Co-developed-by: Vincent Chen Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/kernel/head.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 2877af90b025..0c307c0bd3d6 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -299,6 +299,7 @@ clear_bss_done: /* Initialize page tables and relocate to virtual addresses */ la sp, init_thread_union + THREAD_SIZE XIP_FIXUP_OFFSET sp + addi sp, sp, -PT_SIZE #ifdef CONFIG_BUILTIN_DTB la a0, __dtb_start XIP_FIXUP_OFFSET a0 @@ -316,6 +317,7 @@ clear_bss_done: /* Restore C environment */ la tp, init_task la sp, init_thread_union + THREAD_SIZE + addi sp, sp, -PT_SIZE =20 #ifdef CONFIG_KASAN call kasan_early_init --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC6C8C433EF for ; Wed, 11 May 2022 08:34:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243752AbiEKIeO (ORCPT ); Wed, 11 May 2022 04:34:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243816AbiEKIb5 (ORCPT ); Wed, 11 May 2022 04:31:57 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1AF39443D7 for ; Wed, 11 May 2022 01:31:54 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id cq17-20020a17090af99100b001dc0386cd8fso1423203pjb.5 for ; Wed, 11 May 2022 01:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=renU6boUc8bjl7+T0+5P6aUpTemVDlmCU6gWIarVu9c=; b=VuzX83IZhRm4Pe99Gm3V7OoCvEp0z84v8JRxEiPiBz2aAGi9cn16IY9IcrHbA00wF2 RPK4sUNQyFimpqbf1avolryq3OyRAeepmiwY0IuVNUcYQHlVlvXbIq5XN9dINsywodV0 WkX9Co6NTbSDi03nyGX74NJOnZQQgR0bb4vrfP7Lr2DnUvwdUmxwPgGB4BMwKVVQTb9i FixbVPkUYrMIoSQD850nMr5GUM36+NdL6BxV0VT7BLJswWN1a6zwFLKOq1eeQ7/Ua7Kz VZf+HuXS+X7k5pRNuNtX3osHiAY4X69bsMo1JDtDloJxdVnEg1E0ayGVyl//Z1TZzw0s YOrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=renU6boUc8bjl7+T0+5P6aUpTemVDlmCU6gWIarVu9c=; b=GI8qW/MjNM2NRW6ghIg7MbYG9EcEPtn2FzWkmlsMWssx9eiUZ4UOXIPrH0ryplg/dg TuLvUD3oqV4/g1HJNt0zaDAJUWpcm/0l365AsHLwIOm6AQ7pQO9F58m09gK4ibHsuMTT 9pYW0F+BEx1nqejWDwXRfmvR1Whm4CNHmmtyFBUjTTRD1WIN5NqlemMNtNhoOgnu3jj3 O36+n+zZ/sf9tu2N1zYb8RVwU1ff9VL7lRaSO/NlY0bVWV/27CEp5nimk5PIot+N43d+ DxpfBkaXGar60F0oGSuRgl5VMi9x0WC8Ai5PVJCCXpCfFeHnfuqm/oFf+EAKW0rkAh3Y c/hQ== X-Gm-Message-State: AOAM533X3un7TWvQaX51QxlldtOuGxd20AjGnYR6KHqvOVhfBiVn3Crv 7weScFMOLvqex20mzY94v0AzDnJOd8Xsnw== X-Google-Smtp-Source: ABdhPJzTt/eBd9wV+KzZVC98MS1893vrJwmEN4p2oHY/UTvF/oBUGO0yuU1T278iz6ZleFC0OUckmA== X-Received: by 2002:a17:902:e851:b0:15e:d129:fb20 with SMTP id t17-20020a170902e85100b0015ed129fb20mr23797543plg.140.1652257914323; Wed, 11 May 2022 01:31:54 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:53 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 15/16] riscv: Add V extension to KVM ISA allow list Date: Wed, 11 May 2022 08:31:25 +0000 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vincent Chen Add V extension to KVM_RISCV_ISA_ALLOWED list to enable VCPU to support V extension. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kvm/vcpu.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0734e42f74f2..02ad7cf64d1c 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -33,6 +33,7 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_m ('m' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') +#define RISCV_ISA_EXT_v ('v' - 'a') =20 /* * Increse this to higher value as kernel support more ISA extensions. diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 7461f964d20a..c0a3be86d613 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -39,7 +39,8 @@ const struct kvm_stats_header kvm_vcpu_stats_header =3D { }; =20 #define KVM_RISCV_ISA_DISABLE_ALLOWED (riscv_isa_extension_mask(d) | \ - riscv_isa_extension_mask(f)) + riscv_isa_extension_mask(f) | \ + riscv_isa_extension_mask(v)) =20 #define KVM_RISCV_ISA_DISABLE_NOT_ALLOWED (riscv_isa_extension_mask(a) | \ riscv_isa_extension_mask(c) | \ --=20 2.17.1 From nobody Sun Jun 14 21:06:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90BB6C433EF for ; Wed, 11 May 2022 08:34:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243069AbiEKIeV (ORCPT ); Wed, 11 May 2022 04:34:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243757AbiEKIb7 (ORCPT ); Wed, 11 May 2022 04:31:59 -0400 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CF8B45AD2 for ; Wed, 11 May 2022 01:31:56 -0700 (PDT) Received: by mail-pj1-x102f.google.com with SMTP id iq10so1618121pjb.0 for ; Wed, 11 May 2022 01:31:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:in-reply-to :references; bh=IfVlsTAB7z7hMED1dtN6CVJwv02w28SofuIEv8aID38=; b=kUs4ehPZnLd+O9p/4BDnqDQkhpIAMDEyA3RjEu3KkBthrdUXYk8CxXqNH7d8xkX/Yr ycUya5FVQWnls35kL/H2nCa75zyIIiiiPWMsM4F1ojH73CSRqpcSAQcyu1SovzA120Pp bxishhAnO2SGaOVKFoK06QGwPo21zEeff2Pmj9dBM5VL1Zf2c1VMFI6I0m9DeRHCwdXe Ho8BWK1v5eFKmYOsIWa/mQKIRTzaKm74kKqb67TQdiNDBaGZSxOYF/Rpv0aK/3GMGajg uw7Aek8LfV6LslvTF+Y+js8dWC9iRY+bo59HTZVOsHF6HnXYF+9Rhu8hW2OtqHtr/6SL bdaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=IfVlsTAB7z7hMED1dtN6CVJwv02w28SofuIEv8aID38=; b=zS/ziJRW9uqlWNKiv9BYJerHj1NL1Obg+dnv3kmC7h3jj8L74zXELrOR+hKx5qxxXv otcihqWAlzUwl4ireObYGv6FItISydsTh/T/sP95WtiDPdzA/QsCyWU4YGFC36+316bB H5ti21dczbCwP7qI8S7ppC5Bxqy0bV1tuDpkF9Ho38DNsJYGQ++FSpAsdqyHoKG9Z0Hn WNTOV9jp3SpqlAVf2KbzwUUZk6uLnzMBM/XHCyerA42eu/BKzT/oqPzMdZTwPX9KKAwJ xeHdraX/Nu6TazNxrhPt0adv6AFk0Xdh3n+CmXf3/fn8xAxJSVbiHyFlgwmtrUmsWR7N tb/w== X-Gm-Message-State: AOAM533JuKfFFeaw8HX9PmDyDQEH73iZ2Fv2OgrJvETPvv9OGcPHfIL2 CCC0IxnuUHmaXgJhWdEV/5fDJw== X-Google-Smtp-Source: ABdhPJzLwaHw233DeREMXjw0n96HLjA5QQn/j6XYIJ3JJyY2e/6KchzzZmtlRy4PV1ArPmPG1p0FKw== X-Received: by 2002:a17:902:e886:b0:15e:8ba0:b749 with SMTP id w6-20020a170902e88600b0015e8ba0b749mr24627356plg.95.1652257916206; Wed, 11 May 2022 01:31:56 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id m10-20020aa7900a000000b0050dc7628170sm1020202pfo.74.2022.05.11.01.31.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 01:31:55 -0700 (PDT) From: Greentime Hu To: palmer@dabbelt.com, paul.walmsley@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu Subject: [PATCH v10 16/16] riscv: KVM: Add vector lazy save/restore support Date: Wed, 11 May 2022 08:31:26 +0000 Message-Id: <8174f9e04cbb55b8bdeceeb0ca6ff2bdd748290c.1652257230.git.greentime.hu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Vincent Chen This patch adds vector context save/restore for guest VCPUs. To reduce the impact on KVM performance, the implementation imitates the FP context switch mechanism to lazily store and restore the vector context only when the kernel enters/exits the in-kernel run loop and not during the KVM world switch. Signed-off-by: Vincent Chen Signed-off-by: Greentime Hu --- arch/riscv/include/asm/kvm_host.h | 2 + arch/riscv/include/asm/kvm_vcpu_vector.h | 65 +++++++++ arch/riscv/include/uapi/asm/kvm.h | 6 + arch/riscv/kernel/asm-offsets.c | 7 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 30 ++++ arch/riscv/kvm/vcpu_switch.S | 69 +++++++++ arch/riscv/kvm/vcpu_vector.c | 173 +++++++++++++++++++++++ 8 files changed, 353 insertions(+) create mode 100644 arch/riscv/include/asm/kvm_vcpu_vector.h create mode 100644 arch/riscv/kvm/vcpu_vector.c diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index cd4bbcecb0fb..60fb3de61f5c 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #define KVM_MAX_VCPUS \ @@ -122,6 +123,7 @@ struct kvm_cpu_context { unsigned long sstatus; unsigned long hstatus; union __riscv_fp_state fp; + struct __riscv_v_state vector; }; =20 struct kvm_vcpu_csr { diff --git a/arch/riscv/include/asm/kvm_vcpu_vector.h b/arch/riscv/include/= asm/kvm_vcpu_vector.h new file mode 100644 index 000000000000..1dcc1b2e05bb --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_vector.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 SiFive + * + * Authors: + * Atish Patra + * Anup Patel + * Vincent Chen + * Greentime Hu + */ + +#ifndef __KVM_VCPU_RISCV_VECTOR_H +#define __KVM_VCPU_RISCV_VECTOR_H + +#include + +struct kvm_cpu_context; + +#ifdef CONFIG_VECTOR +void __kvm_riscv_vector_save(struct kvm_cpu_context *context); +void __kvm_riscv_vector_restore(struct kvm_cpu_context *context); +void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu); +void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long isa); +void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long isa); +void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx); +void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx); +void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu); +#else +static inline void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) +{ +} + +static inline void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context= *cntx, + unsigned long isa) +{ +} + +static inline void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_cont= ext *cntx, + unsigned long isa) +{ +} + +static inline void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context = *cntx) +{ +} + +static inline void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_conte= xt *cntx) +{ +} + +static inline void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcp= u) +{ +} +#endif + +int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype); +int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype); +#endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index f808ad1ce500..b16e2f72eeee 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -123,6 +123,12 @@ struct kvm_riscv_timer { #define KVM_REG_RISCV_FP_D_REG(name) \ (offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64)) =20 +/* V extension registers are mapped as type 7 */ +#define KVM_REG_RISCV_VECTOR (0x07 << KVM_REG_RISCV_TYPE_SHIFT) +#define KVM_REG_RISCV_VECTOR_CSR_REG(name) \ + (offsetof(struct __riscv_v_state, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_VECTOR_REG(n) \ + ((n) + sizeof(struct __riscv_v_state) / sizeof(unsigned long)) #endif =20 #endif /* __LINUX_KVM_RISCV_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index 80316ef7bb78..2540b9146072 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -278,6 +278,13 @@ void asm_offsets(void) OFFSET(KVM_ARCH_FP_D_F31, kvm_cpu_context, fp.d.f[31]); OFFSET(KVM_ARCH_FP_D_FCSR, kvm_cpu_context, fp.d.fcsr); =20 + /* V extension */ + + OFFSET(KVM_ARCH_VECTOR_VSTART, kvm_cpu_context, vector.vstart); + OFFSET(KVM_ARCH_VECTOR_VL, kvm_cpu_context, vector.vl); + OFFSET(KVM_ARCH_VECTOR_VTYPE, kvm_cpu_context, vector.vtype); + OFFSET(KVM_ARCH_VECTOR_VCSR, kvm_cpu_context, vector.vcsr); + OFFSET(KVM_ARCH_VECTOR_DATAP, kvm_cpu_context, vector.datap); /* * THREAD_{F,X}* might be larger than a S-type offset can handle, but * these are used in performance-sensitive assembly so we can't resort diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index e5c56182f48f..acf39cd87fbb 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -17,6 +17,7 @@ kvm-y +=3D mmu.o kvm-y +=3D vcpu.o kvm-y +=3D vcpu_exit.o kvm-y +=3D vcpu_fp.o +kvm-y +=3D vcpu_vector.o kvm-y +=3D vcpu_switch.o kvm-y +=3D vcpu_sbi.o kvm-$(CONFIG_RISCV_SBI_V01) +=3D vcpu_sbi_v01.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index c0a3be86d613..c3e941dffcd4 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -19,6 +19,7 @@ #include #include #include +#include =20 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] =3D { KVM_GENERIC_VCPU_STATS(), @@ -74,6 +75,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) =20 kvm_riscv_vcpu_fp_reset(vcpu); =20 + kvm_riscv_vcpu_vector_reset(vcpu); + kvm_riscv_vcpu_timer_reset(vcpu); =20 WRITE_ONCE(vcpu->arch.irqs_pending, 0); @@ -110,6 +113,15 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) cntx->hstatus |=3D HSTATUS_SPVP; cntx->hstatus |=3D HSTATUS_SPV; =20 + if (has_vector()) { + cntx->vector.datap =3D kmalloc(riscv_vsize, GFP_KERNEL); + if (!cntx->vector.datap) + return -ENOMEM; + vcpu->arch.host_context.vector.datap =3D kzalloc(riscv_vsize, GFP_KERNEL= ); + if (!vcpu->arch.host_context.vector.datap) + return -ENOMEM; + } + /* By default, make CY, TM, and IR counters accessible in VU mode */ reset_csr->scounteren =3D 0x7; =20 @@ -140,6 +152,9 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) =20 /* Free unused pages pre-allocated for Stage2 page table mappings */ kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); + + /* Free vector context space for host and guest kernel */ + kvm_riscv_vcpu_free_vector_context(vcpu); } =20 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) @@ -383,6 +398,9 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu, else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) return kvm_riscv_vcpu_set_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_VECTOR) + return kvm_riscv_vcpu_set_reg_vector(vcpu, reg, + KVM_REG_RISCV_VECTOR); =20 return -EINVAL; } @@ -404,6 +422,9 @@ static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu, else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_FP_D) return kvm_riscv_vcpu_get_reg_fp(vcpu, reg, KVM_REG_RISCV_FP_D); + else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) =3D=3D KVM_REG_RISCV_VECTOR) + return kvm_riscv_vcpu_get_reg_vector(vcpu, reg, + KVM_REG_RISCV_VECTOR); =20 return -EINVAL; } @@ -643,6 +664,9 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_riscv_vcpu_host_fp_save(&vcpu->arch.host_context); kvm_riscv_vcpu_guest_fp_restore(&vcpu->arch.guest_context, vcpu->arch.isa); + kvm_riscv_vcpu_host_vector_save(&vcpu->arch.host_context); + kvm_riscv_vcpu_guest_vector_restore(&vcpu->arch.guest_context, + vcpu->arch.isa); =20 vcpu->cpu =3D cpu; } @@ -657,6 +681,12 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) vcpu->arch.isa); kvm_riscv_vcpu_host_fp_restore(&vcpu->arch.host_context); =20 + kvm_riscv_vcpu_guest_vector_save(&vcpu->arch.guest_context, + vcpu->arch.isa); + kvm_riscv_vcpu_host_vector_restore(&vcpu->arch.host_context); + + csr_write(CSR_HGATP, 0); + csr->vsstatus =3D csr_read(CSR_VSSTATUS); csr->vsie =3D csr_read(CSR_VSIE); csr->vstvec =3D csr_read(CSR_VSTVEC); diff --git a/arch/riscv/kvm/vcpu_switch.S b/arch/riscv/kvm/vcpu_switch.S index d74df8eb4d71..730dc9b8c644 100644 --- a/arch/riscv/kvm/vcpu_switch.S +++ b/arch/riscv/kvm/vcpu_switch.S @@ -406,3 +406,72 @@ __kvm_riscv_fp_d_restore: csrw CSR_SSTATUS, t2 ret #endif + +#ifdef CONFIG_VECTOR + +#define vstatep a0 +#define datap a1 +#define x_vstart t0 +#define x_vtype t1 +#define x_vl t2 +#define x_vcsr t3 +#define incr t4 +#define status t5 + +ENTRY(__kvm_riscv_vector_save) + li status, SR_VS + csrs CSR_STATUS, status + + li a2, KVM_ARCH_VECTOR_DATAP + add datap, a0, a2 + ld datap, (datap) + csrr x_vstart, CSR_VSTART + csrr x_vtype, CSR_VTYPE + csrr x_vl, CSR_VL + csrr x_vcsr, CSR_VCSR + vsetvli incr, x0, e8, m8, ta, ma + vse8.v v0, (datap) + add datap, datap, incr + vse8.v v8, (datap) + add datap, datap, incr + vse8.v v16, (datap) + add datap, datap, incr + vse8.v v24, (datap) + + REG_S x_vstart, KVM_ARCH_VECTOR_VSTART(vstatep) + REG_S x_vtype, KVM_ARCH_VECTOR_VTYPE(vstatep) + REG_S x_vl, KVM_ARCH_VECTOR_VL(vstatep) + REG_S x_vcsr, KVM_ARCH_VECTOR_VCSR(vstatep) + + csrc CSR_STATUS, status + ret +ENDPROC(__kvm_riscv_vector_save) + +ENTRY(__kvm_riscv_vector_restore) + li status, SR_VS + csrs CSR_STATUS, status + + li a2, KVM_ARCH_VECTOR_DATAP + add datap, a0, a2 + ld datap, (datap) + vsetvli incr, x0, e8, m8, ta, ma + vle8.v v0, (datap) + add datap, datap, incr + vle8.v v8, (datap) + add datap, datap, incr + vle8.v v16, (datap) + add datap, datap, incr + vle8.v v24, (datap) + + REG_L x_vstart, KVM_ARCH_VECTOR_VSTART(vstatep) + REG_L x_vtype, KVM_ARCH_VECTOR_VTYPE(vstatep) + REG_L x_vl, KVM_ARCH_VECTOR_VL(vstatep) + REG_L x_vcsr, KVM_ARCH_VECTOR_VCSR(vstatep) + vsetvl x0, x_vl, x_vtype + csrw CSR_VSTART, x_vstart + csrw CSR_VCSR, x_vcsr + + csrc CSR_STATUS, status + ret +ENDPROC(__kvm_riscv_vector_restore) +#endif diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c new file mode 100644 index 000000000000..37bf4ffd47dd --- /dev/null +++ b/arch/riscv/kvm/vcpu_vector.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Western Digital Corporation or its affiliates. + * Copyright (C) 2022 SiFive + * + * Authors: + * Atish Patra + * Anup Patel + * Vincent Chen + * Greentime Hu + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_VECTOR +extern unsigned long riscv_vsize; +void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) +{ + unsigned long isa =3D vcpu->arch.isa; + struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; + + cntx->sstatus &=3D ~SR_VS; + if (riscv_isa_extension_available(&isa, v)) + cntx->sstatus |=3D SR_VS_INITIAL; + else + cntx->sstatus |=3D SR_VS_OFF; + + memset(cntx->vector.datap, 0, riscv_vsize); +} + +static void kvm_riscv_vcpu_vector_clean(struct kvm_cpu_context *cntx) +{ + cntx->sstatus &=3D ~SR_VS; + cntx->sstatus |=3D SR_VS_CLEAN; +} + +void kvm_riscv_vcpu_guest_vector_save(struct kvm_cpu_context *cntx, + unsigned long isa) +{ + if ((cntx->sstatus & SR_VS) =3D=3D SR_VS_DIRTY) { + if (riscv_isa_extension_available(&isa, v)) + __kvm_riscv_vector_save(cntx); + kvm_riscv_vcpu_vector_clean(cntx); + } +} + +void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_context *cntx, + unsigned long isa) +{ + if ((cntx->sstatus & SR_VS) !=3D SR_VS_OFF) { + if (riscv_isa_extension_available(&isa, v)) + __kvm_riscv_vector_restore(cntx); + kvm_riscv_vcpu_vector_clean(cntx); + } +} + +void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx) +{ + /* No need to check host sstatus as it can be modified outside */ + __kvm_riscv_vector_save(cntx); +} + +void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx) +{ + __kvm_riscv_vector_restore(cntx); +} + +void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu) +{ + kfree(vcpu->arch.guest_reset_context.vector.datap); + kfree(vcpu->arch.host_context.vector.datap); +} +#else +#define riscv_vsize (0) +#endif + +static void *kvm_riscv_vcpu_vreg_addr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + size_t reg_size) +{ + struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; + void *reg_val; + size_t vlenb =3D riscv_vsize / 32; + + if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { + if (reg_size !=3D sizeof(unsigned long)) + return NULL; + switch (reg_num) { + case KVM_REG_RISCV_VECTOR_CSR_REG(vstart): + reg_val =3D &cntx->vector.vstart; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vl): + reg_val =3D &cntx->vector.vl; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vtype): + reg_val =3D &cntx->vector.vtype; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr): + reg_val =3D &cntx->vector.vcsr; + break; + case KVM_REG_RISCV_VECTOR_CSR_REG(datap): + default: + return NULL; + } + } else if (reg_num <=3D KVM_REG_RISCV_VECTOR_REG(31)) { + if (reg_size !=3D vlenb) + return NULL; + reg_val =3D cntx->vector.datap + + (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; + } else { + return NULL; + } + + return reg_val; +} + +int kvm_riscv_vcpu_get_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + unsigned long isa =3D vcpu->arch.isa; + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val; + size_t reg_size =3D KVM_REG_SIZE(reg->id); + + if ((rtype =3D=3D KVM_REG_RISCV_VECTOR) && + riscv_isa_extension_available(&isa, v)) { + reg_val =3D kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); + } + + if (!reg_val) + return -EINVAL; + + if (copy_to_user(uaddr, reg_val, reg_size)) + return -EFAULT; + + return 0; +} + +int kvm_riscv_vcpu_set_reg_vector(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg, + unsigned long rtype) +{ + unsigned long isa =3D vcpu->arch.isa; + unsigned long __user *uaddr =3D + (unsigned long __user *)(unsigned long)reg->addr; + unsigned long reg_num =3D reg->id & ~(KVM_REG_ARCH_MASK | + KVM_REG_SIZE_MASK | + rtype); + void *reg_val =3D NULL; + size_t reg_size =3D KVM_REG_SIZE(reg->id); + + if ((rtype =3D=3D KVM_REG_RISCV_VECTOR) && + riscv_isa_extension_available(&isa, v)) { + reg_val =3D kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size); + } + + if (!reg_val) + return -EINVAL; + + if (copy_from_user(reg_val, uaddr, reg_size)) + return -EFAULT; + + return 0; +} --=20 2.17.1