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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:20 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Syed Nayyar Waris Subject: [PATCH 1/8] counter: 104-quad-8: Utilize iomap interface Date: Tue, 10 May 2022 13:30:53 -0400 Message-Id: <861c003318dce3d2bef4061711643bb04f5ec14f.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Cc: Syed Nayyar Waris Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/counter/104-quad-8.c | 169 ++++++++++++++++++----------------- 1 file changed, 89 insertions(+), 80 deletions(-) diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c index a17e51d65aca..43dde9abfdcf 100644 --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c @@ -63,7 +63,7 @@ struct quad8 { unsigned int synchronous_mode[QUAD8_NUM_COUNTERS]; unsigned int index_polarity[QUAD8_NUM_COUNTERS]; unsigned int cable_fault_enable; - unsigned int base; + void __iomem *base; }; =20 #define QUAD8_REG_INTERRUPT_STATUS 0x10 @@ -118,8 +118,8 @@ static int quad8_signal_read(struct counter_device *cou= nter, if (signal->id < 16) return -EINVAL; =20 - state =3D inb(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) - & BIT(signal->id - 16); + state =3D ioread8(priv->base + QUAD8_REG_INDEX_INPUT_LEVELS) & + BIT(signal->id - 16); =20 *level =3D (state) ? COUNTER_SIGNAL_LEVEL_HIGH : COUNTER_SIGNAL_LEVEL_LOW; =20 @@ -130,14 +130,14 @@ static int quad8_count_read(struct counter_device *co= unter, struct counter_count *count, u64 *val) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id; + void __iomem *const base_offset =3D priv->base + 2 * count->id; unsigned int flags; unsigned int borrow; unsigned int carry; unsigned long irqflags; int i; =20 - flags =3D inb(base_offset + 1); + flags =3D ioread8(base_offset + 1); borrow =3D flags & QUAD8_FLAG_BT; carry =3D !!(flags & QUAD8_FLAG_CT); =20 @@ -147,11 +147,11 @@ static int quad8_count_read(struct counter_device *co= unter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Reset Byte Pointer; transfer Counter to Output Latch */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, - base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, + base_offset + 1); =20 for (i =3D 0; i < 3; i++) - *val |=3D (unsigned long)inb(base_offset) << (8 * i); + *val |=3D (unsigned long)ioread8(base_offset) << (8 * i); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -162,7 +162,7 @@ static int quad8_count_write(struct counter_device *cou= nter, struct counter_count *count, u64 val) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id; + void __iomem *const base_offset =3D priv->base + 2 * count->id; unsigned long irqflags; int i; =20 @@ -173,27 +173,27 @@ static int quad8_count_write(struct counter_device *c= ounter, spin_lock_irqsave(&priv->lock, irqflags); =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Counter can only be set via Preset Register */ for (i =3D 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), base_offset); =20 /* Transfer Preset Register to Counter */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, base_offset + 1); =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Set Preset Register back to original value */ val =3D priv->preset[count->id]; for (i =3D 0; i < 3; i++) - outb(val >> (8 * i), base_offset); + iowrite8(val >> (8 * i), base_offset); =20 /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -246,7 +246,7 @@ static int quad8_function_write(struct counter_device *= counter, unsigned int *const quadrature_mode =3D priv->quadrature_mode + id; unsigned int *const scale =3D priv->quadrature_scale + id; unsigned int *const synchronous_mode =3D priv->synchronous_mode + id; - const int base_offset =3D priv->base + 2 * id + 1; + void __iomem *const base_offset =3D priv->base + 2 * id + 1; unsigned long irqflags; unsigned int mode_cfg; unsigned int idr_cfg; @@ -266,7 +266,7 @@ static int quad8_function_write(struct counter_device *= counter, if (*synchronous_mode) { *synchronous_mode =3D 0; /* Disable synchronous function mode */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); } } else { *quadrature_mode =3D 1; @@ -292,7 +292,7 @@ static int quad8_function_write(struct counter_device *= counter, } =20 /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -305,10 +305,10 @@ static int quad8_direction_read(struct counter_device= *counter, { const struct quad8 *const priv =3D counter_priv(counter); unsigned int ud_flag; - const unsigned int flag_addr =3D priv->base + 2 * count->id + 1; + void __iomem *const flag_addr =3D priv->base + 2 * count->id + 1; =20 /* U/D flag: nonzero =3D up, zero =3D down */ - ud_flag =3D inb(flag_addr) & QUAD8_FLAG_UD; + ud_flag =3D ioread8(flag_addr) & QUAD8_FLAG_UD; =20 *direction =3D (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : COUNTER_COUNT_DIRECTION_BACKWARD; @@ -402,7 +402,7 @@ static int quad8_events_configure(struct counter_device= *counter) struct counter_event_node *event_node; unsigned int next_irq_trigger; unsigned long ior_cfg; - unsigned long base_offset; + void __iomem *base_offset; =20 spin_lock_irqsave(&priv->lock, irqflags); =20 @@ -438,13 +438,13 @@ static int quad8_events_configure(struct counter_devi= ce *counter) priv->preset_enable[event_node->channel] << 1 | priv->irq_trigger[event_node->channel] << 3; base_offset =3D priv->base + 2 * event_node->channel + 1; - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); =20 /* Enable IRQ line */ irq_enabled |=3D BIT(event_node->channel); } =20 - outb(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(irq_enabled, priv->base + QUAD8_REG_INDEX_INTERRUPT); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -508,7 +508,7 @@ static int quad8_index_polarity_set(struct counter_devi= ce *counter, { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; - const int base_offset =3D priv->base + 2 * channel_id + 1; + void __iomem *const base_offset =3D priv->base + 2 * channel_id + 1; unsigned long irqflags; unsigned int idr_cfg =3D index_polarity << 1; =20 @@ -519,7 +519,7 @@ static int quad8_index_polarity_set(struct counter_devi= ce *counter, priv->index_polarity[channel_id] =3D index_polarity; =20 /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -549,7 +549,7 @@ static int quad8_synchronous_mode_set(struct counter_de= vice *counter, { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id - 16; - const int base_offset =3D priv->base + 2 * channel_id + 1; + void __iomem *const base_offset =3D priv->base + 2 * channel_id + 1; unsigned long irqflags; unsigned int idr_cfg =3D synchronous_mode; =20 @@ -566,7 +566,7 @@ static int quad8_synchronous_mode_set(struct counter_de= vice *counter, priv->synchronous_mode[channel_id] =3D synchronous_mode; =20 /* Load Index Control configuration to Index Control Register */ - outb(QUAD8_CTR_IDR | idr_cfg, base_offset); + iowrite8(QUAD8_CTR_IDR | idr_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -614,7 +614,7 @@ static int quad8_count_mode_write(struct counter_device= *counter, struct quad8 *const priv =3D counter_priv(counter); unsigned int count_mode; unsigned int mode_cfg; - const int base_offset =3D priv->base + 2 * count->id + 1; + void __iomem *const base_offset =3D priv->base + 2 * count->id + 1; unsigned long irqflags; =20 /* Map Generic Counter count mode to 104-QUAD-8 count mode */ @@ -648,7 +648,7 @@ static int quad8_count_mode_write(struct counter_device= *counter, mode_cfg |=3D (priv->quadrature_scale[count->id] + 1) << 3; =20 /* Load mode configuration to Counter Mode Register */ - outb(QUAD8_CTR_CMR | mode_cfg, base_offset); + iowrite8(QUAD8_CTR_CMR | mode_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -669,7 +669,7 @@ static int quad8_count_enable_write(struct counter_devi= ce *counter, struct counter_count *count, u8 enable) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id; + void __iomem *const base_offset =3D priv->base + 2 * count->id; unsigned long irqflags; unsigned int ior_cfg; =20 @@ -681,7 +681,7 @@ static int quad8_count_enable_write(struct counter_devi= ce *counter, priv->irq_trigger[count->id] << 3; =20 /* Load I/O control configuration */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset + 1); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -697,9 +697,9 @@ static int quad8_error_noise_get(struct counter_device = *counter, struct counter_count *count, u32 *noise_error) { const struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id + 1; + void __iomem *const base_offset =3D priv->base + 2 * count->id + 1; =20 - *noise_error =3D !!(inb(base_offset) & QUAD8_FLAG_E); + *noise_error =3D !!(ioread8(base_offset) & QUAD8_FLAG_E); =20 return 0; } @@ -717,17 +717,17 @@ static int quad8_count_preset_read(struct counter_dev= ice *counter, static void quad8_preset_register_set(struct quad8 *const priv, const int = id, const unsigned int preset) { - const unsigned int base_offset =3D priv->base + 2 * id; + void __iomem *const base_offset =3D priv->base + 2 * id; int i; =20 priv->preset[id] =3D preset; =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Set Preset Register */ for (i =3D 0; i < 3; i++) - outb(preset >> (8 * i), base_offset); + iowrite8(preset >> (8 * i), base_offset); } =20 static int quad8_count_preset_write(struct counter_device *counter, @@ -816,7 +816,7 @@ static int quad8_count_preset_enable_write(struct count= er_device *counter, u8 preset_enable) { struct quad8 *const priv =3D counter_priv(counter); - const int base_offset =3D priv->base + 2 * count->id + 1; + void __iomem *const base_offset =3D priv->base + 2 * count->id + 1; unsigned long irqflags; unsigned int ior_cfg; =20 @@ -831,7 +831,7 @@ static int quad8_count_preset_enable_write(struct count= er_device *counter, priv->irq_trigger[count->id] << 3; =20 /* Load I/O control configuration to Input / Output Control Register */ - outb(QUAD8_CTR_IOR | ior_cfg, base_offset); + iowrite8(QUAD8_CTR_IOR | ior_cfg, base_offset); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -858,7 +858,7 @@ static int quad8_signal_cable_fault_read(struct counter= _device *counter, } =20 /* Logic 0 =3D cable fault */ - status =3D inb(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + status =3D ioread8(priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -899,7 +899,8 @@ static int quad8_signal_cable_fault_enable_write(struct= counter_device *counter, /* Enable is active low in Differential Encoder Cable Status register */ cable_fault_enable =3D ~priv->cable_fault_enable; =20 - outb(cable_fault_enable, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(cable_fault_enable, + priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -923,7 +924,7 @@ static int quad8_signal_fck_prescaler_write(struct coun= ter_device *counter, { struct quad8 *const priv =3D counter_priv(counter); const size_t channel_id =3D signal->id / 2; - const int base_offset =3D priv->base + 2 * channel_id; + void __iomem *const base_offset =3D priv->base + 2 * channel_id; unsigned long irqflags; =20 spin_lock_irqsave(&priv->lock, irqflags); @@ -931,12 +932,12 @@ static int quad8_signal_fck_prescaler_write(struct co= unter_device *counter, priv->fck_prescaler[channel_id] =3D prescaler; =20 /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); =20 /* Set filter clock factor */ - outb(prescaler, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); + iowrite8(prescaler, base_offset); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + base_offset + 1); =20 spin_unlock_irqrestore(&priv->lock, irqflags); =20 @@ -1084,12 +1085,12 @@ static irqreturn_t quad8_irq_handler(int irq, void = *private) { struct counter_device *counter =3D private; struct quad8 *const priv =3D counter_priv(counter); - const unsigned long base =3D priv->base; + void __iomem *const base =3D priv->base; unsigned long irq_status; unsigned long channel; u8 event; =20 - irq_status =3D inb(base + QUAD8_REG_INTERRUPT_STATUS); + irq_status =3D ioread8(base + QUAD8_REG_INTERRUPT_STATUS); if (!irq_status) return IRQ_NONE; =20 @@ -1118,17 +1119,43 @@ static irqreturn_t quad8_irq_handler(int irq, void = *private) } =20 /* Clear pending interrupts on device */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base + QUAD8_REG_CHAN_OP); =20 return IRQ_HANDLED; } =20 +static void quad8_init_counter(void __iomem *const base_offset) +{ + unsigned long i; + + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + /* Reset filter clock factor */ + iowrite8(0, base_offset); + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, + base_offset + 1); + /* Reset Byte Pointer */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); + /* Reset Preset Register */ + for (i =3D 0; i < 3; i++) + iowrite8(0x00, base_offset); + /* Reset Borrow, Carry, Compare, and Sign flags */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); + /* Reset Error flag */ + iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); + /* Binary encoding; Normal count; non-quadrature mode */ + iowrite8(QUAD8_CTR_CMR, base_offset + 1); + /* Disable A and B inputs; preset on index; FLG1 as Carry */ + iowrite8(QUAD8_CTR_IOR, base_offset + 1); + /* Disable index function; negative index polarity */ + iowrite8(QUAD8_CTR_IDR, base_offset + 1); +} + static int quad8_probe(struct device *dev, unsigned int id) { struct counter_device *counter; struct quad8 *priv; - int i, j; - unsigned int base_offset; + unsigned long i; int err; =20 if (!devm_request_region(dev, base[id], QUAD8_EXTENT, dev_name(dev))) { @@ -1142,6 +1169,10 @@ static int quad8_probe(struct device *dev, unsigned = int id) return -ENOMEM; priv =3D counter_priv(counter); =20 + priv->base =3D devm_ioport_map(dev, base[id], QUAD8_EXTENT); + if (!priv->base) + return -ENOMEM; + /* Initialize Counter device and driver data */ counter->name =3D dev_name(dev); counter->parent =3D dev; @@ -1150,43 +1181,21 @@ static int quad8_probe(struct device *dev, unsigned= int id) counter->num_counts =3D ARRAY_SIZE(quad8_counts); counter->signals =3D quad8_signals; counter->num_signals =3D ARRAY_SIZE(quad8_signals); - priv->base =3D base[id]; =20 spin_lock_init(&priv->lock); =20 /* Reset Index/Interrupt Register */ - outb(0x00, base[id] + QUAD8_REG_INDEX_INTERRUPT); + iowrite8(0x00, priv->base + QUAD8_REG_INDEX_INTERRUPT); /* Reset all counters and disable interrupt function */ - outb(QUAD8_CHAN_OP_RESET_COUNTERS, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, priv->base + QUAD8_REG_CHAN_OP); /* Set initial configuration for all counters */ - for (i =3D 0; i < QUAD8_NUM_COUNTERS; i++) { - base_offset =3D base[id] + 2 * i; - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset filter clock factor */ - outb(0, base_offset); - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, - base_offset + 1); - /* Reset Byte Pointer */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, base_offset + 1); - /* Reset Preset Register */ - for (j =3D 0; j < 3; j++) - outb(0x00, base_offset); - /* Reset Borrow, Carry, Compare, and Sign flags */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, base_offset + 1); - /* Reset Error flag */ - outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, base_offset + 1); - /* Binary encoding; Normal count; non-quadrature mode */ - outb(QUAD8_CTR_CMR, base_offset + 1); - /* Disable A and B inputs; preset on index; FLG1 as Carry */ - outb(QUAD8_CTR_IOR, base_offset + 1); - /* Disable index function; negative index polarity */ - outb(QUAD8_CTR_IDR, base_offset + 1); - } + for (i =3D 0; i < QUAD8_NUM_COUNTERS; i++) + quad8_init_counter(priv->base + 2 * i); /* Disable Differential Encoder Cable Status for all channels */ - outb(0xFF, base[id] + QUAD8_DIFF_ENCODER_CABLE_STATUS); + iowrite8(0xFF, priv->base + QUAD8_DIFF_ENCODER_CABLE_STATUS); /* Enable all counters and enable interrupt function */ - outb(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, base[id] + QUAD8_REG_CHAN_OP); + iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, + priv->base + QUAD8_REG_CHAN_OP); =20 err =3D devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, IRQF_SHARED, counter->name, counter); --=20 2.35.3 From nobody Sun May 10 09:53:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18D9CC433FE for ; Tue, 10 May 2022 17:34:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348643AbiEJRhP (ORCPT ); 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:21 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 2/8] gpio: 104-dio-48e: Utilize iomap interface Date: Tue, 10 May 2022 13:30:54 -0400 Message-Id: <8bc6e7d2fef9f0c320580dd8266eb27da2670feb.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/gpio/gpio-104-dio-48e.c | 63 +++++++++++++++++---------------- 1 file changed, 33 insertions(+), 30 deletions(-) diff --git a/drivers/gpio/gpio-104-dio-48e.c b/drivers/gpio/gpio-104-dio-48= e.c index 6bf41040c41f..f118ad9bcd33 100644 --- a/drivers/gpio/gpio-104-dio-48e.c +++ b/drivers/gpio/gpio-104-dio-48e.c @@ -49,7 +49,7 @@ struct dio48e_gpio { unsigned char out_state[6]; unsigned char control[2]; raw_spinlock_t lock; - unsigned int base; + void __iomem *base; unsigned char irq_mask; }; =20 @@ -70,7 +70,7 @@ static int dio48e_gpio_direction_input(struct gpio_chip *= chip, unsigned int offs struct dio48e_gpio *const dio48egpio =3D gpiochip_get_data(chip); const unsigned int io_port =3D offset / 8; const unsigned int control_port =3D io_port / 3; - const unsigned int control_addr =3D dio48egpio->base + 3 + control_port *= 4; + void __iomem *const control_addr =3D dio48egpio->base + 3 + control_port = * 4; unsigned long flags; unsigned int control; =20 @@ -95,9 +95,9 @@ static int dio48e_gpio_direction_input(struct gpio_chip *= chip, unsigned int offs } =20 control =3D BIT(7) | dio48egpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, control_addr); control &=3D ~BIT(7); - outb(control, control_addr); + iowrite8(control, control_addr); =20 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); =20 @@ -111,7 +111,7 @@ static int dio48e_gpio_direction_output(struct gpio_chi= p *chip, unsigned int off const unsigned int io_port =3D offset / 8; const unsigned int control_port =3D io_port / 3; const unsigned int mask =3D BIT(offset % 8); - const unsigned int control_addr =3D dio48egpio->base + 3 + control_port *= 4; + void __iomem *const control_addr =3D dio48egpio->base + 3 + control_port = * 4; const unsigned int out_port =3D (io_port > 2) ? io_port + 1 : io_port; unsigned long flags; unsigned int control; @@ -142,12 +142,12 @@ static int dio48e_gpio_direction_output(struct gpio_c= hip *chip, unsigned int off dio48egpio->out_state[io_port] &=3D ~mask; =20 control =3D BIT(7) | dio48egpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, control_addr); =20 - outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port); + iowrite8(dio48egpio->out_state[io_port], dio48egpio->base + out_port); =20 control &=3D ~BIT(7); - outb(control, control_addr); + iowrite8(control, control_addr); =20 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); =20 @@ -171,7 +171,7 @@ static int dio48e_gpio_get(struct gpio_chip *chip, unsi= gned int offset) return -EINVAL; } =20 - port_state =3D inb(dio48egpio->base + in_port); + port_state =3D ioread8(dio48egpio->base + in_port); =20 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); =20 @@ -186,7 +186,7 @@ static int dio48e_gpio_get_multiple(struct gpio_chip *c= hip, unsigned long *mask, struct dio48e_gpio *const dio48egpio =3D gpiochip_get_data(chip); unsigned long offset; unsigned long gpio_mask; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; =20 /* clear bits array to a clean slate */ @@ -194,7 +194,7 @@ static int dio48e_gpio_get_multiple(struct gpio_chip *c= hip, unsigned long *mask, =20 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { port_addr =3D dio48egpio->base + ports[offset / 8]; - port_state =3D inb(port_addr) & gpio_mask; + port_state =3D ioread8(port_addr) & gpio_mask; =20 bitmap_set_value8(bits, port_state, offset); } @@ -217,7 +217,7 @@ static void dio48e_gpio_set(struct gpio_chip *chip, uns= igned int offset, int val else dio48egpio->out_state[port] &=3D ~mask; =20 - outb(dio48egpio->out_state[port], dio48egpio->base + out_port); + iowrite8(dio48egpio->out_state[port], dio48egpio->base + out_port); =20 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); } @@ -229,7 +229,7 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *= chip, unsigned long offset; unsigned long gpio_mask; size_t index; - unsigned int port_addr; + void __iomem *port_addr; unsigned long bitmask; unsigned long flags; =20 @@ -244,7 +244,7 @@ static void dio48e_gpio_set_multiple(struct gpio_chip *= chip, /* update output state data and set device gpio register */ dio48egpio->out_state[index] &=3D ~gpio_mask; dio48egpio->out_state[index] |=3D bitmask; - outb(dio48egpio->out_state[index], port_addr); + iowrite8(dio48egpio->out_state[index], port_addr); =20 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); } @@ -274,7 +274,7 @@ static void dio48e_irq_mask(struct irq_data *data) =20 if (!dio48egpio->irq_mask) /* disable interrupts */ - inb(dio48egpio->base + 0xB); + ioread8(dio48egpio->base + 0xB); =20 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags); } @@ -294,8 +294,8 @@ static void dio48e_irq_unmask(struct irq_data *data) =20 if (!dio48egpio->irq_mask) { /* enable interrupts */ - outb(0x00, dio48egpio->base + 0xF); - outb(0x00, dio48egpio->base + 0xB); + iowrite8(0x00, dio48egpio->base + 0xF); + iowrite8(0x00, dio48egpio->base + 0xB); } =20 if (offset =3D=3D 19) @@ -341,7 +341,7 @@ static irqreturn_t dio48e_irq_handler(int irq, void *de= v_id) =20 raw_spin_lock(&dio48egpio->lock); =20 - outb(0x00, dio48egpio->base + 0xF); + iowrite8(0x00, dio48egpio->base + 0xF); =20 raw_spin_unlock(&dio48egpio->lock); =20 @@ -373,7 +373,7 @@ static int dio48e_irq_init_hw(struct gpio_chip *gc) struct dio48e_gpio *const dio48egpio =3D gpiochip_get_data(gc); =20 /* Disable IRQ by default */ - inb(dio48egpio->base + 0xB); + ioread8(dio48egpio->base + 0xB); =20 return 0; } @@ -395,6 +395,10 @@ static int dio48e_probe(struct device *dev, unsigned i= nt id) return -EBUSY; } =20 + dio48egpio->base =3D devm_ioport_map(dev, base[id], DIO48E_EXTENT); + if (!dio48egpio->base) + return -ENOMEM; + dio48egpio->chip.label =3D name; dio48egpio->chip.parent =3D dev; dio48egpio->chip.owner =3D THIS_MODULE; @@ -408,7 +412,6 @@ static int dio48e_probe(struct device *dev, unsigned in= t id) dio48egpio->chip.get_multiple =3D dio48e_gpio_get_multiple; dio48egpio->chip.set =3D dio48e_gpio_set; dio48egpio->chip.set_multiple =3D dio48e_gpio_set_multiple; - dio48egpio->base =3D base[id]; =20 girq =3D &dio48egpio->chip.irq; girq->chip =3D &dio48e_irqchip; @@ -423,16 +426,16 @@ static int dio48e_probe(struct device *dev, unsigned = int id) raw_spin_lock_init(&dio48egpio->lock); =20 /* initialize all GPIO as output */ - outb(0x80, base[id] + 3); - outb(0x00, base[id]); - outb(0x00, base[id] + 1); - outb(0x00, base[id] + 2); - outb(0x00, base[id] + 3); - outb(0x80, base[id] + 7); - outb(0x00, base[id] + 4); - outb(0x00, base[id] + 5); - outb(0x00, base[id] + 6); - outb(0x00, base[id] + 7); + iowrite8(0x80, dio48egpio->base + 3); + iowrite8(0x00, dio48egpio->base); + iowrite8(0x00, dio48egpio->base + 1); + iowrite8(0x00, dio48egpio->base + 2); + iowrite8(0x00, dio48egpio->base + 3); + iowrite8(0x80, dio48egpio->base + 7); + iowrite8(0x00, dio48egpio->base + 4); + iowrite8(0x00, dio48egpio->base + 5); + iowrite8(0x00, dio48egpio->base + 6); + iowrite8(0x00, dio48egpio->base + 7); =20 err =3D devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio); if (err) { --=20 2.35.3 From nobody Sun May 10 09:53:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9F39C433EF for ; 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:22 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 3/8] gpio: 104-idi-48: Utilize iomap interface Date: Tue, 10 May 2022 13:30:55 -0400 Message-Id: <09e2418d2dcf93c45a70c3a0a1fe7fdd8104a689.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/gpio/gpio-104-idi-48.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-104-idi-48.c b/drivers/gpio/gpio-104-idi-48.c index 34be7dd9f5b9..9521ece3ebef 100644 --- a/drivers/gpio/gpio-104-idi-48.c +++ b/drivers/gpio/gpio-104-idi-48.c @@ -47,7 +47,7 @@ struct idi_48_gpio { raw_spinlock_t lock; spinlock_t ack_lock; unsigned char irq_mask[6]; - unsigned base; + void __iomem *base; unsigned char cos_enb; }; =20 @@ -66,15 +66,15 @@ static int idi_48_gpio_get(struct gpio_chip *chip, unsi= gned offset) struct idi_48_gpio *const idi48gpio =3D gpiochip_get_data(chip); unsigned i; static const unsigned int register_offset[6] =3D { 0, 1, 2, 4, 5, 6 }; - unsigned base_offset; + void __iomem *port_addr; unsigned mask; =20 for (i =3D 0; i < 48; i +=3D 8) if (offset < i + 8) { - base_offset =3D register_offset[i / 8]; + port_addr =3D idi48gpio->base + register_offset[i / 8]; mask =3D BIT(offset - i); =20 - return !!(inb(idi48gpio->base + base_offset) & mask); + return !!(ioread8(port_addr) & mask); } =20 /* The following line should never execute since offset < 48 */ @@ -88,7 +88,7 @@ static int idi_48_gpio_get_multiple(struct gpio_chip *chi= p, unsigned long *mask, unsigned long offset; unsigned long gpio_mask; static const size_t ports[] =3D { 0, 1, 2, 4, 5, 6 }; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; =20 /* clear bits array to a clean slate */ @@ -96,7 +96,7 @@ static int idi_48_gpio_get_multiple(struct gpio_chip *chi= p, unsigned long *mask, =20 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { port_addr =3D idi48gpio->base + ports[offset / 8]; - port_state =3D inb(port_addr) & gpio_mask; + port_state =3D ioread8(port_addr) & gpio_mask; =20 bitmap_set_value8(bits, port_state, offset); } @@ -130,7 +130,7 @@ static void idi_48_irq_mask(struct irq_data *data) =20 raw_spin_lock_irqsave(&idi48gpio->lock, flags); =20 - outb(idi48gpio->cos_enb, idi48gpio->base + 7); + iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7); =20 raw_spin_unlock_irqrestore(&idi48gpio->lock, flags); } @@ -163,7 +163,7 @@ static void idi_48_irq_unmask(struct irq_data *data) =20 raw_spin_lock_irqsave(&idi48gpio->lock, flags); =20 - outb(idi48gpio->cos_enb, idi48gpio->base + 7); + iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7); =20 raw_spin_unlock_irqrestore(&idi48gpio->lock, flags); } @@ -204,7 +204,7 @@ static irqreturn_t idi_48_irq_handler(int irq, void *de= v_id) =20 raw_spin_lock(&idi48gpio->lock); =20 - cos_status =3D inb(idi48gpio->base + 7); + cos_status =3D ioread8(idi48gpio->base + 7); =20 raw_spin_unlock(&idi48gpio->lock); =20 @@ -250,8 +250,8 @@ static int idi_48_irq_init_hw(struct gpio_chip *gc) struct idi_48_gpio *const idi48gpio =3D gpiochip_get_data(gc); =20 /* Disable IRQ by default */ - outb(0, idi48gpio->base + 7); - inb(idi48gpio->base + 7); + iowrite8(0, idi48gpio->base + 7); + ioread8(idi48gpio->base + 7); =20 return 0; } @@ -273,6 +273,10 @@ static int idi_48_probe(struct device *dev, unsigned i= nt id) return -EBUSY; } =20 + idi48gpio->base =3D devm_ioport_map(dev, base[id], IDI_48_EXTENT); + if (!idi48gpio->base) + return -ENOMEM; + idi48gpio->chip.label =3D name; idi48gpio->chip.parent =3D dev; idi48gpio->chip.owner =3D THIS_MODULE; @@ -283,7 +287,6 @@ static int idi_48_probe(struct device *dev, unsigned in= t id) idi48gpio->chip.direction_input =3D idi_48_gpio_direction_input; idi48gpio->chip.get =3D idi_48_gpio_get; idi48gpio->chip.get_multiple =3D idi_48_gpio_get_multiple; - idi48gpio->base =3D base[id]; =20 girq =3D &idi48gpio->chip.irq; girq->chip =3D &idi_48_irqchip; --=20 2.35.3 From nobody Sun May 10 09:53:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09381C4332F for ; Tue, 10 May 2022 17:34:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348629AbiEJRhM (ORCPT ); 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:22 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 4/8] gpio: 104-idio-16: Utilize iomap interface Date: Tue, 10 May 2022 13:30:56 -0400 Message-Id: <1aed489e67526819d9f5c5a11f4bb3a172acd1f1.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/gpio/gpio-104-idio-16.c | 33 ++++++++++++++++++--------------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpio/gpio-104-idio-16.c b/drivers/gpio/gpio-104-idio-1= 6.c index c68ed1a135fa..45f7ad8573e1 100644 --- a/drivers/gpio/gpio-104-idio-16.c +++ b/drivers/gpio/gpio-104-idio-16.c @@ -44,7 +44,7 @@ struct idio_16_gpio { struct gpio_chip chip; raw_spinlock_t lock; unsigned long irq_mask; - unsigned int base; + void __iomem *base; unsigned int out_state; }; =20 @@ -79,9 +79,9 @@ static int idio_16_gpio_get(struct gpio_chip *chip, unsig= ned int offset) return -EINVAL; =20 if (offset < 24) - return !!(inb(idio16gpio->base + 1) & mask); + return !!(ioread8(idio16gpio->base + 1) & mask); =20 - return !!(inb(idio16gpio->base + 5) & (mask>>8)); + return !!(ioread8(idio16gpio->base + 5) & (mask>>8)); } =20 static int idio_16_gpio_get_multiple(struct gpio_chip *chip, @@ -91,9 +91,9 @@ static int idio_16_gpio_get_multiple(struct gpio_chip *ch= ip, =20 *bits =3D 0; if (*mask & GENMASK(23, 16)) - *bits |=3D (unsigned long)inb(idio16gpio->base + 1) << 16; + *bits |=3D (unsigned long)ioread8(idio16gpio->base + 1) << 16; if (*mask & GENMASK(31, 24)) - *bits |=3D (unsigned long)inb(idio16gpio->base + 5) << 24; + *bits |=3D (unsigned long)ioread8(idio16gpio->base + 5) << 24; =20 return 0; } @@ -116,9 +116,9 @@ static void idio_16_gpio_set(struct gpio_chip *chip, un= signed int offset, idio16gpio->out_state &=3D ~mask; =20 if (offset > 7) - outb(idio16gpio->out_state >> 8, idio16gpio->base + 4); + iowrite8(idio16gpio->out_state >> 8, idio16gpio->base + 4); else - outb(idio16gpio->out_state, idio16gpio->base); + iowrite8(idio16gpio->out_state, idio16gpio->base); =20 raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -135,9 +135,9 @@ static void idio_16_gpio_set_multiple(struct gpio_chip = *chip, idio16gpio->out_state |=3D *mask & *bits; =20 if (*mask & 0xFF) - outb(idio16gpio->out_state, idio16gpio->base); + iowrite8(idio16gpio->out_state, idio16gpio->base); if ((*mask >> 8) & 0xFF) - outb(idio16gpio->out_state >> 8, idio16gpio->base + 4); + iowrite8(idio16gpio->out_state >> 8, idio16gpio->base + 4); =20 raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -158,7 +158,7 @@ static void idio_16_irq_mask(struct irq_data *data) if (!idio16gpio->irq_mask) { raw_spin_lock_irqsave(&idio16gpio->lock, flags); =20 - outb(0, idio16gpio->base + 2); + iowrite8(0, idio16gpio->base + 2); =20 raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -177,7 +177,7 @@ static void idio_16_irq_unmask(struct irq_data *data) if (!prev_irq_mask) { raw_spin_lock_irqsave(&idio16gpio->lock, flags); =20 - inb(idio16gpio->base + 2); + ioread8(idio16gpio->base + 2); =20 raw_spin_unlock_irqrestore(&idio16gpio->lock, flags); } @@ -212,7 +212,7 @@ static irqreturn_t idio_16_irq_handler(int irq, void *d= ev_id) =20 raw_spin_lock(&idio16gpio->lock); =20 - outb(0, idio16gpio->base + 1); + iowrite8(0, idio16gpio->base + 1); =20 raw_spin_unlock(&idio16gpio->lock); =20 @@ -232,8 +232,8 @@ static int idio_16_irq_init_hw(struct gpio_chip *gc) struct idio_16_gpio *const idio16gpio =3D gpiochip_get_data(gc); =20 /* Disable IRQ by default */ - outb(0, idio16gpio->base + 2); - outb(0, idio16gpio->base + 1); + iowrite8(0, idio16gpio->base + 2); + iowrite8(0, idio16gpio->base + 1); =20 return 0; } @@ -255,6 +255,10 @@ static int idio_16_probe(struct device *dev, unsigned = int id) return -EBUSY; } =20 + idio16gpio->base =3D devm_ioport_map(dev, base[id], IDIO_16_EXTENT); + if (!idio16gpio->base) + return -ENOMEM; + idio16gpio->chip.label =3D name; idio16gpio->chip.parent =3D dev; idio16gpio->chip.owner =3D THIS_MODULE; @@ -268,7 +272,6 @@ static int idio_16_probe(struct device *dev, unsigned i= nt id) idio16gpio->chip.get_multiple =3D idio_16_gpio_get_multiple; idio16gpio->chip.set =3D idio_16_gpio_set; idio16gpio->chip.set_multiple =3D idio_16_gpio_set_multiple; - idio16gpio->base =3D base[id]; idio16gpio->out_state =3D 0xFFFF; =20 girq =3D &idio16gpio->chip.irq; --=20 2.35.3 From nobody Sun May 10 09:53:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D548AC433F5 for ; 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:23 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 5/8] gpio: gpio-mm: Utilize iomap interface Date: Tue, 10 May 2022 13:30:57 -0400 Message-Id: <1b274435871047e85fc8bbbf15840424632c47d0.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/gpio/gpio-gpio-mm.c | 43 +++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/gpio-gpio-mm.c b/drivers/gpio/gpio-gpio-mm.c index b89b8c5ff1f5..097a06463d01 100644 --- a/drivers/gpio/gpio-gpio-mm.c +++ b/drivers/gpio/gpio-gpio-mm.c @@ -42,7 +42,7 @@ struct gpiomm_gpio { unsigned char out_state[6]; unsigned char control[2]; spinlock_t lock; - unsigned int base; + void __iomem *base; }; =20 static int gpiomm_gpio_get_direction(struct gpio_chip *chip, @@ -64,7 +64,6 @@ static int gpiomm_gpio_direction_input(struct gpio_chip *= chip, struct gpiomm_gpio *const gpiommgpio =3D gpiochip_get_data(chip); const unsigned int io_port =3D offset / 8; const unsigned int control_port =3D io_port / 3; - const unsigned int control_addr =3D gpiommgpio->base + 3 + control_port*4; unsigned long flags; unsigned int control; =20 @@ -89,7 +88,7 @@ static int gpiomm_gpio_direction_input(struct gpio_chip *= chip, } =20 control =3D BIT(7) | gpiommgpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, gpiommgpio->base + 3 + control_port*4); =20 spin_unlock_irqrestore(&gpiommgpio->lock, flags); =20 @@ -103,7 +102,6 @@ static int gpiomm_gpio_direction_output(struct gpio_chi= p *chip, const unsigned int io_port =3D offset / 8; const unsigned int control_port =3D io_port / 3; const unsigned int mask =3D BIT(offset % 8); - const unsigned int control_addr =3D gpiommgpio->base + 3 + control_port*4; const unsigned int out_port =3D (io_port > 2) ? io_port + 1 : io_port; unsigned long flags; unsigned int control; @@ -134,9 +132,9 @@ static int gpiomm_gpio_direction_output(struct gpio_chi= p *chip, gpiommgpio->out_state[io_port] &=3D ~mask; =20 control =3D BIT(7) | gpiommgpio->control[control_port]; - outb(control, control_addr); + iowrite8(control, gpiommgpio->base + 3 + control_port*4); =20 - outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port); + iowrite8(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port); =20 spin_unlock_irqrestore(&gpiommgpio->lock, flags); =20 @@ -160,7 +158,7 @@ static int gpiomm_gpio_get(struct gpio_chip *chip, unsi= gned int offset) return -EINVAL; } =20 - port_state =3D inb(gpiommgpio->base + in_port); + port_state =3D ioread8(gpiommgpio->base + in_port); =20 spin_unlock_irqrestore(&gpiommgpio->lock, flags); =20 @@ -175,7 +173,7 @@ static int gpiomm_gpio_get_multiple(struct gpio_chip *c= hip, unsigned long *mask, struct gpiomm_gpio *const gpiommgpio =3D gpiochip_get_data(chip); unsigned long offset; unsigned long gpio_mask; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; =20 /* clear bits array to a clean slate */ @@ -183,7 +181,7 @@ static int gpiomm_gpio_get_multiple(struct gpio_chip *c= hip, unsigned long *mask, =20 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) { port_addr =3D gpiommgpio->base + ports[offset / 8]; - port_state =3D inb(port_addr) & gpio_mask; + port_state =3D ioread8(port_addr) & gpio_mask; =20 bitmap_set_value8(bits, port_state, offset); } @@ -207,7 +205,7 @@ static void gpiomm_gpio_set(struct gpio_chip *chip, uns= igned int offset, else gpiommgpio->out_state[port] &=3D ~mask; =20 - outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port); + iowrite8(gpiommgpio->out_state[port], gpiommgpio->base + out_port); =20 spin_unlock_irqrestore(&gpiommgpio->lock, flags); } @@ -219,7 +217,7 @@ static void gpiomm_gpio_set_multiple(struct gpio_chip *= chip, unsigned long offset; unsigned long gpio_mask; size_t index; - unsigned int port_addr; + void __iomem *port_addr; unsigned long bitmask; unsigned long flags; =20 @@ -234,7 +232,7 @@ static void gpiomm_gpio_set_multiple(struct gpio_chip *= chip, /* update output state data and set device gpio register */ gpiommgpio->out_state[index] &=3D ~gpio_mask; gpiommgpio->out_state[index] |=3D bitmask; - outb(gpiommgpio->out_state[index], port_addr); + iowrite8(gpiommgpio->out_state[index], port_addr); =20 spin_unlock_irqrestore(&gpiommgpio->lock, flags); } @@ -268,6 +266,10 @@ static int gpiomm_probe(struct device *dev, unsigned i= nt id) return -EBUSY; } =20 + gpiommgpio->base =3D devm_ioport_map(dev, base[id], GPIOMM_EXTENT); + if (!gpiommgpio->base) + return -ENOMEM; + gpiommgpio->chip.label =3D name; gpiommgpio->chip.parent =3D dev; gpiommgpio->chip.owner =3D THIS_MODULE; @@ -281,7 +283,6 @@ static int gpiomm_probe(struct device *dev, unsigned in= t id) gpiommgpio->chip.get_multiple =3D gpiomm_gpio_get_multiple; gpiommgpio->chip.set =3D gpiomm_gpio_set; gpiommgpio->chip.set_multiple =3D gpiomm_gpio_set_multiple; - gpiommgpio->base =3D base[id]; =20 spin_lock_init(&gpiommgpio->lock); =20 @@ -292,14 +293,14 @@ static int gpiomm_probe(struct device *dev, unsigned = int id) } =20 /* initialize all GPIO as output */ - outb(0x80, base[id] + 3); - outb(0x00, base[id]); - outb(0x00, base[id] + 1); - outb(0x00, base[id] + 2); - outb(0x80, base[id] + 7); - outb(0x00, base[id] + 4); - outb(0x00, base[id] + 5); - outb(0x00, base[id] + 6); + iowrite8(0x80, gpiommgpio->base + 3); + iowrite8(0x00, gpiommgpio->base); + iowrite8(0x00, gpiommgpio->base + 1); + iowrite8(0x00, gpiommgpio->base + 2); + iowrite8(0x80, gpiommgpio->base + 7); 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:24 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Bartosz Golaszewski Subject: [PATCH 6/8] gpio: ws16c48: Utilize iomap interface Date: Tue, 10 May 2022 13:30:58 -0400 Message-Id: <817800777df540e6d92b4b8aec832e68488a4eaf.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/gpio/gpio-ws16c48.c | 65 +++++++++++++++++++------------------ 1 file changed, 34 insertions(+), 31 deletions(-) diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c index bb02a82e22f4..5078631d8014 100644 --- a/drivers/gpio/gpio-ws16c48.c +++ b/drivers/gpio/gpio-ws16c48.c @@ -47,7 +47,7 @@ struct ws16c48_gpio { raw_spinlock_t lock; unsigned long irq_mask; unsigned long flow_mask; - unsigned base; + void __iomem *base; }; =20 static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned off= set) @@ -73,7 +73,7 @@ static int ws16c48_gpio_direction_input(struct gpio_chip = *chip, unsigned offset) =20 ws16c48gpio->io_state[port] |=3D mask; ws16c48gpio->out_state[port] &=3D ~mask; - outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); + iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); =20 @@ -95,7 +95,7 @@ static int ws16c48_gpio_direction_output(struct gpio_chip= *chip, ws16c48gpio->out_state[port] |=3D mask; else ws16c48gpio->out_state[port] &=3D ~mask; - outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); + iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); =20 @@ -118,7 +118,7 @@ static int ws16c48_gpio_get(struct gpio_chip *chip, uns= igned offset) return -EINVAL; } =20 - port_state =3D inb(ws16c48gpio->base + port); + port_state =3D ioread8(ws16c48gpio->base + port); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); =20 @@ -131,7 +131,7 @@ static int ws16c48_gpio_get_multiple(struct gpio_chip *= chip, struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(chip); unsigned long offset; unsigned long gpio_mask; - unsigned int port_addr; + void __iomem *port_addr; unsigned long port_state; =20 /* clear bits array to a clean slate */ @@ -139,7 +139,7 @@ static int ws16c48_gpio_get_multiple(struct gpio_chip *= chip, =20 for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { port_addr =3D ws16c48gpio->base + offset / 8; - port_state =3D inb(port_addr) & gpio_mask; + port_state =3D ioread8(port_addr) & gpio_mask; =20 bitmap_set_value8(bits, port_state, offset); } @@ -166,7 +166,7 @@ static void ws16c48_gpio_set(struct gpio_chip *chip, un= signed offset, int value) ws16c48gpio->out_state[port] |=3D mask; else ws16c48gpio->out_state[port] &=3D ~mask; - outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); + iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -178,7 +178,7 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip = *chip, unsigned long offset; unsigned long gpio_mask; size_t index; - unsigned int port_addr; + void __iomem *port_addr; unsigned long bitmask; unsigned long flags; =20 @@ -195,7 +195,7 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip = *chip, /* update output state data and set device gpio register */ ws16c48gpio->out_state[index] &=3D ~gpio_mask; ws16c48gpio->out_state[index] |=3D bitmask; - outb(ws16c48gpio->out_state[index], port_addr); + iowrite8(ws16c48gpio->out_state[index], port_addr); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -219,10 +219,10 @@ static void ws16c48_irq_ack(struct irq_data *data) =20 port_state =3D ws16c48gpio->irq_mask >> (8*port); =20 - outb(0x80, ws16c48gpio->base + 7); - outb(port_state & ~mask, ws16c48gpio->base + 8 + port); - outb(port_state | mask, ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(port_state & ~mask, ws16c48gpio->base + 8 + port); + iowrite8(port_state | mask, ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -244,9 +244,9 @@ static void ws16c48_irq_mask(struct irq_data *data) =20 ws16c48gpio->irq_mask &=3D ~mask; =20 - outb(0x80, ws16c48gpio->base + 7); - outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -268,9 +268,9 @@ static void ws16c48_irq_unmask(struct irq_data *data) =20 ws16c48gpio->irq_mask |=3D mask; =20 - outb(0x80, ws16c48gpio->base + 7); - outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); + iowrite8(0xC0, ws16c48gpio->base + 7); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } @@ -304,9 +304,9 @@ static int ws16c48_irq_set_type(struct irq_data *data, = unsigned flow_type) return -EINVAL; } =20 - outb(0x40, ws16c48gpio->base + 7); - outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x40, ws16c48gpio->base + 7); + iowrite8(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port= ); + iowrite8(0xC0, ws16c48gpio->base + 7); =20 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); =20 @@ -330,20 +330,20 @@ static irqreturn_t ws16c48_irq_handler(int irq, void = *dev_id) unsigned long int_id; unsigned long gpio; =20 - int_pending =3D inb(ws16c48gpio->base + 6) & 0x7; + int_pending =3D ioread8(ws16c48gpio->base + 6) & 0x7; if (!int_pending) return IRQ_NONE; =20 /* loop until all pending interrupts are handled */ do { for_each_set_bit(port, &int_pending, 3) { - int_id =3D inb(ws16c48gpio->base + 8 + port); + int_id =3D ioread8(ws16c48gpio->base + 8 + port); for_each_set_bit(gpio, &int_id, 8) generic_handle_domain_irq(chip->irq.domain, gpio + 8*port); } =20 - int_pending =3D inb(ws16c48gpio->base + 6) & 0x7; + int_pending =3D ioread8(ws16c48gpio->base + 6) & 0x7; } while (int_pending); =20 return IRQ_HANDLED; @@ -370,11 +370,11 @@ static int ws16c48_irq_init_hw(struct gpio_chip *gc) struct ws16c48_gpio *const ws16c48gpio =3D gpiochip_get_data(gc); =20 /* Disable IRQ by default */ - outb(0x80, ws16c48gpio->base + 7); - outb(0, ws16c48gpio->base + 8); - outb(0, ws16c48gpio->base + 9); - outb(0, ws16c48gpio->base + 10); - outb(0xC0, ws16c48gpio->base + 7); + iowrite8(0x80, ws16c48gpio->base + 7); + iowrite8(0, ws16c48gpio->base + 8); + iowrite8(0, ws16c48gpio->base + 9); + iowrite8(0, ws16c48gpio->base + 10); + iowrite8(0xC0, ws16c48gpio->base + 7); =20 return 0; } @@ -396,6 +396,10 @@ static int ws16c48_probe(struct device *dev, unsigned = int id) return -EBUSY; } =20 + ws16c48gpio->base =3D devm_ioport_map(dev, base[id], WS16C48_EXTENT); + if (!ws16c48gpio->base) + return -ENOMEM; + ws16c48gpio->chip.label =3D name; ws16c48gpio->chip.parent =3D dev; ws16c48gpio->chip.owner =3D THIS_MODULE; @@ -409,7 +413,6 @@ static int ws16c48_probe(struct device *dev, unsigned i= nt id) ws16c48gpio->chip.get_multiple =3D ws16c48_gpio_get_multiple; ws16c48gpio->chip.set =3D ws16c48_gpio_set; ws16c48gpio->chip.set_multiple =3D ws16c48_gpio_set_multiple; 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:24 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Jonathan Cameron , Lars-Peter Clausen Subject: [PATCH 7/8] iio: adc: stx104: Utilize iomap interface Date: Tue, 10 May 2022 13:30:59 -0400 Message-Id: <64673797df382c52fc32fce24348b25a0b05e73a.1652201921.git.william.gray@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/iio/adc/stx104.c | 56 +++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 55bd2dc514e9..7552351bfed9 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -51,7 +51,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base= addresses"); */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - unsigned int base; + void __iomem *base; }; =20 /** @@ -64,7 +64,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - unsigned int base; + void __iomem *base; unsigned int out_state; }; =20 @@ -79,7 +79,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config =3D inb(priv->base + 11); + adc_config =3D ioread8(priv->base + 11); gain =3D adc_config & 0x3; =20 *val =3D 1 << gain; @@ -91,24 +91,24 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } =20 /* select ADC channel */ - outb(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); =20 /* trigger ADC sample capture and wait for completion */ - outb(0, priv->base); - while (inb(priv->base + 8) & BIT(7)); + iowrite8(0, priv->base); + while (ioread8(priv->base + 8) & BIT(7)); =20 - *val =3D inw(priv->base); + *val =3D ioread16(priv->base); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config =3D inb(priv->base + 11); + adc_config =3D ioread8(priv->base + 11); adbu =3D !(adc_config & BIT(2)); =20 *val =3D -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config =3D inb(priv->base + 11); + adc_config =3D ioread8(priv->base + 11); adbu =3D !(adc_config & BIT(2)); gain =3D adc_config & 0x3; =20 @@ -130,16 +130,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - outb(0, priv->base + 11); + iowrite8(0, priv->base + 11); break; case 2: - outb(1, priv->base + 11); + iowrite8(1, priv->base + 11); break; case 4: - outb(2, priv->base + 11); + iowrite8(2, priv->base + 11); break; case 8: - outb(3, priv->base + 11); + iowrite8(3, priv->base + 11); break; default: return -EINVAL; @@ -153,7 +153,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; =20 priv->chan_out_states[chan->channel] =3D val; - outw(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, priv->base + 4 + 2 * chan->channel); =20 return 0; } @@ -222,7 +222,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsi= gned int offset) if (offset >=3D 4) return -EINVAL; =20 - return !!(inb(stx104gpio->base) & BIT(offset)); + return !!(ioread8(stx104gpio->base) & BIT(offset)); } =20 static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long = *mask, @@ -230,7 +230,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *c= hip, unsigned long *mask, { struct stx104_gpio *const stx104gpio =3D gpiochip_get_data(chip); =20 - *bits =3D inb(stx104gpio->base); + *bits =3D ioread8(stx104gpio->base); =20 return 0; } @@ -252,7 +252,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, uns= igned int offset, else stx104gpio->out_state &=3D ~mask; =20 - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); =20 spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -279,7 +279,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *= chip, =20 stx104gpio->out_state &=3D ~*mask; stx104gpio->out_state |=3D *mask & *bits; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); =20 spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -306,11 +306,16 @@ static int stx104_probe(struct device *dev, unsigned = int id) return -EBUSY; } =20 + priv =3D iio_priv(indio_dev); + priv->base =3D devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info =3D &stx104_info; indio_dev->modes =3D INDIO_DIRECT_MODE; =20 /* determine if differential inputs */ - if (inb(base[id] + 8) & BIT(5)) { + if (ioread8(priv->base + 8) & BIT(5)) { indio_dev->num_channels =3D ARRAY_SIZE(stx104_channels_diff); indio_dev->channels =3D stx104_channels_diff; } else { @@ -320,18 +325,15 @@ static int stx104_probe(struct device *dev, unsigned = int id) =20 indio_dev->name =3D dev_name(dev); =20 - priv =3D iio_priv(indio_dev); - priv->base =3D base[id]; - /* configure device for software trigger operation */ - outb(0, base[id] + 9); + iowrite8(0, priv->base + 9); =20 /* initialize gain setting to x1 */ - outb(0, base[id] + 11); + iowrite8(0, priv->base + 11); =20 /* initialize DAC output to 0V */ - outw(0, base[id] + 4); - outw(0, base[id] + 6); + iowrite16(0, priv->base + 4); + iowrite16(0, priv->base + 6); =20 stx104gpio->chip.label =3D dev_name(dev); stx104gpio->chip.parent =3D dev; @@ -346,7 +348,7 @@ static int stx104_probe(struct device *dev, unsigned in= t id) stx104gpio->chip.get_multiple =3D stx104_gpio_get_multiple; stx104gpio->chip.set =3D stx104_gpio_set; stx104gpio->chip.set_multiple =3D stx104_gpio_set_multiple; - stx104gpio->base =3D base[id] + 3; + stx104gpio->base =3D priv->base + 3; stx104gpio->out_state =3D 0x0; =20 spin_lock_init(&stx104gpio->lock); --=20 2.35.3 From nobody Sun May 10 09:53:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B00FC433F5 for ; Tue, 10 May 2022 17:33:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348291AbiEJRfu (ORCPT ); Tue, 10 May 2022 13:35:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348255AbiEJRfc (ORCPT ); Tue, 10 May 2022 13:35:32 -0400 Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0BCE4B872 for ; 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[69.109.179.158]) by smtp.gmail.com with ESMTPSA id i6-20020a05620a150600b0069ff8ebec64sm8490411qkk.103.2022.05.10.10.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 May 2022 10:31:25 -0700 (PDT) From: William Breathitt Gray To: linux-iio@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linus.walleij@linaro.org, schnelle@linux.ibm.com, David.Laight@ACULAB.COM, macro@orcam.me.uk, William Breathitt Gray , Jonathan Cameron , Lars-Peter Clausen Subject: [PATCH 8/8] iio: dac: cio-dac: Utilize iomap interface Date: Tue, 10 May 2022 13:31:00 -0400 Message-Id: X-Mailer: git-send-email 2.32.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij --- drivers/iio/dac/cio-dac.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/iio/dac/cio-dac.c b/drivers/iio/dac/cio-dac.c index 95813569f394..8080984dcb03 100644 --- a/drivers/iio/dac/cio-dac.c +++ b/drivers/iio/dac/cio-dac.c @@ -41,7 +41,7 @@ MODULE_PARM_DESC(base, "Measurement Computing CIO-DAC bas= e addresses"); */ struct cio_dac_iio { int chan_out_states[CIO_DAC_NUM_CHAN]; - unsigned int base; + void __iomem *base; }; =20 static int cio_dac_read_raw(struct iio_dev *indio_dev, @@ -71,7 +71,7 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, return -EINVAL; =20 priv->chan_out_states[chan->channel] =3D val; - outw(val, priv->base + chan_addr_offset); + iowrite16(val, priv->base + chan_addr_offset); =20 return 0; } @@ -105,18 +105,20 @@ static int cio_dac_probe(struct device *dev, unsigned= int id) return -EBUSY; } =20 + priv =3D iio_priv(indio_dev); + priv->base =3D devm_ioport_map(dev, base[id], CIO_DAC_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info =3D &cio_dac_info; indio_dev->modes =3D INDIO_DIRECT_MODE; indio_dev->channels =3D cio_dac_channels; indio_dev->num_channels =3D CIO_DAC_NUM_CHAN; indio_dev->name =3D dev_name(dev); =20 - priv =3D iio_priv(indio_dev); - priv->base =3D base[id]; - /* initialize DAC outputs to 0V */ for (i =3D 0; i < 32; i +=3D 2) - outw(0, base[id] + i); + iowrite16(0, priv->base + i); =20 return devm_iio_device_register(dev, indio_dev); } --=20 2.35.3