From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD9E8C4332F for ; Fri, 6 May 2022 03:30:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388585AbiEFDeS (ORCPT ); Thu, 5 May 2022 23:34:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388559AbiEFDd4 (ORCPT ); Thu, 5 May 2022 23:33:56 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3CF89644DE for ; Thu, 5 May 2022 20:30:08 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:27 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 1/9] dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards Date: Fri, 6 May 2022 11:23:15 +0800 Message-Id: X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This introduces bindings for boards based Sunplus SP7021 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qin Jian --- .../bindings/arm/sunplus,sp7021.yaml | 28 +++++++++++++++++++ MAINTAINERS | 7 +++++ 2 files changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/sunplus,sp7021.ya= ml diff --git a/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml b/Do= cumentation/devicetree/bindings/arm/sunplus,sp7021.yaml new file mode 100644 index 000000000..ef48fb270 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Boards Device Tree Bindings + +maintainers: + - qinjian + +description: | + ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC. + Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - sunplus,sp7021-achip + - const: sunplus,sp7021 + +additionalProperties: true + +... diff --git a/MAINTAINERS b/MAINTAINERS index cd0f68d4a..8b5e2e639 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2738,6 +2738,13 @@ F: drivers/clocksource/armv7m_systick.c N: stm32 N: stm =20 +ARM/SUNPLUS SP7021 SOC SUPPORT +M: Qin Jian +L: linux-arm-kernel@lists.infradead.org (moderated for mon-subscribers) +S: Maintained +W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview +F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml + ARM/Synaptics SoC support M: Jisheng Zhang M: Sebastian Hesselbarth --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D9CAC433F5 for ; Fri, 6 May 2022 03:31:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388649AbiEFDf1 (ORCPT ); Thu, 5 May 2022 23:35:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388607AbiEFDeV (ORCPT ); Thu, 5 May 2022 23:34:21 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 54AB0D65 for ; Thu, 5 May 2022 20:30:14 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:28 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian , Rob Herring Subject: [PATCH v14 2/9] dt-bindings: reset: Add bindings for SP7021 reset driver Date: Fri, 6 May 2022 11:23:16 +0800 Message-Id: <454127e7321ff107d868421edd8fffc86480831c.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation to describe Sunplus SP7021 reset driver bindings. Reviewed-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qin Jian --- .../bindings/reset/sunplus,reset.yaml | 38 ++++++++ MAINTAINERS | 2 + include/dt-bindings/reset/sp-sp7021.h | 87 +++++++++++++++++++ 3 files changed, 127 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/sunplus,reset.y= aml create mode 100644 include/dt-bindings/reset/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/reset/sunplus,reset.yaml b/D= ocumentation/devicetree/bindings/reset/sunplus,reset.yaml new file mode 100644 index 000000000..f24646ba9 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/sunplus,reset.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/sunplus,reset.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Sunplus SoC Reset Controller + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-reset + + reg: + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + rstc: reset@9c000054 { + compatible =3D "sunplus,sp7021-reset"; + reg =3D <0x9c000054 0x28>; + #reset-cells =3D <1>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 8b5e2e639..a8be86b25 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2744,6 +2744,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated fo= r mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: include/dt-bindings/reset/sp-sp7021.h =20 ARM/Synaptics SoC support M: Jisheng Zhang diff --git a/include/dt-bindings/reset/sp-sp7021.h b/include/dt-bindings/re= set/sp-sp7021.h new file mode 100644 index 000000000..ab4867073 --- /dev/null +++ b/include/dt-bindings/reset/sp-sp7021.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_RST_SUNPLUS_SP7021_H +#define _DT_BINDINGS_RST_SUNPLUS_SP7021_H + +#define RST_SYSTEM 0 +#define RST_RTC 1 +#define RST_IOCTL 2 +#define RST_IOP 3 +#define RST_OTPRX 4 +#define RST_NOC 5 +#define RST_BR 6 +#define RST_RBUS_L00 7 +#define RST_SPIFL 8 +#define RST_SDCTRL0 9 +#define RST_PERI0 10 +#define RST_A926 11 +#define RST_UMCTL2 12 +#define RST_PERI1 13 +#define RST_DDR_PHY0 14 +#define RST_ACHIP 15 +#define RST_STC0 16 +#define RST_STC_AV0 17 +#define RST_STC_AV1 18 +#define RST_STC_AV2 19 +#define RST_UA0 20 +#define RST_UA1 21 +#define RST_UA2 22 +#define RST_UA3 23 +#define RST_UA4 24 +#define RST_HWUA 25 +#define RST_DDC0 26 +#define RST_UADMA 27 +#define RST_CBDMA0 28 +#define RST_CBDMA1 29 +#define RST_SPI_COMBO_0 30 +#define RST_SPI_COMBO_1 31 +#define RST_SPI_COMBO_2 32 +#define RST_SPI_COMBO_3 33 +#define RST_AUD 34 +#define RST_USBC0 35 +#define RST_USBC1 36 +#define RST_UPHY0 37 +#define RST_UPHY1 38 +#define RST_I2CM0 39 +#define RST_I2CM1 40 +#define RST_I2CM2 41 +#define RST_I2CM3 42 +#define RST_PMC 43 +#define RST_CARD_CTL0 44 +#define RST_CARD_CTL1 45 +#define RST_CARD_CTL4 46 +#define RST_BCH 47 +#define RST_DDFCH 48 +#define RST_CSIIW0 49 +#define RST_CSIIW1 50 +#define RST_MIPICSI0 51 +#define RST_MIPICSI1 52 +#define RST_HDMI_TX 53 +#define RST_VPOST 54 +#define RST_TGEN 55 +#define RST_DMIX 56 +#define RST_TCON 57 +#define RST_INTERRUPT 58 +#define RST_RGST 59 +#define RST_GPIO 60 +#define RST_RBUS_TOP 61 +#define RST_MAILBOX 62 +#define RST_SPIND 63 +#define RST_I2C2CBUS 64 +#define RST_SEC 65 +#define RST_DVE 66 +#define RST_GPOST0 67 +#define RST_OSD0 68 +#define RST_DISP_PWM 69 +#define RST_UADBG 70 +#define RST_DUMMY_MASTER 71 +#define RST_FIO_CTL 72 +#define RST_FPGA 73 +#define RST_L2SW 74 +#define RST_ICM 75 +#define RST_AXI_GLOBAL 76 + +#endif --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10EA6C433FE for ; Fri, 6 May 2022 03:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388614AbiEFDfN (ORCPT ); Thu, 5 May 2022 23:35:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388599AbiEFDeU (ORCPT ); Thu, 5 May 2022 23:34:20 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9AD3C1B7 for ; Thu, 5 May 2022 20:30:14 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:28 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 3/9] reset: Add Sunplus SP7021 reset driver Date: Fri, 6 May 2022 11:23:17 +0800 Message-Id: <7fa394ed3cfcf44cd4af8c1e9c9d45db120da47f.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add reset driver for Sunplus SP7021 SoC. Reviewed-by: Philipp Zabel Signed-off-by: Qin Jian --- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-sunplus.c | 212 ++++++++++++++++++++++++++++++++++ 4 files changed, 223 insertions(+) create mode 100644 drivers/reset/reset-sunplus.c diff --git a/MAINTAINERS b/MAINTAINERS index a8be86b25..26066f199 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2745,6 +2745,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/reset/reset-sunplus.c F: include/dt-bindings/reset/sp-sp7021.h =20 ARM/Synaptics SoC support diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 6f8ba0ddc..36825787e 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -231,6 +231,15 @@ config RESET_STARFIVE_JH7100 help This enables the reset controller driver for the StarFive JH7100 SoC. =20 +config RESET_SUNPLUS + bool "Sunplus SoCs Reset Driver" if COMPILE_TEST + default ARCH_SUNPLUS + help + This enables the reset driver support for Sunplus SoCs. + The reset lines that can be asserted and deasserted by toggling bits + in a contiguous, exclusive register space. The register is HIWORD_MASKE= D, + which means each register hold 16 reset lines. + config RESET_SUNXI bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI default ARCH_SUNXI diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index bd0a97be1..cadc46d3e 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_RESET_SCMI) +=3D reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_STARFIVE_JH7100) +=3D reset-starfive-jh7100.o +obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o obj-$(CONFIG_RESET_TI_SCI) +=3D reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) +=3D reset-ti-syscon.o diff --git a/drivers/reset/reset-sunplus.c b/drivers/reset/reset-sunplus.c new file mode 100644 index 000000000..2f23ecaa7 --- /dev/null +++ b/drivers/reset/reset-sunplus.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * SP7021 reset driver + * + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +/* HIWORD_MASK_REG BITS */ +#define BITS_PER_HWM_REG 16 + +/* resets HW info: reg_index_shift */ +static const u32 sp_resets[] =3D { +/* SP7021: mo_reset0 ~ mo_reset9 */ + 0x00, + 0x02, + 0x03, + 0x04, + 0x05, + 0x06, + 0x07, + 0x08, + 0x09, + 0x0a, + 0x0b, + 0x0d, + 0x0e, + 0x0f, + 0x10, + 0x12, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1a, + 0x1b, + 0x1c, + 0x1d, + 0x1e, + 0x1f, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x2a, + 0x2b, + 0x2d, + 0x2e, + 0x30, + 0x31, + 0x32, + 0x33, + 0x3d, + 0x3e, + 0x3f, + 0x42, + 0x44, + 0x4b, + 0x4c, + 0x4d, + 0x4e, + 0x4f, + 0x50, + 0x55, + 0x60, + 0x61, + 0x6a, + 0x6f, + 0x70, + 0x73, + 0x74, + 0x86, + 0x8a, + 0x8b, + 0x8d, + 0x8e, + 0x8f, + 0x90, + 0x92, + 0x93, + 0x94, + 0x95, + 0x96, + 0x97, + 0x98, + 0x99, +}; + +struct sp_reset { + struct reset_controller_dev rcdev; + struct notifier_block notifier; + void __iomem *base; +}; + +static inline struct sp_reset *to_sp_reset(struct reset_controller_dev *rc= dev) +{ + return container_of(rcdev, struct sp_reset, rcdev); +} + +static int sp_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct sp_reset *reset =3D to_sp_reset(rcdev); + int index =3D sp_resets[id] / BITS_PER_HWM_REG; + int shift =3D sp_resets[id] % BITS_PER_HWM_REG; + u32 val; + + val =3D (1 << (16 + shift)) | (assert << shift); + writel(val, reset->base + (index * 4)); + + return 0; +} + +static int sp_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return sp_reset_update(rcdev, id, true); +} + +static int sp_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return sp_reset_update(rcdev, id, false); +} + +static int sp_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct sp_reset *reset =3D to_sp_reset(rcdev); + int index =3D sp_resets[id] / BITS_PER_HWM_REG; + int shift =3D sp_resets[id] % BITS_PER_HWM_REG; + u32 reg; + + reg =3D readl(reset->base + (index * 4)); + + return !!(reg & BIT(shift)); +} + +static const struct reset_control_ops sp_reset_ops =3D { + .assert =3D sp_reset_assert, + .deassert =3D sp_reset_deassert, + .status =3D sp_reset_status, +}; + +static int sp_restart(struct notifier_block *nb, unsigned long mode, + void *cmd) +{ + struct sp_reset *reset =3D container_of(nb, struct sp_reset, notifier); + + sp_reset_assert(&reset->rcdev, 0); + sp_reset_deassert(&reset->rcdev, 0); + + return NOTIFY_DONE; +} + +static int sp_reset_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sp_reset *reset; + struct resource *res; + int ret; + + reset =3D devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + reset->base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(reset->base)) + return PTR_ERR(reset->base); + + reset->rcdev.ops =3D &sp_reset_ops; + reset->rcdev.owner =3D THIS_MODULE; + reset->rcdev.of_node =3D dev->of_node; + reset->rcdev.nr_resets =3D resource_size(res) / 4 * BITS_PER_HWM_REG; + + ret =3D devm_reset_controller_register(dev, &reset->rcdev); + if (ret) + return ret; + + reset->notifier.notifier_call =3D sp_restart; + reset->notifier.priority =3D 192; + + return register_restart_handler(&reset->notifier); +} + +static const struct of_device_id sp_reset_dt_ids[] =3D { + {.compatible =3D "sunplus,sp7021-reset",}, + { /* sentinel */ }, +}; + +static struct platform_driver sp_reset_driver =3D { + .probe =3D sp_reset_probe, + .driver =3D { + .name =3D "sunplus-reset", + .of_match_table =3D sp_reset_dt_ids, + .suppress_bind_attrs =3D true, + }, +}; +builtin_platform_driver(sp_reset_driver); --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64E0BC433F5 for ; Fri, 6 May 2022 03:30:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388593AbiEFDea (ORCPT ); Thu, 5 May 2022 23:34:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388587AbiEFDd5 (ORCPT ); Thu, 5 May 2022 23:33:57 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2BD0F644F8 for ; Thu, 5 May 2022 20:30:06 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:28 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 4/9] dt-bindings: clock: Add bindings for SP7021 clock driver Date: Fri, 6 May 2022 11:23:18 +0800 Message-Id: <96fb8d38c891ee0716375a9194b4870c43946122.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation to describe Sunplus SP7021 clock driver bindings. Signed-off-by: Qin Jian --- fix the comments from Krzysztof & Rob. --- .../bindings/clock/sunplus,sp7021-clkc.yaml | 51 +++++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/sp-sp7021.h | 88 +++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sunplus,sp7021-= clkc.yaml create mode 100644 include/dt-bindings/clock/sp-sp7021.h diff --git a/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.ya= ml b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml new file mode 100644 index 000000000..859b2cca5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Clock Controller Binding + +maintainers: + - Qin Jian + +properties: + compatible: + const: sunplus,sp7021-clkc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + + extclk: osc0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + clock-output-names =3D "extclk"; + }; + + clkc: clock-controller@9c000000 { + compatible =3D "sunplus,sp7021-clkc"; + reg =3D <0x9c000000 0x280>; + clocks =3D <&extclk>; + #clock-cells =3D <1>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 26066f199..5d8b420d0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2744,8 +2744,10 @@ L: linux-arm-kernel@lists.infradead.org (moderated f= or mon-subscribers) S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml +F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/reset/reset-sunplus.c +F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h =20 ARM/Synaptics SoC support diff --git a/include/dt-bindings/clock/sp-sp7021.h b/include/dt-bindings/cl= ock/sp-sp7021.h new file mode 100644 index 000000000..cd84321eb --- /dev/null +++ b/include/dt-bindings/clock/sp-sp7021.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H +#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H + +/* gates */ +#define CLK_RTC 0 +#define CLK_OTPRX 1 +#define CLK_NOC 2 +#define CLK_BR 3 +#define CLK_SPIFL 4 +#define CLK_PERI0 5 +#define CLK_PERI1 6 +#define CLK_STC0 7 +#define CLK_STC_AV0 8 +#define CLK_STC_AV1 9 +#define CLK_STC_AV2 10 +#define CLK_UA0 11 +#define CLK_UA1 12 +#define CLK_UA2 13 +#define CLK_UA3 14 +#define CLK_UA4 15 +#define CLK_HWUA 16 +#define CLK_DDC0 17 +#define CLK_UADMA 18 +#define CLK_CBDMA0 19 +#define CLK_CBDMA1 20 +#define CLK_SPI_COMBO_0 21 +#define CLK_SPI_COMBO_1 22 +#define CLK_SPI_COMBO_2 23 +#define CLK_SPI_COMBO_3 24 +#define CLK_AUD 25 +#define CLK_USBC0 26 +#define CLK_USBC1 27 +#define CLK_UPHY0 28 +#define CLK_UPHY1 29 +#define CLK_I2CM0 30 +#define CLK_I2CM1 31 +#define CLK_I2CM2 32 +#define CLK_I2CM3 33 +#define CLK_PMC 34 +#define CLK_CARD_CTL0 35 +#define CLK_CARD_CTL1 36 +#define CLK_CARD_CTL4 37 +#define CLK_BCH 38 +#define CLK_DDFCH 39 +#define CLK_CSIIW0 40 +#define CLK_CSIIW1 41 +#define CLK_MIPICSI0 42 +#define CLK_MIPICSI1 43 +#define CLK_HDMI_TX 44 +#define CLK_VPOST 45 +#define CLK_TGEN 46 +#define CLK_DMIX 47 +#define CLK_TCON 48 +#define CLK_GPIO 49 +#define CLK_MAILBOX 50 +#define CLK_SPIND 51 +#define CLK_I2C2CBUS 52 +#define CLK_SEC 53 +#define CLK_DVE 54 +#define CLK_GPOST0 55 +#define CLK_OSD0 56 +#define CLK_DISP_PWM 57 +#define CLK_UADBG 58 +#define CLK_FIO_CTL 59 +#define CLK_FPGA 60 +#define CLK_L2SW 61 +#define CLK_ICM 62 +#define CLK_AXI_GLOBAL 63 + +/* plls */ +#define PLL_A 64 +#define PLL_E 65 +#define PLL_E_2P5 66 +#define PLL_E_25 67 +#define PLL_E_112P5 68 +#define PLL_F 69 +#define PLL_TV 70 +#define PLL_TV_A 71 +#define PLL_SYS 72 + +#define CLK_MAX 73 + +#endif --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 524FBC433F5 for ; Fri, 6 May 2022 03:31:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388703AbiEFDfS (ORCPT ); Thu, 5 May 2022 23:35:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388600AbiEFDeU (ORCPT ); Thu, 5 May 2022 23:34:20 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8C7D911C37 for ; Thu, 5 May 2022 20:30:17 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:28 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 5/9] clk: Add Sunplus SP7021 clock driver Date: Fri, 6 May 2022 11:23:19 +0800 Message-Id: <3dd18fbdb3d8db9a6436b2fa442b4fcc7e8e1a68.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add clock driver for Sunplus SP7021 SoC. Signed-off-by: Qin Jian --- Fix the comments from Arnd. --- MAINTAINERS | 1 + drivers/clk/Kconfig | 10 + drivers/clk/Makefile | 1 + drivers/clk/clk-sp7021.c | 721 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 733 insertions(+) create mode 100644 drivers/clk/clk-sp7021.c diff --git a/MAINTAINERS b/MAINTAINERS index 5d8b420d0..8b77f7ae4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2746,6 +2746,7 @@ W: https://sunplus-tibbo.atlassian.net/wiki/spaces/do= c/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index d4d67fbae..9eedeea78 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -351,6 +351,16 @@ config COMMON_CLK_VC5 This driver supports the IDT VersaClock 5 and VersaClock 6 programmable clock generators. =20 +config COMMON_CLK_SP7021 + bool "Clock driver for Sunplus SP7021 SoC" + depends on SOC_SP7021 || COMPILE_TEST + default SOC_SP7021 + help + This driver supports the Sunplus SP7021 SoC clocks. + It implements SP7021 PLLs/gate. + Not all features of the PLL are currently supported + by the driver. + config COMMON_CLK_STM32MP157 def_bool COMMON_CLK && MACH_STM32MP157 help diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 16e588630..377ea7f7b 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -61,6 +61,7 @@ obj-$(CONFIG_COMMON_CLK_SI5351) +=3D clk-si5351.o obj-$(CONFIG_COMMON_CLK_SI514) +=3D clk-si514.o obj-$(CONFIG_COMMON_CLK_SI544) +=3D clk-si544.o obj-$(CONFIG_COMMON_CLK_SI570) +=3D clk-si570.o +obj-$(CONFIG_COMMON_CLK_SP7021) +=3D clk-sp7021.o obj-$(CONFIG_COMMON_CLK_STM32F) +=3D clk-stm32f4.o obj-$(CONFIG_COMMON_CLK_STM32H7) +=3D clk-stm32h7.o obj-$(CONFIG_COMMON_CLK_STM32MP157) +=3D clk-stm32mp1.o diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c new file mode 100644 index 000000000..61e401b1a --- /dev/null +++ b/drivers/clk/clk-sp7021.c @@ -0,0 +1,721 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG(i) (pll_regs + (i) * 4) + +#define PLLA_CTL REG(7) +#define PLLE_CTL REG(12) +#define PLLF_CTL REG(13) +#define PLLTV_CTL REG(14) +#define PLLSYS_CTL REG(26) + +/* speical div_width values for PLLTV/PLLA */ +#define DIV_TV 33 +#define DIV_A 34 + +/* PLLTV parameters */ +enum { + SEL_FRA, + SDM_MOD, + PH_SEL, + NFRA, + DIVR, + DIVN, + DIVM, + P_MAX +}; + +#define MASK_SEL_FRA GENMASK(1, 1) +#define MASK_SDM_MOD GENMASK(2, 2) +#define MASK_PH_SEL GENMASK(4, 4) +#define MASK_NFRA GENMASK(12, 6) +#define MASK_DIVR GENMASK(8, 7) +#define MASK_DIVN GENMASK(7, 0) +#define MASK_DIVM GENMASK(14, 8) + +/* HIWORD_MASK FIELD_PREP */ +#define HWM_FIELD_PREP(mask, value) \ +({ \ + u32 m =3D mask; \ + (m << 16) | FIELD_PREP(m, value); \ +}) + +struct sp_pll { + struct clk_hw hw; + void __iomem *reg; + spinlock_t *lock; /* lock for reg */ + int div_shift; + int div_width; + int pd_bit; /* power down bit idx */ + int bp_bit; /* bypass bit idx */ + unsigned long brate; /* base rate, TODO: replace brate with muldiv */ + u32 p[P_MAX]; /* for hold PLLTV/PLLA parameters */ +}; + +#define to_sp_pll(_hw) container_of(_hw, struct sp_pll, hw) + +#define clk_regs (sp_clk_base + 0x000) /* G0 ~ CLKEN */ +#define pll_regs (sp_clk_base + 0x200) /* G4 ~ PLL */ +static void __iomem *sp_clk_base; +static struct clk_hw_onecell_data *sp_clk_data; + +#define F_EXTCLK BIT(16) /* parent clock is EXTCLK */ + +/* gates HW info: reg_index_shift | parent */ +static const u32 sp_clk_gates[] =3D { + 0x12, + 0x15, + 0x16, + 0x17, + 0x19, + 0x1b | F_EXTCLK, + 0x1f | F_EXTCLK, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28 | F_EXTCLK, + 0x29 | F_EXTCLK, + 0x2a | F_EXTCLK, + 0x2b | F_EXTCLK, + 0x2c | F_EXTCLK, + 0x2d | F_EXTCLK, + 0x2e, + 0x2f | F_EXTCLK, + 0x30, + 0x31, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x3a, + 0x3b, + 0x3d, + 0x3e, + 0x40, + 0x41, + 0x42, + 0x43, + 0x4d, + 0x4e, + 0x4f, + 0x52, + 0x54, + 0x5b, + 0x5c, + 0x5d, + 0x5e, + 0x5f, + 0x60, + 0x65, + 0x70, + 0x71, + 0x7a, + 0x83, + 0x96, + 0x9a, + 0x9b, + 0x9d, + 0x9e, + 0x9f, + 0xa0, + 0xa2, + 0xa3, + 0xa5, + 0xa6, + 0xa7, + 0xa8, + 0xa9, +}; + +static DEFINE_SPINLOCK(plla_lock); +static DEFINE_SPINLOCK(plle_lock); +static DEFINE_SPINLOCK(pllf_lock); +static DEFINE_SPINLOCK(pllsys_lock); +static DEFINE_SPINLOCK(plltv_lock); + +#define _M 1000000UL +#define F_27M (27 * _M) + +/*********************************** PLL_TV ******************************= ****/ + +/* TODO: set proper FVCO range */ +#define FVCO_MIN (100 * _M) +#define FVCO_MAX (200 * _M) + +#define F_MIN (FVCO_MIN / 8) +#define F_MAX (FVCO_MAX) + +static long plltv_integer_div(struct sp_pll *clk, unsigned long freq) +{ + /* valid m values: 27M must be divisible by m, 0 means end */ + static const u32 m_table[] =3D { + 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 27, 30, 32, 0 + }; + u32 m, n, r; + unsigned long fvco, nf; + + freq =3D clamp(freq, F_MIN, F_MAX); + + /* DIVR 0~3 */ + for (r =3D 0; r <=3D 3; r++) { + fvco =3D freq << r; + if (fvco <=3D FVCO_MAX) + break; + } + + /* DIVM */ + for (m =3D 0; m_table[m]; m++) { + nf =3D fvco * m_table[m]; + n =3D nf / F_27M; + if ((n * F_27M) =3D=3D nf) + break; + } + m =3D m_table[m]; + + if (!m) { + pr_err("%s: %s freq:%lu not found a valid setting\n", + __func__, clk_hw_get_name(&clk->hw), freq); + return -EINVAL; + } + + /* save parameters */ + clk->p[SEL_FRA] =3D 0; + clk->p[DIVR] =3D r; + clk->p[DIVN] =3D n; + clk->p[DIVM] =3D m; + + return freq; +} + +/* parameters for PLLTV fractional divider */ +static const u32 pt[][5] =3D { + /* conventional fractional */ + { + 1, // factor + 5, // 5 * p0 (nint) + 1, // 1 * p0 + F_27M, // F_27M / p0 + 1, // p0 / p2 + }, + /* phase rotation */ + { + 10, // factor + 54, // 5.4 * p0 (nint) + 2, // 0.2 * p0 + F_27M / 10, // F_27M / p0 + 5, // p0 / p2 + }, +}; + +static const u32 mods[] =3D { 91, 55 }; /* SDM_MOD mod values */ + +static long plltv_fractional_div(struct sp_pll *clk, unsigned long freq) +{ + u32 m, r; + u32 nint, nfra; + u32 df_quotient_min =3D 210000000; + u32 df_remainder_min =3D 0; + unsigned long fvco, nf, f, fout =3D 0; + int sdm, ph; + + freq =3D clamp(freq, F_MIN, F_MAX); + + /* DIVR 0~3 */ + for (r =3D 0; r <=3D 3; r++) { + fvco =3D freq << r; + if (fvco <=3D FVCO_MAX) + break; + } + f =3D F_27M >> r; + + /* PH_SEL 1/0 */ + for (ph =3D 1; ph >=3D 0; ph--) { + const u32 *pp =3D pt[ph]; + u32 ms =3D 1; + + /* SDM_MOD 0/1 */ + for (sdm =3D 0; sdm <=3D 1; sdm++) { + u32 mod =3D mods[sdm]; + + /* DIVM 1~32 */ + for (m =3D ms; m <=3D 32; m++) { + u32 df; /* diff freq */ + u32 df_quotient, df_remainder; + + nf =3D fvco * m; + nint =3D nf / pp[3]; + + if (nint < pp[1]) + continue; + if (nint > pp[1]) + break; + + nfra =3D (((nf % pp[3]) * mod * pp[4]) + (F_27M / 2)) / F_27M; + if (nfra) + df =3D (f * (nint + pp[2]) / pp[0]) - + (f * (mod - nfra) / mod / pp[4]); + else + df =3D (f * (nint) / pp[0]); + + df_quotient =3D df / m; + df_remainder =3D ((df % m) * 1000) / m; + + if (freq > df_quotient) { + df_quotient =3D freq - df_quotient - 1; + df_remainder =3D 1000 - df_remainder; + } else { + df_quotient =3D df_quotient - freq; + } + + if (df_quotient_min > df_quotient || + (df_quotient_min =3D=3D df_quotient && + df_remainder_min > df_remainder)) { + /* found a closer freq, save parameters */ + clk->p[SEL_FRA] =3D 1; + clk->p[SDM_MOD] =3D sdm; + clk->p[PH_SEL] =3D ph; + clk->p[NFRA] =3D nfra; + clk->p[DIVR] =3D r; + clk->p[DIVM] =3D m; + + fout =3D df / m; + df_quotient_min =3D df_quotient; + df_remainder_min =3D df_remainder; + } + } + } + } + + if (!fout) { + pr_err("%s: %s freq:%lu not found a valid setting\n", + __func__, clk_hw_get_name(&clk->hw), freq); + return -EINVAL; + } + + return fout; +} + +static long plltv_div(struct sp_pll *clk, unsigned long freq) +{ + if (freq % 100) + return plltv_fractional_div(clk, freq); + + return plltv_integer_div(clk, freq); +} + +static void plltv_set_rate(struct sp_pll *clk) +{ + u32 reg; + + reg =3D HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); + reg |=3D HWM_FIELD_PREP(MASK_SDM_MOD, clk->p[SDM_MOD]); + reg |=3D HWM_FIELD_PREP(MASK_PH_SEL, clk->p[PH_SEL]); + reg |=3D HWM_FIELD_PREP(MASK_NFRA, clk->p[NFRA]); + writel(reg, clk->reg); + + reg =3D HWM_FIELD_PREP(MASK_DIVR, clk->p[DIVR]); + writel(reg, clk->reg + 4); + + reg =3D HWM_FIELD_PREP(MASK_DIVN, clk->p[DIVN] - 1); + reg |=3D HWM_FIELD_PREP(MASK_DIVM, clk->p[DIVM] - 1); + writel(reg, clk->reg + 8); +} + +/*********************************** PLL_A *******************************= ****/ + +/* from Q628_PLLs_REG_setting.xlsx */ +static const struct { + u32 rate; + u32 regs[5]; +} pa[] =3D { + { + .rate =3D 135475200, + .regs =3D { + 0x4801, + 0x02df, + 0x248f, + 0x0211, + 0x33e9 + } + }, + { + .rate =3D 147456000, + .regs =3D { + 0x4801, + 0x1adf, + 0x2490, + 0x0349, + 0x33e9 + } + }, + { + .rate =3D 196608000, + .regs =3D { + 0x4801, + 0x42ef, + 0x2495, + 0x01c6, + 0x33e9 + } + }, +}; + +static void plla_set_rate(struct sp_pll *clk) +{ + const u32 *pp =3D pa[clk->p[0]].regs; + int i; + + for (i =3D 0; i < ARRAY_SIZE(pa->regs); i++) + writel(0xffff0000 | pp[i], clk->reg + (i * 4)); +} + +static long plla_round_rate(struct sp_pll *clk, unsigned long rate) +{ + int i =3D ARRAY_SIZE(pa); + + while (--i) { + if (rate >=3D pa[i].rate) + break; + } + clk->p[0] =3D i; + + return pa[i].rate; +} + +/********************************** SP_PLL *******************************= ****/ + +static long sp_pll_calc_div(struct sp_pll *clk, unsigned long rate) +{ + u32 fbdiv; + u32 max =3D 1 << clk->div_width; + + fbdiv =3D DIV_ROUND_CLOSEST(rate, clk->brate); + if (fbdiv > max) + fbdiv =3D max; + + return fbdiv; +} + +static long sp_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct sp_pll *clk =3D to_sp_pll(hw); + long ret; + + if (rate =3D=3D *prate) { + ret =3D *prate; /* bypass */ + } else if (clk->div_width =3D=3D DIV_A) { + ret =3D plla_round_rate(clk, rate); + } else if (clk->div_width =3D=3D DIV_TV) { + ret =3D plltv_div(clk, rate); + if (ret < 0) + ret =3D *prate; + } else { + ret =3D sp_pll_calc_div(clk, rate) * clk->brate; + } + + return ret; +} + +static unsigned long sp_pll_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct sp_pll *clk =3D to_sp_pll(hw); + u32 reg =3D readl(clk->reg); + unsigned long ret; + + if (reg & BIT(clk->bp_bit)) { + ret =3D prate; /* bypass */ + } else if (clk->div_width =3D=3D DIV_A) { + ret =3D pa[clk->p[0]].rate; + } else if (clk->div_width =3D=3D DIV_TV) { + u32 m, r, reg2; + + r =3D FIELD_GET(MASK_DIVR, readl(clk->reg + 4)); + reg2 =3D readl(clk->reg + 8); + m =3D FIELD_GET(MASK_DIVM, reg2) + 1; + + if (reg & BIT(1)) { /* SEL_FRA */ + /* fractional divider */ + u32 sdm =3D FIELD_GET(MASK_SDM_MOD, reg); + u32 ph =3D FIELD_GET(MASK_PH_SEL, reg); + u32 nfra =3D FIELD_GET(MASK_NFRA, reg); + const u32 *pp =3D pt[ph]; + + ret =3D prate >> r; + ret =3D (ret * (pp[1] + pp[2]) / pp[0]) - + (ret * (mods[sdm] - nfra) / mods[sdm] / pp[4]); + ret /=3D m; + } else { + /* integer divider */ + u32 n =3D FIELD_GET(MASK_DIVN, reg2) + 1; + + ret =3D (prate / m * n) >> r; + } + } else { + u32 fbdiv =3D ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + = 1; + + ret =3D clk->brate * fbdiv; + } + + return ret; +} + +static int sp_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct sp_pll *clk =3D to_sp_pll(hw); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(clk->lock, flags); + + reg =3D BIT(clk->bp_bit + 16); /* HIWORD_MASK */ + + if (rate =3D=3D prate) { + reg |=3D BIT(clk->bp_bit); /* bypass */ + } else if (clk->div_width =3D=3D DIV_A) { + plla_set_rate(clk); + } else if (clk->div_width =3D=3D DIV_TV) { + plltv_set_rate(clk); + } else if (clk->div_width) { + u32 fbdiv =3D sp_pll_calc_div(clk, rate); + u32 mask =3D GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift= ); + + reg |=3D (mask << 16) | (((fbdiv - 1) << clk->div_shift) & mask); + } + + writel(reg, clk->reg); + + spin_unlock_irqrestore(clk->lock, flags); + + return 0; +} + +static int sp_pll_enable(struct clk_hw *hw) +{ + struct sp_pll *clk =3D to_sp_pll(hw); + + writel(BIT(clk->pd_bit + 16) | BIT(clk->pd_bit), clk->reg); /* power up */ + + return 0; +} + +static void sp_pll_disable(struct clk_hw *hw) +{ + struct sp_pll *clk =3D to_sp_pll(hw); + + writel(BIT(clk->pd_bit + 16), clk->reg); /* power down */ +} + +static int sp_pll_is_enabled(struct clk_hw *hw) +{ + struct sp_pll *clk =3D to_sp_pll(hw); + + return readl(clk->reg) & BIT(clk->pd_bit); +} + +static const struct clk_ops sp_pll_ops =3D { + .enable =3D sp_pll_enable, + .disable =3D sp_pll_disable, + .is_enabled =3D sp_pll_is_enabled, + .round_rate =3D sp_pll_round_rate, + .recalc_rate =3D sp_pll_recalc_rate, + .set_rate =3D sp_pll_set_rate +}; + +static const struct clk_ops sp_pll_sub_ops =3D { + .enable =3D sp_pll_enable, + .disable =3D sp_pll_disable, + .is_enabled =3D sp_pll_is_enabled, + .recalc_rate =3D sp_pll_recalc_rate, +}; + +static void dbg_clk(struct clk_hw *hw) +{ + const char *name =3D clk_hw_get_name(hw); + unsigned long rate =3D clk_hw_get_rate(hw); + + pr_debug("%-20s%lu\n", name, rate); +} + +static struct clk_hw *sp_pll_register(struct device *dev, const char *name, + const struct clk_parent_data *parent_data, + void __iomem *reg, int pd_bit, int bp_bit, + unsigned long brate, int shift, int width, + spinlock_t *lock) +{ + struct sp_pll *pll; + struct clk_hw *hw; + struct clk_init_data initd =3D { + .name =3D name, + .parent_data =3D parent_data, + .ops =3D (bp_bit >=3D 0) ? &sp_pll_ops : &sp_pll_sub_ops, + .num_parents =3D 1, + /* system clock, should not be disabled */ + .flags =3D (reg =3D=3D PLLSYS_CTL) ? CLK_IS_CRITICAL : 0, + }; + int ret; + + pll =3D devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->hw.init =3D &initd; + pll->reg =3D reg; + pll->pd_bit =3D pd_bit; + pll->bp_bit =3D bp_bit; + pll->brate =3D brate; + pll->div_shift =3D shift; + pll->div_width =3D width; + pll->lock =3D lock; + + hw =3D &pll->hw; + ret =3D devm_clk_hw_register(dev, hw); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + dbg_clk(hw); + + return hw; +} + +static int sp7021_clk_probe(struct platform_device *pdev) +{ + static const u32 sp_clken[] =3D { + 0x67ef, 0x03ff, 0xff03, 0xfff0, 0x0004, /* G0.1~5 */ + 0x0000, 0x8000, 0xffff, 0x0040, 0x0000, /* G0.6~10 */ + }; + static struct clk_parent_data pd_ext, pd_sys, pd_e; + struct device *dev =3D &pdev->dev; + struct clk_hw **hws; + struct resource *res; + int i; + + /* This memory region include multi HW regs in discontinuous order. + * clk driver used some discontinuous areas in the memory region. + * Using devm_platform_ioremap_resource() would conflicted with other dri= vers. + */ + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + sp_clk_base =3D devm_ioremap(dev, res->start, resource_size(res)); + if (!sp_clk_base) + return -ENXIO; + + /* enable default clks */ + for (i =3D 0; i < ARRAY_SIZE(sp_clken); i++) + writel((sp_clken[i] << 16) | sp_clken[i], sp_clk_base + 4 * (1 + i)); + + sp_clk_data =3D devm_kzalloc(dev, struct_size(sp_clk_data, hws, CLK_MAX), + GFP_KERNEL); + if (!sp_clk_data) + return -ENOMEM; + + hws =3D sp_clk_data->hws; + pd_ext.fw_name =3D "extclk"; + + /* PLL_A */ + hws[PLL_A] =3D sp_pll_register(dev, "plla", &pd_ext, PLLA_CTL, + 11, 12, 27000000, 0, DIV_A, &plla_lock); + if (IS_ERR(hws[PLL_A])) + return PTR_ERR(hws[PLL_A]); + + /* PLL_E */ + hws[PLL_E] =3D sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL, + 6, 2, 50000000, 0, 0, &plle_lock); + if (IS_ERR(hws[PLL_E])) + return PTR_ERR(hws[PLL_E]); + pd_e.hw =3D hws[PLL_E]; + hws[PLL_E_2P5] =3D sp_pll_register(dev, "plle_2p5", &pd_e, PLLE_CTL, + 13, -1, 2500000, 0, 0, &plle_lock); + if (IS_ERR(hws[PLL_E_2P5])) + return PTR_ERR(hws[PLL_E_2P5]); + hws[PLL_E_25] =3D sp_pll_register(dev, "plle_25", &pd_e, PLLE_CTL, + 12, -1, 25000000, 0, 0, &plle_lock); + if (IS_ERR(hws[PLL_E_25])) + return PTR_ERR(hws[PLL_E_25]); + hws[PLL_E_112P5] =3D sp_pll_register(dev, "plle_112p5", &pd_e, PLLE_CTL, + 11, -1, 112500000, 0, 0, &plle_lock); + if (IS_ERR(hws[PLL_E_112P5])) + return PTR_ERR(hws[PLL_E_112P5]); + + /* PLL_F */ + hws[PLL_F] =3D sp_pll_register(dev, "pllf", &pd_ext, PLLF_CTL, + 0, 10, 13500000, 1, 4, &pllf_lock); + if (IS_ERR(hws[PLL_F])) + return PTR_ERR(hws[PLL_F]); + + /* PLL_TV */ + hws[PLL_TV] =3D sp_pll_register(dev, "plltv", &pd_ext, PLLTV_CTL, + 0, 15, 27000000, 0, DIV_TV, &plltv_lock); + if (IS_ERR(hws[PLL_TV])) + return PTR_ERR(hws[PLL_TV]); + hws[PLL_TV_A] =3D devm_clk_hw_register_divider(dev, "plltv_a", "plltv", 0, + PLLTV_CTL + 4, 5, 1, + CLK_DIVIDER_POWER_OF_TWO, + &plltv_lock); + if (IS_ERR(hws[PLL_TV_A])) + return PTR_ERR(hws[PLL_TV_A]); + dbg_clk(hws[PLL_TV_A]); + + /* PLL_SYS */ + hws[PLL_SYS] =3D sp_pll_register(dev, "pllsys", &pd_ext, PLLSYS_CTL, + 10, 9, 13500000, 0, 4, &pllsys_lock); + if (IS_ERR(hws[PLL_SYS])) + return PTR_ERR(hws[PLL_SYS]); + pd_sys.hw =3D hws[PLL_SYS]; + + /* gates */ + for (i =3D 0; i < ARRAY_SIZE(sp_clk_gates); i++) { + char name[10]; + u32 f =3D sp_clk_gates[i]; + int j =3D f & 0xffff; + struct clk_parent_data *pd =3D (f & F_EXTCLK) ? &pd_ext : &pd_sys; + + sprintf(name, "%02d_0x%02x", i, j); + hws[i] =3D clk_hw_register_gate_parent_data(dev, name, pd, 0, + clk_regs + (j >> 4) * 4, + j & 0x0f, + CLK_GATE_HIWORD_MASK, + NULL); + if (IS_ERR(hws[i])) + return PTR_ERR(hws[i]); + dbg_clk(hws[i]); + } + + sp_clk_data->num =3D CLK_MAX; + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, sp_clk_dat= a); +} + +static const struct of_device_id sp7021_clk_dt_ids[] =3D { + { .compatible =3D "sunplus,sp7021-clkc", }, + { } +}; + +static struct platform_driver sp7021_clk_driver =3D { + .probe =3D sp7021_clk_probe, + .driver =3D { + .name =3D "sp7021-clk", + .of_match_table =3D sp7021_clk_dt_ids, + }, +}; +module_platform_driver(sp7021_clk_driver); + +MODULE_AUTHOR("Sunplus Technology"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Clock driver for Sunplus SP7021 SoC"); --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD86CC433F5 for ; Fri, 6 May 2022 03:31:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388650AbiEFDen (ORCPT ); Thu, 5 May 2022 23:34:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388597AbiEFDeF (ORCPT ); Thu, 5 May 2022 23:34:05 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 54D27D74 for ; Thu, 5 May 2022 20:30:14 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:29 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian , Rob Herring Subject: [PATCH v14 6/9] dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller Date: Fri, 6 May 2022 11:23:20 +0800 Message-Id: <56fb5e9a35a901f15d8e9721385c7e916c181377.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation to describe Sunplus SP7021 interrupt controller bindings. Reviewed-by: Rob Herring Signed-off-by: Qin Jian --- .../sunplus,sp7021-intc.yaml | 62 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= sunplus,sp7021-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sunplus= ,sp7021-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= sunplus,sp7021-intc.yaml new file mode 100644 index 000000000..f26d8b213 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021= -intc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. 2021 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-int= c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 SoC Interrupt Controller Device Tree Bindings + +maintainers: + - Qin Jian + +properties: + compatible: + items: + - const: sunplus,sp7021-intc + + reg: + maxItems: 2 + description: + Specifies base physical address(s) and size of the controller regs. + The 1st region include type/polarity/priority/mask regs. + The 2nd region include clear/masked_ext0/masked_ext1/group regs. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + The first cell is the IRQ number, the second cell is the trigger + type as defined in interrupt.txt in this directory. + + interrupts: + maxItems: 2 + description: + EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt + controller. + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - interrupts + +additionalProperties: false + +examples: + - | + #include + + intc: interrupt-controller@9c000780 { + compatible =3D "sunplus,sp7021-intc"; + reg =3D <0x9c000780 0x80>, <0x9c000a80 0x80>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupt-parent =3D <&gic>; + interrupts =3D , /* EXT_INT0 */ + ; /* EXT_INT1 */ + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 8b77f7ae4..9fba67159 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2745,6 +2745,7 @@ S: Maintained W: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview F: Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-i= ntc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c F: drivers/reset/reset-sunplus.c --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AF84C433EF for ; Fri, 6 May 2022 03:31:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388664AbiEFDe5 (ORCPT ); Thu, 5 May 2022 23:34:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388606AbiEFDeK (ORCPT ); Thu, 5 May 2022 23:34:10 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3B7E8644FC for ; Thu, 5 May 2022 20:30:07 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:29 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 7/9] irqchip: Add Sunplus SP7021 interrupt controller driver Date: Fri, 6 May 2022 11:23:21 +0800 Message-Id: <7e469fb049959f88cf2b37649e6f3eb1d0fd3440.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add interrupt controller driver for Sunplus SP7021 SoC. This is the interrupt controller in P-chip which collects all interrupt sources in P-chip and routes them to parent interrupt controller in C-chip. Signed-off-by: Qin Jian Acked-by: Marc Zyngier Reported-by: kernel test robot --- MAINTAINERS | 1 + drivers/irqchip/Kconfig | 9 + drivers/irqchip/Makefile | 2 + drivers/irqchip/irq-sp7021-intc.c | 278 ++++++++++++++++++++++++++++++ 4 files changed, 290 insertions(+) create mode 100644 drivers/irqchip/irq-sp7021-intc.c diff --git a/MAINTAINERS b/MAINTAINERS index 9fba67159..cf6873295 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2748,6 +2748,7 @@ F: Documentation/devicetree/bindings/clock/sunplus,sp= 7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-i= ntc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml F: drivers/clk/clk-sp7021.c +F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c F: include/dt-bindings/clock/sp-sp7021.h F: include/dt-bindings/reset/sp-sp7021.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 7038957f4..f5c2596bc 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -617,4 +617,13 @@ config MCHP_EIC help Support for Microchip External Interrupt Controller. =20 +config SUNPLUS_SP7021_INTC + bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST + default SOC_SP7021 + help + Support for the Sunplus SP7021 Interrupt Controller IP core. + SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a + chained controller, routing all interrupt source in P-Chip to + the primary controller on C-Chip. + endmenu diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index c1f611cbf..eb0ac83ff 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -117,3 +117,5 @@ obj-$(CONFIG_WPCM450_AIC) +=3D irq-wpcm450-aic.o obj-$(CONFIG_IRQ_IDT3243X) +=3D irq-idt3243x.o obj-$(CONFIG_APPLE_AIC) +=3D irq-apple-aic.o obj-$(CONFIG_MCHP_EIC) +=3D irq-mchp-eic.o +obj-$(CONFIG_SUNPLUS_SP7021_INTC) +=3D irq-sp7021-intc.o + diff --git a/drivers/irqchip/irq-sp7021-intc.c b/drivers/irqchip/irq-sp7021= -intc.c new file mode 100644 index 000000000..b45c1a601 --- /dev/null +++ b/drivers/irqchip/irq-sp7021-intc.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include + +#define SP_INTC_HWIRQ_MIN 0 +#define SP_INTC_HWIRQ_MAX 223 + +#define SP_INTC_NR_IRQS (SP_INTC_HWIRQ_MAX - SP_INTC_HWIRQ_MIN + 1) +#define SP_INTC_NR_GROUPS DIV_ROUND_UP(SP_INTC_NR_IRQS, 32) +#define SP_INTC_REG_SIZE (SP_INTC_NR_GROUPS * 4) + +/* REG_GROUP_0 regs */ +#define REG_INTR_TYPE (sp_intc.g0) +#define REG_INTR_POLARITY (REG_INTR_TYPE + SP_INTC_REG_SIZE) +#define REG_INTR_PRIORITY (REG_INTR_POLARITY + SP_INTC_REG_SIZE) +#define REG_INTR_MASK (REG_INTR_PRIORITY + SP_INTC_REG_SIZE) + +/* REG_GROUP_1 regs */ +#define REG_INTR_CLEAR (sp_intc.g1) +#define REG_MASKED_EXT1 (REG_INTR_CLEAR + SP_INTC_REG_SIZE) +#define REG_MASKED_EXT0 (REG_MASKED_EXT1 + SP_INTC_REG_SIZE) +#define REG_INTR_GROUP (REG_INTR_CLEAR + 31 * 4) + +#define GROUP_MASK (BIT(SP_INTC_NR_GROUPS) - 1) +#define GROUP_SHIFT_EXT1 (0) +#define GROUP_SHIFT_EXT0 (8) + +/* + * When GPIO_INT0~7 set to edge trigger, doesn't work properly. + * WORKAROUND: change it to level trigger, and toggle the polarity + * at ACK/Handler to make the HW work. + */ +#define GPIO_INT0_HWIRQ 120 +#define GPIO_INT7_HWIRQ 127 +#define IS_GPIO_INT(irq) \ +({ \ + u32 i =3D irq; \ + (i >=3D GPIO_INT0_HWIRQ) && (i <=3D GPIO_INT7_HWIRQ); \ +}) + +/* index of states */ +enum { + _IS_EDGE =3D 0, + _IS_LOW, + _IS_ACTIVE +}; + +#define STATE_BIT(irq, idx) (((irq) - GPIO_INT0_HWIRQ) * 3 + (idx)) +#define ASSIGN_STATE(irq, idx, v) assign_bit(STATE_BIT(irq, idx), sp_intc.= states, v) +#define TEST_STATE(irq, idx) test_bit(STATE_BIT(irq, idx), sp_intc.states) + +static struct sp_intctl { + /* + * REG_GROUP_0: include type/polarity/priority/mask regs. + * REG_GROUP_1: include clear/masked_ext0/masked_ext1/group regs. + */ + void __iomem *g0; // REG_GROUP_0 base + void __iomem *g1; // REG_GROUP_1 base + + struct irq_domain *domain; + raw_spinlock_t lock; + + /* + * store GPIO_INT states + * each interrupt has 3 states: is_edge, is_low, is_active + */ + DECLARE_BITMAP(states, (GPIO_INT7_HWIRQ - GPIO_INT0_HWIRQ + 1) * 3); +} sp_intc; + +static struct irq_chip sp_intc_chip; + +static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value) +{ + u32 offset, mask; + unsigned long flags; + void __iomem *reg; + + offset =3D (hwirq / 32) * 4; + reg =3D base + offset; + + raw_spin_lock_irqsave(&sp_intc.lock, flags); + mask =3D readl_relaxed(reg); + if (value) + mask |=3D BIT(hwirq % 32); + else + mask &=3D ~BIT(hwirq % 32); + writel_relaxed(mask, reg); + raw_spin_unlock_irqrestore(&sp_intc.lock, flags); +} + +static void sp_intc_ack_irq(struct irq_data *d) +{ + u32 hwirq =3D d->hwirq; + + if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WOR= KAROUND + sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW)= ); + ASSIGN_STATE(hwirq, _IS_ACTIVE, true); + } + + sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1); +} + +static void sp_intc_mask_irq(struct irq_data *d) +{ + sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0); +} + +static void sp_intc_unmask_irq(struct irq_data *d) +{ + sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 1); +} + +static int sp_intc_set_type(struct irq_data *d, unsigned int type) +{ + u32 hwirq =3D d->hwirq; + bool is_edge =3D !(type & IRQ_TYPE_LEVEL_MASK); + bool is_low =3D (type =3D=3D IRQ_TYPE_LEVEL_LOW || type =3D=3D IRQ_TYPE_E= DGE_FALLING); + + irq_set_handler_locked(d, is_edge ? handle_edge_irq : handle_level_irq); + + if (unlikely(IS_GPIO_INT(hwirq) && is_edge)) { // WORKAROUND + /* store states */ + ASSIGN_STATE(hwirq, _IS_EDGE, is_edge); + ASSIGN_STATE(hwirq, _IS_LOW, is_low); + ASSIGN_STATE(hwirq, _IS_ACTIVE, false); + /* change to level */ + is_edge =3D false; + } + + sp_intc_assign_bit(hwirq, REG_INTR_TYPE, is_edge); + sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, is_low); + + return 0; +} + +static int sp_intc_get_ext_irq(int ext_num) +{ + void __iomem *base =3D ext_num ? REG_MASKED_EXT1 : REG_MASKED_EXT0; + u32 shift =3D ext_num ? GROUP_SHIFT_EXT1 : GROUP_SHIFT_EXT0; + u32 groups; + u32 pending_group; + u32 group; + u32 pending_irq; + + groups =3D readl_relaxed(REG_INTR_GROUP); + pending_group =3D (groups >> shift) & GROUP_MASK; + if (!pending_group) + return -1; + + group =3D fls(pending_group) - 1; + pending_irq =3D readl_relaxed(base + group * 4); + if (!pending_irq) + return -1; + + return (group * 32) + fls(pending_irq) - 1; +} + +static void sp_intc_handle_ext_cascaded(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + int ext_num =3D (int)irq_desc_get_handler_data(desc); + int hwirq; + + chained_irq_enter(chip, desc); + + while ((hwirq =3D sp_intc_get_ext_irq(ext_num)) >=3D 0) { + if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // = WORKAROUND + ASSIGN_STATE(hwirq, _IS_ACTIVE, false); + sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW)= ); + } else { + generic_handle_domain_irq(sp_intc.domain, hwirq); + } + } + + chained_irq_exit(chip, desc); +} + +static struct irq_chip sp_intc_chip =3D { + .name =3D "sp_intc", + .irq_ack =3D sp_intc_ack_irq, + .irq_mask =3D sp_intc_mask_irq, + .irq_unmask =3D sp_intc_unmask_irq, + .irq_set_type =3D sp_intc_set_type, +}; + +static int sp_intc_irq_domain_map(struct irq_domain *domain, + unsigned int irq, irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &sp_intc_chip, handle_level_irq); + irq_set_chip_data(irq, &sp_intc_chip); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops sp_intc_dm_ops =3D { + .xlate =3D irq_domain_xlate_twocell, + .map =3D sp_intc_irq_domain_map, +}; + +static int sp_intc_irq_map(struct device_node *node, int i) +{ + unsigned int irq; + + irq =3D irq_of_parse_and_map(node, i); + if (!irq) + return -ENOENT; + + irq_set_chained_handler_and_data(irq, sp_intc_handle_ext_cascaded, (void = *)i); + + return 0; +} + +static int __init sp_intc_init_dt(struct device_node *node, struct device_= node *parent) +{ + int i, ret; + + sp_intc.g0 =3D of_iomap(node, 0); + if (!sp_intc.g0) + return -ENXIO; + + sp_intc.g1 =3D of_iomap(node, 1); + if (!sp_intc.g1) { + ret =3D -ENXIO; + goto out_unmap0; + } + + ret =3D sp_intc_irq_map(node, 0); // EXT_INT0 + if (ret) + goto out_unmap1; + + ret =3D sp_intc_irq_map(node, 1); // EXT_INT1 + if (ret) + goto out_unmap1; + + /* initial regs */ + for (i =3D 0; i < SP_INTC_NR_GROUPS; i++) { + /* all mask */ + writel_relaxed(0, REG_INTR_MASK + i * 4); + /* all edge */ + writel_relaxed(~0, REG_INTR_TYPE + i * 4); + /* all high-active */ + writel_relaxed(0, REG_INTR_POLARITY + i * 4); + /* all EXT_INT0 */ + writel_relaxed(~0, REG_INTR_PRIORITY + i * 4); + /* all clear */ + writel_relaxed(~0, REG_INTR_CLEAR + i * 4); + } + + sp_intc.domain =3D irq_domain_add_linear(node, SP_INTC_NR_IRQS, + &sp_intc_dm_ops, &sp_intc); + if (!sp_intc.domain) { + ret =3D -ENOMEM; + goto out_unmap1; + } + + raw_spin_lock_init(&sp_intc.lock); + + return 0; + +out_unmap1: + iounmap(sp_intc.g1); +out_unmap0: + iounmap(sp_intc.g0); + + return ret; +} + +IRQCHIP_DECLARE(sp_intc, "sunplus,sp7021-intc", sp_intc_init_dt); --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED2E6C433EF for ; Fri, 6 May 2022 03:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1388632AbiEFDeh (ORCPT ); Thu, 5 May 2022 23:34:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388586AbiEFDd5 (ORCPT ); Thu, 5 May 2022 23:33:57 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id C72D7644E9 for ; Thu, 5 May 2022 20:30:06 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:29 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 8/9] ARM: sunplus: Add initial support for Sunplus SP7021 SoC Date: Fri, 6 May 2022 11:23:22 +0800 Message-Id: X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch aims to add an initial support for Sunplus SP7021 SoC. Reviewed-by: Arnd Bergmann Signed-off-by: Qin Jian Reported-by: kernel test robot --- MAINTAINERS | 1 + arch/arm/Kconfig | 2 ++ arch/arm/Makefile | 1 + arch/arm/mach-sunplus/Kconfig | 27 +++++++++++++++++++++++++++ arch/arm/mach-sunplus/Makefile | 9 +++++++++ arch/arm/mach-sunplus/sp7021.c | 16 ++++++++++++++++ 6 files changed, 56 insertions(+) create mode 100644 arch/arm/mach-sunplus/Kconfig create mode 100644 arch/arm/mach-sunplus/Makefile create mode 100644 arch/arm/mach-sunplus/sp7021.c diff --git a/MAINTAINERS b/MAINTAINERS index cf6873295..38890c055 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2747,6 +2747,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp70= 21.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-i= ntc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c F: drivers/irqchip/irq-sp7021-intc.c F: drivers/reset/reset-sunplus.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4c97cb40e..1ee9a27a3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -693,6 +693,8 @@ source "arch/arm/mach-sti/Kconfig" =20 source "arch/arm/mach-stm32/Kconfig" =20 +source "arch/arm/mach-sunplus/Kconfig" + source "arch/arm/mach-sunxi/Kconfig" =20 source "arch/arm/mach-tegra/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 77172d555..1e19d2f4b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -216,6 +216,7 @@ machine-$(CONFIG_ARCH_RENESAS) +=3D shmobile machine-$(CONFIG_ARCH_INTEL_SOCFPGA) +=3D socfpga machine-$(CONFIG_ARCH_STI) +=3D sti machine-$(CONFIG_ARCH_STM32) +=3D stm32 +machine-$(CONFIG_ARCH_SUNPLUS) +=3D sunplus machine-$(CONFIG_ARCH_SUNXI) +=3D sunxi machine-$(CONFIG_ARCH_TEGRA) +=3D tegra machine-$(CONFIG_ARCH_U8500) +=3D ux500 diff --git a/arch/arm/mach-sunplus/Kconfig b/arch/arm/mach-sunplus/Kconfig new file mode 100644 index 000000000..be20425c2 --- /dev/null +++ b/arch/arm/mach-sunplus/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +menuconfig ARCH_SUNPLUS + bool "Sunplus SoCs" + depends on ARCH_MULTI_V7 + help + Support for Sunplus SoC family: SP7021 and succeeding SoC-based systems, + such as the Banana Pi BPI-F2S development board (and derivatives). + () + () + +config SOC_SP7021 + bool "Sunplus SP7021 SoC support" + depends on ARCH_SUNPLUS + default ARCH_SUNPLUS + select HAVE_ARM_ARCH_TIMER + select ARM_GIC + select ARM_PSCI + select PINCTRL + select PINCTRL_SPPCTL + select SERIAL_SUNPLUS + select SERIAL_SUNPLUS_CONSOLE + help + Support for Sunplus SP7021 SoC. It is based on ARM 4-core + Cortex-A7 with various peripherals (ex: I2C, SPI, SDIO, + Ethernet and etc.), FPGA interface, chip-to-chip bus. + It is designed for industrial control. diff --git a/arch/arm/mach-sunplus/Makefile b/arch/arm/mach-sunplus/Makefile new file mode 100644 index 000000000..c902580a7 --- /dev/null +++ b/arch/arm/mach-sunplus/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the linux kernel. +# + +# Object file lists. + +obj-$(CONFIG_SOC_SP7021) +=3D sp7021.o + diff --git a/arch/arm/mach-sunplus/sp7021.c b/arch/arm/mach-sunplus/sp7021.c new file mode 100644 index 000000000..774d0a5bd --- /dev/null +++ b/arch/arm/mach-sunplus/sp7021.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (C) Sunplus Technology Co., Ltd. + * All rights reserved. + */ +#include +#include + +static const char *sp7021_compat[] __initconst =3D { + "sunplus,sp7021", + NULL +}; + +DT_MACHINE_START(SP7021_DT, "SP7021") + .dt_compat =3D sp7021_compat, +MACHINE_END --=20 2.33.1 From nobody Fri May 8 09:13:17 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE93CC433F5 for ; Fri, 6 May 2022 03:31:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352199AbiEFDfC (ORCPT ); Thu, 5 May 2022 23:35:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388608AbiEFDeL (ORCPT ); Thu, 5 May 2022 23:34:11 -0400 Received: from mx1.cqplus1.com (unknown [113.204.237.245]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2BD78644F9 for ; Thu, 5 May 2022 20:30:06 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 172.28.114.216 by mx1.cqplus1.com with MailGates ESMTP Server V5.0(24048:0:AUTH_RELAY) (envelope-from ); Fri, 06 May 2022 11:23:29 +0800 (CST) From: Qin Jian To: krzysztof.kozlowski@linaro.org Cc: robh+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, tglx@linutronix.de, maz@kernel.org, p.zabel@pengutronix.de, linux@armlinux.org.uk, arnd@arndb.de, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Qin Jian Subject: [PATCH v14 9/9] ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig Date: Fri, 6 May 2022 11:23:23 +0800 Message-Id: <594b7258f2e6bd7a23473732699155dd4662f2dc.1651805790.git.qinjian@cqplus1.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add generic Sunplus SP7021 based board defconfig Signed-off-by: Qin Jian --- MAINTAINERS | 1 + arch/arm/configs/multi_v7_defconfig | 1 + arch/arm/configs/sp7021_defconfig | 59 +++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 arch/arm/configs/sp7021_defconfig diff --git a/MAINTAINERS b/MAINTAINERS index 38890c055..93f4de6c1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2747,6 +2747,7 @@ F: Documentation/devicetree/bindings/arm/sunplus,sp70= 21.yaml F: Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml F: Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-i= ntc.yaml F: Documentation/devicetree/bindings/reset/sunplus,reset.yaml +F: arch/arm/configs/sp7021_*defconfig F: arch/arm/mach-sunplus/ F: drivers/clk/clk-sp7021.c F: drivers/irqchip/irq-sp7021-intc.c diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v= 7_defconfig index 8863fa969..a3bd9dbd8 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -86,6 +86,7 @@ CONFIG_MACH_SPEAR1310=3Dy CONFIG_MACH_SPEAR1340=3Dy CONFIG_ARCH_STI=3Dy CONFIG_ARCH_STM32=3Dy +CONFIG_ARCH_SUNPLUS=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_TEGRA=3Dy CONFIG_ARCH_UNIPHIER=3Dy diff --git a/arch/arm/configs/sp7021_defconfig b/arch/arm/configs/sp7021_de= fconfig new file mode 100644 index 000000000..703b9aaa4 --- /dev/null +++ b/arch/arm/configs/sp7021_defconfig @@ -0,0 +1,59 @@ +CONFIG_SYSVIPC=3Dy +CONFIG_NO_HZ_IDLE=3Dy +CONFIG_HIGH_RES_TIMERS=3Dy +CONFIG_PREEMPT=3Dy +CONFIG_IKCONFIG=3Dy +CONFIG_IKCONFIG_PROC=3Dy +CONFIG_LOG_BUF_SHIFT=3D14 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=3Dy +CONFIG_PERF_EVENTS=3Dy +CONFIG_SLAB=3Dy +CONFIG_ARCH_SUNPLUS=3Dy +# CONFIG_VDSO is not set +CONFIG_SMP=3Dy +CONFIG_THUMB2_KERNEL=3Dy +CONFIG_FORCE_MAX_ZONEORDER=3D12 +CONFIG_VFP=3Dy +CONFIG_NEON=3Dy +CONFIG_MODULES=3Dy +CONFIG_MODULE_UNLOAD=3Dy +CONFIG_MODVERSIONS=3Dy +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_UEVENT_HELPER=3Dy +CONFIG_UEVENT_HELPER_PATH=3D"/sbin/hotplug" +CONFIG_DEVTMPFS=3Dy +CONFIG_DEVTMPFS_MOUNT=3Dy +CONFIG_BLK_DEV_LOOP=3Dy +CONFIG_INPUT_SPARSEKMAP=3Dy +CONFIG_INPUT_EVDEV=3Dy +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_HWMON is not set +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=3Dy +CONFIG_EXT4_FS=3Dy +# CONFIG_DNOTIFY is not set +CONFIG_FANOTIFY=3Dy +CONFIG_VFAT_FS=3Dy +CONFIG_FAT_DEFAULT_IOCHARSET=3D"utf8" +CONFIG_EXFAT_FS=3Dy +CONFIG_TMPFS=3Dy +CONFIG_TMPFS_POSIX_ACL=3Dy +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=3Dy +CONFIG_NLS_ASCII=3Dy +CONFIG_NLS_ISO8859_1=3Dy +CONFIG_NLS_UTF8=3Dy +CONFIG_PRINTK_TIME=3Dy +CONFIG_DYNAMIC_DEBUG=3Dy +CONFIG_MAGIC_SYSRQ=3Dy +CONFIG_DEBUG_FS=3Dy +CONFIG_DEBUG_USER=3Dy --=20 2.33.1