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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id i10sm5266634pjd.2.2022.02.06.22.30.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 22:30:50 -0800 (PST) From: Zong Li To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, krzysztof.kozlowski@canonical.com, conor.dooley@microchip.com, geert@linux-m68k.org, bin.meng@windriver.com, green.wan@sifive.com, vkoul@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v5 1/3] dt-bindings: Add dma-channels property and modify compatible Date: Mon, 7 Feb 2022 14:30:38 +0800 Message-Id: <30430019105af445d52b7a48331c106f8e6d6816.1644215230.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dma-channels property, then we can determine how many channels there by device tree, rather than statically defining it in PDMA driver. In addition, we also modify the compatible for PDMA versioning scheme. Signed-off-by: Zong Li Suggested-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Reviewed-by: Palmer Dabbelt Reviewed-by: Rob Herring --- .../bindings/dma/sifive,fu540-c000-pdma.yaml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.y= aml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index 75ad898c59bc..92f410f54d72 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -25,7 +25,15 @@ description: | properties: compatible: items: - - const: sifive,fu540-c000-pdma + - enum: + - sifive,fu540-c000-pdma + - const: sifive,pdma0 + description: + Should be "sifive,-pdma" and "sifive,pdma". + Supported compatible strings are - + "sifive,fu540-c000-pdma" for the SiFive PDMA v0 as integrated onto t= he + SiFive FU540 chip resp and "sifive,pdma0" for the SiFive PDMA v0 IP = block + with no chip integration tweaks. =20 reg: maxItems: 1 @@ -34,6 +42,12 @@ properties: minItems: 1 maxItems: 8 =20 + dma-channels: + description: For backwards-compatibility, the default value is 4 + minimum: 1 + maximum: 4 + default: 4 + '#dma-cells': const: 1 =20 @@ -48,8 +62,9 @@ additionalProperties: false examples: - | dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; + compatible =3D "sifive,fu540-c000-pdma", "sifive,pdma0"; reg =3D <0x3000000 0x8000>; + dma-channels =3D <4>; interrupts =3D <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; #dma-cells =3D <1>; }; --=20 2.31.1 From nobody Mon Jun 29 16:42:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 523A0C4167D for ; Mon, 7 Feb 2022 06:41:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351932AbiBGGhM (ORCPT ); Mon, 7 Feb 2022 01:37:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234073AbiBGGbR (ORCPT ); Mon, 7 Feb 2022 01:31:17 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45E2DC0401C1 for ; Sun, 6 Feb 2022 22:30:54 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id x3so10414406pll.3 for ; Sun, 06 Feb 2022 22:30:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O3fmm4nvalmQleWa1byPzKYwRMYCW7Pxtk8Gk5epwAE=; b=Mev+fmMrEndOiPaIwMiostWKbCgoFUolVWzZCS5uUOeb6YzZKZEj6A9J+rHrqQqR1b FfCWf6jS25cRBOHFXTGitsymEc26oKLYlLLr4D4R0sNOup6+y6vzmEnPUbVKelaVdhFg F03jL7I3xrKN6prjd7rT616gqxvZcctqtMaWnyXsuQNlrEkD/GbYCOXrEZfqeuDGJh9+ oFz365NpbqYAz4kSJOv6L1wQBP8D7yXOe8Unverh0JpEvOQvoMIA0+i3rH4v57fyrLOf Ps15s79JTNhaF4VRgNZYkbR6r0o9WR6DTFOTFXw3AqgmOZarWyVpad9aRR1sKCPoxEUM CLaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O3fmm4nvalmQleWa1byPzKYwRMYCW7Pxtk8Gk5epwAE=; b=ggh+dCZCWyZBKYV1F2xNPqBBLdj+i0CKLwZiEZCWae0CjcsWcK2Be5j7WoiXQ2WK1P KbvpaAhsu+hq5r5b52frUIRAWMGXttxfcZhTEl2HYCyrTgnwQMpNG8p8Ejj3mahuguAv /yiV4mGG3xzRmw8E6RxUSkIi3ggVGpBr3sOegy9LYA7oWbPHhsdtd0pUOHXX5TezG1lf 1udNrtYN6WpBUcxaiFAbDI/hALj/NabQS6ggBSbCwD/Rg8JTCz/HPgU2W4iv4UuxCD2X SVNSjgtOJdhYvY+cmbzwmvLmFVOCAh9ovUCqj9wnE7NBcM+xttGksBWBbhwk9MkTvaYg b2+w== X-Gm-Message-State: AOAM533kATqPW+aSXKWSiATHMUam1QUpdHo3bQlXHEPnd+kQVECoBu53 E3sWQknyj/dfFvG+KcooWkOw9g== X-Google-Smtp-Source: ABdhPJz8oBJ3w7oZV38zeOV4odPSlf2oJfYGXKEsseSqcLYbDUnaotjNjwPZV1gk/z/pgQvbgRWgyg== X-Received: by 2002:a17:90a:5a01:: with SMTP id b1mr7252147pjd.134.1644215453808; Sun, 06 Feb 2022 22:30:53 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id i10sm5266634pjd.2.2022.02.06.22.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 22:30:53 -0800 (PST) From: Zong Li To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, krzysztof.kozlowski@canonical.com, conor.dooley@microchip.com, geert@linux-m68k.org, bin.meng@windriver.com, green.wan@sifive.com, vkoul@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Zong Li , Palmer Dabbelt Subject: [PATCH v5 2/3] riscv: dts: Add dma-channels property and modify compatible Date: Mon, 7 Feb 2022 14:30:39 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add dma-channels property, then we can determine how many channels there by device tree, in addition, we add the pdma versioning scheme for compatible. Signed-off-by: Zong Li Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Acked-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ++- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv= /boot/dts/microchip/microchip-mpfs.dtsi index 869aaf0d5c06..d8869ec99945 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -187,11 +187,12 @@ plic: interrupt-controller@c000000 { }; =20 dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; + compatible =3D "sifive,fu540-c000-pdma", "sifive,pdma0"; reg =3D <0x0 0x3000000 0x0 0x8000>; interrupt-parent =3D <&plic>; interrupts =3D <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; + dma-channels =3D <4>; #dma-cells =3D <1>; }; =20 diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/d= ts/sifive/fu540-c000.dtsi index 3eef52b1a59b..6a3011180846 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -168,11 +168,12 @@ uart0: serial@10010000 { status =3D "disabled"; }; dma: dma@3000000 { - compatible =3D "sifive,fu540-c000-pdma"; + compatible =3D "sifive,fu540-c000-pdma", "sifive,pdma0"; reg =3D <0x0 0x3000000 0x0 0x8000>; interrupt-parent =3D <&plic0>; interrupts =3D <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>; + dma-channels =3D <4>; #dma-cells =3D <1>; }; uart1: serial@10011000 { --=20 2.31.1 From nobody Mon Jun 29 16:42:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97781C433EF for ; Mon, 7 Feb 2022 06:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346015AbiBGGgm (ORCPT ); Mon, 7 Feb 2022 01:36:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236921AbiBGGbR (ORCPT ); Mon, 7 Feb 2022 01:31:17 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2823C0401C4 for ; Sun, 6 Feb 2022 22:30:57 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id 192so11310127pfz.3 for ; Sun, 06 Feb 2022 22:30:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NsFZzRzWxi9SLwITfrc8E6h9ajUabmlo1GhXmJ+C3hc=; b=WAlvS5EXiVRFIZe8CQYOYmWuBeX252Ah939fQC4xFyJiOgiQOqKLCEZ9w/rsR6+gi6 9ofS/fBv7QwPpn/VyFviNxUjm4OSgt5WaUQ38ohiXY8yU3zjlUJ1Yvbtqkq/Q0hEdem+ vOL4LBrdoiDalFZWuSYY69OLG3uLZfb1ktFR1Bo8AZaDqbbY/rsgggVvLIGRaCKEw8tO M6ffn1560ArOL3Xpl5xg0EVvQnm6FsEePBN54U5qe7xAaGTB4ob9FbVdBbdf9fWl+Xe5 0rS+pkIIUcoKVFmz3iMt4cxeBgkdGefflHbs0Y4BJCec9H7Tu+D3zt+hkDIKrAumXmsr epUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NsFZzRzWxi9SLwITfrc8E6h9ajUabmlo1GhXmJ+C3hc=; b=PRF7ct7NG5lCPM+xysCnRRIbpO+oGvJbPg8UM2MhAp/P0UPeObZBUasXAaoScvCIk1 4XQKj8BMMNzy3AeV70irZnToSrS12dQIrtvebTVLGblhHBD90s+qPz7G4qcAzxn4sH8k xBaux4hJ69xfvB9ZA4EElH+lJc9JsoUbHPJd2FEjjYN8nfq2+ASLgzuMQ4eCtoFcPUPs Nwr1wgqFXK3R3daKWY/P/nscNrjqKkPM+yeyUEu/jhW8JLFYdRjeikJc5afVH/TOSJDk 4nAGGuiEBMnpeju1YLv1J9ODMI2Are/pEsPHQ8NpCJnHkHdA0kM09ccE80DvvctbxJXe 3pow== X-Gm-Message-State: AOAM531zyXz0cmySvvK2r/3k5z9vDd+77AxfjzbSrd78bNQ2czcZZrif R61xjk4Sx6onxPDraFWQL87ywA== X-Google-Smtp-Source: ABdhPJztzK0ckN9GMQ0TxEmrpCSlWLQmxoXoG9PxqUVTiaqQJQd7I9kf9tGQI9fcbpFkt9zsEeErKA== X-Received: by 2002:aa7:84d5:: with SMTP id x21mr14270143pfn.72.1644215456964; Sun, 06 Feb 2022 22:30:56 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id i10sm5266634pjd.2.2022.02.06.22.30.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 22:30:56 -0800 (PST) From: Zong Li To: robh+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, krzysztof.kozlowski@canonical.com, conor.dooley@microchip.com, geert@linux-m68k.org, bin.meng@windriver.com, green.wan@sifive.com, vkoul@kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Zong Li Subject: [PATCH v5 3/3] dmaengine: sf-pdma: Get number of channel by device tree Date: Mon, 7 Feb 2022 14:30:40 +0800 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It currently assumes that there are always four channels, it would cause the error if there is actually less than four channels. Change that by getting number of channel from device tree. For backwards-compatibility, it uses the default value (i.e. 4) when there is no 'dma-channels' information in dts. Signed-off-by: Zong Li --- drivers/dma/sf-pdma/sf-pdma.c | 21 ++++++++++++++------- drivers/dma/sf-pdma/sf-pdma.h | 8 ++------ 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index f12606aeff87..2ae10b61dfa1 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -482,9 +482,7 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma) static int sf_pdma_probe(struct platform_device *pdev) { struct sf_pdma *pdma; - struct sf_pdma_chan *chan; struct resource *res; - int len, chans; int ret; const enum dma_slave_buswidth widths =3D DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | @@ -492,13 +490,21 @@ static int sf_pdma_probe(struct platform_device *pdev) DMA_SLAVE_BUSWIDTH_16_BYTES | DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES; =20 - chans =3D PDMA_NR_CH; - len =3D sizeof(*pdma) + sizeof(*chan) * chans; - pdma =3D devm_kzalloc(&pdev->dev, len, GFP_KERNEL); + pdma =3D devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL); if (!pdma) return -ENOMEM; =20 - pdma->n_chans =3D chans; + ret =3D of_property_read_u32(pdev->dev.of_node, "dma-channels", + &pdma->n_chans); + if (ret) { + dev_notice(&pdev->dev, "set number of channels to default value: 4\n"); + pdma->n_chans =3D PDMA_MAX_NR_CH; + } + + if (pdma->n_chans > PDMA_MAX_NR_CH) { + dev_err(&pdev->dev, "the number of channels exceeds the maximum\n"); + return -EINVAL; + } =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); pdma->membase =3D devm_ioremap_resource(&pdev->dev, res); @@ -556,7 +562,7 @@ static int sf_pdma_remove(struct platform_device *pdev) struct sf_pdma_chan *ch; int i; =20 - for (i =3D 0; i < PDMA_NR_CH; i++) { + for (i =3D 0; i < pdma->n_chans; i++) { ch =3D &pdma->chans[i]; =20 devm_free_irq(&pdev->dev, ch->txirq, ch); @@ -574,6 +580,7 @@ static int sf_pdma_remove(struct platform_device *pdev) =20 static const struct of_device_id sf_pdma_dt_ids[] =3D { { .compatible =3D "sifive,fu540-c000-pdma" }, + { .compatible =3D "sifive,pdma0" }, {}, }; MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids); diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h index 0c20167b097d..8127d792f639 100644 --- a/drivers/dma/sf-pdma/sf-pdma.h +++ b/drivers/dma/sf-pdma/sf-pdma.h @@ -22,11 +22,7 @@ #include "../dmaengine.h" #include "../virt-dma.h" =20 -#define PDMA_NR_CH 4 - -#if (PDMA_NR_CH !=3D 4) -#error "Please define PDMA_NR_CH to 4" -#endif +#define PDMA_MAX_NR_CH 4 =20 #define PDMA_BASE_ADDR 0x3000000 #define PDMA_CHAN_OFFSET 0x1000 @@ -118,7 +114,7 @@ struct sf_pdma { void __iomem *membase; void __iomem *mappedbase; u32 n_chans; - struct sf_pdma_chan chans[PDMA_NR_CH]; + struct sf_pdma_chan chans[PDMA_MAX_NR_CH]; }; =20 #endif /* _SF_PDMA_H */ --=20 2.31.1