From nobody Tue Jun 30 09:57:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45362C433EF for ; Wed, 19 Jan 2022 09:29:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353128AbiASJ3A (ORCPT ); Wed, 19 Jan 2022 04:29:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353091AbiASJ2u (ORCPT ); Wed, 19 Jan 2022 04:28:50 -0500 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EC60C06161C for ; Wed, 19 Jan 2022 01:28:49 -0800 (PST) Received: by mail-pg1-x534.google.com with SMTP id x83so1893926pgx.4 for ; Wed, 19 Jan 2022 01:28:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AEMYWaSEel8Cp4M82ZW85fUPHW8FXC9jvw93/++Wovk=; b=ezn/qJM7sxbIkM29eOAixvkIHUFcHSL+GXFG8F5i0B4NlzOAQ3nNurzh43WyO1Q8Z7 2LP/B9CWpDPCGL1iVN8vr+JpTwRbsSrbjWhwnflX34ph08iMbWRPaam63hSGgc7bA4OJ eDBMvjSoBo8kBDrtTEdy2inGeaFAWcKnty1zrhcpzbm9XBMsbWJYAePXr7f7bXYxN/gi ecSbdEpEelkaENONBeR7cBqwwyCkNtPOtBOC0MCfm1spfL78WRFd3EfMwvCaJ7/xCCFx /mfD+XvxvpRqyXWGmLHJYyoeU14XgF6uW+/YNMQTFYPXEL+dP+FfFOjeDsignik7Eo8e 6xCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AEMYWaSEel8Cp4M82ZW85fUPHW8FXC9jvw93/++Wovk=; b=yGyFqPhDZIcyvrl+r/Bozp5oXNrzVp/+n2W+3SV1BW0woZk5ZcdfsP5ouAo9Yh8S6z y1DIT4QCqxKNI4rkqHlacqnHUVgU3E0vxQrsg97J9tw80SO0SiN/XcrAmVV5abyOjkWz NyqzDQXf+Um74ujAIYBRNJzRgzAj2M8CVHi+oSO+1YZ07FtwQmng+/ylX3rVyeWQvqL0 CQu3dJ1Nq4vvmw5YKSfIF551MC9ZIbLwKmuCgq3iRjNYFq1n0b9g0n/6DCxyOXoJcBez C+NJZ2J8oKQdybjapz0KQktjmR2Rz8s2dv6qNlWR8+/ETG0G8+Ef/ZZCky5+cs05LzHg Jk4A== X-Gm-Message-State: AOAM530qv7LNB6F4TNoIDBcneYbMfq/FpiZq/EZhcUMH6UzKRVy/rlV8 e+ioy5uIMYVi9CSxkBcjOODk7Q== X-Google-Smtp-Source: ABdhPJyoYH6hpuE6wwoRFycNZ0mY/1V2rBlplF2VQiYHcx/nwAScjQ89HomKMDFJA0dt7UXy6/o71A== X-Received: by 2002:a65:690a:: with SMTP id s10mr23376522pgq.48.1642584529158; Wed, 19 Jan 2022 01:28:49 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id y8sm1415894pfl.207.2022.01.19.01.28.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jan 2022 01:28:48 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 1/4] dt-bindings: change the macro name of prci in header files and example Date: Wed, 19 Jan 2022 17:28:38 +0800 Message-Id: <81d9a152e65374117b633f953aa31f378412acb5.1642582832.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We currently change the macro name for fu540 and fu740 by adding the prefix respectively, the dt-bindings should be modified as well. Signed-off-by: Zong Li Acked-by: Palmer Dabbelt # aside from breaking bisect --- .../devicetree/bindings/gpio/sifive,gpio.yaml | 2 +- .../bindings/pci/sifive,fu740-pcie.yaml | 2 +- .../bindings/serial/sifive-serial.yaml | 2 +- include/dt-bindings/clock/sifive-fu540-prci.h | 8 ++++---- include/dt-bindings/clock/sifive-fu740-prci.h | 18 +++++++++--------- 5 files changed, 16 insertions(+), 16 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml b/Docu= mentation/devicetree/bindings/gpio/sifive,gpio.yaml index c2902aac2514..eaf3210fa90c 100644 --- a/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/sifive,gpio.yaml @@ -79,7 +79,7 @@ examples: interrupt-parent =3D <&plic>; interrupts =3D <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; reg =3D <0x10060000 0x1000>; - clocks =3D <&tlclk PRCI_CLK_TLCLK>; + clocks =3D <&tlclk FU540_PRCI_CLK_TLCLK>; gpio-controller; #gpio-cells =3D <2>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml b= /Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml index 2b9d1d6fc661..6e6860551d33 100644 --- a/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml @@ -105,7 +105,7 @@ examples: <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; clock-names =3D "pcie_aux"; - clocks =3D <&prci PRCI_CLK_PCIE_AUX>; + clocks =3D <&prci FU740_PRCI_CLK_PCIE_AUX>; resets =3D <&prci 4>; pwren-gpios =3D <&gpio 5 0>; reset-gpios =3D <&gpio 8 0>; diff --git a/Documentation/devicetree/bindings/serial/sifive-serial.yaml b/= Documentation/devicetree/bindings/serial/sifive-serial.yaml index 09aae43f65a7..b0a8871e3641 100644 --- a/Documentation/devicetree/bindings/serial/sifive-serial.yaml +++ b/Documentation/devicetree/bindings/serial/sifive-serial.yaml @@ -59,7 +59,7 @@ examples: interrupt-parent =3D <&plic0>; interrupts =3D <80>; reg =3D <0x10010000 0x1000>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; }; =20 ... diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bin= dings/clock/sifive-fu540-prci.h index 3b21d0522c91..5af372e8385f 100644 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ b/include/dt-bindings/clock/sifive-fu540-prci.h @@ -10,9 +10,9 @@ =20 /* Clock indexes for use by Device Tree data and the PRCI driver */ =20 -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 +#define FU540_PRCI_CLK_COREPLL 0 +#define FU540_PRCI_CLK_DDRPLL 1 +#define FU540_PRCI_CLK_GEMGXLPLL 2 +#define FU540_PRCI_CLK_TLCLK 3 =20 #endif diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bin= dings/clock/sifive-fu740-prci.h index 7899b7fee7db..672bdadbf6c0 100644 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ b/include/dt-bindings/clock/sifive-fu740-prci.h @@ -11,14 +11,14 @@ =20 /* Clock indexes for use by Device Tree data and the PRCI driver */ =20 -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_DVFSCOREPLL 3 -#define PRCI_CLK_HFPCLKPLL 4 -#define PRCI_CLK_CLTXPLL 5 -#define PRCI_CLK_TLCLK 6 -#define PRCI_CLK_PCLK 7 -#define PRCI_CLK_PCIE_AUX 8 +#define FU740_PRCI_CLK_COREPLL 0 +#define FU740_PRCI_CLK_DDRPLL 1 +#define FU740_PRCI_CLK_GEMGXLPLL 2 +#define FU740_PRCI_CLK_DVFSCOREPLL 3 +#define FU740_PRCI_CLK_HFPCLKPLL 4 +#define FU740_PRCI_CLK_CLTXPLL 5 +#define FU740_PRCI_CLK_TLCLK 6 +#define FU740_PRCI_CLK_PCLK 7 +#define FU740_PRCI_CLK_PCIE_AUX 8 =20 #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ --=20 2.31.1 From nobody Tue Jun 30 09:57:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAB5AC433FE for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y8sm1415894pfl.207.2022.01.19.01.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jan 2022 01:28:51 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 2/4] riscv: dts: Change the macro name of prci in each device node Date: Wed, 19 Jan 2022 17:28:39 +0800 Message-Id: <2a58807f83f24ee1a2707ed71244c7f52d2228e2.1642582832.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We currently change the macro name for fu540 and fu740 by adding the prefix respectively, these marcos are referenced by some device nodes, they should be modified as well. Signed-off-by: Zong Li Acked-by: Palmer Dabbelt # aside from breaking bisect --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 22 +++++++++--------- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 26 +++++++++++----------- 2 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/d= ts/sifive/fu540-c000.dtsi index 0655b5c4201d..2bb88e06e3e2 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -163,7 +163,7 @@ uart0: serial@10010000 { reg =3D <0x0 0x10010000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <4>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; status =3D "disabled"; }; dma: dma@3000000 { @@ -178,7 +178,7 @@ uart1: serial@10011000 { reg =3D <0x0 0x10011000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <5>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; status =3D "disabled"; }; i2c0: i2c@10030000 { @@ -186,7 +186,7 @@ i2c0: i2c@10030000 { reg =3D <0x0 0x10030000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <50>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; reg-shift =3D <2>; reg-io-width =3D <1>; #address-cells =3D <1>; @@ -199,7 +199,7 @@ qspi0: spi@10040000 { 0x0 0x20000000 0x0 0x10000000>; interrupt-parent =3D <&plic0>; interrupts =3D <51>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -210,7 +210,7 @@ qspi1: spi@10041000 { 0x0 0x30000000 0x0 0x10000000>; interrupt-parent =3D <&plic0>; interrupts =3D <52>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -220,7 +220,7 @@ qspi2: spi@10050000 { reg =3D <0x0 0x10050000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <6>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -233,8 +233,8 @@ eth0: ethernet@10090000 { 0x0 0x100a0000 0x0 0x1000>; local-mac-address =3D [00 00 00 00 00 00]; clock-names =3D "pclk", "hclk"; - clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; + clocks =3D <&prci FU540_PRCI_CLK_GEMGXLPLL>, + <&prci FU540_PRCI_CLK_GEMGXLPLL>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -244,7 +244,7 @@ pwm0: pwm@10020000 { reg =3D <0x0 0x10020000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <42 43 44 45>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; #pwm-cells =3D <3>; status =3D "disabled"; }; @@ -253,7 +253,7 @@ pwm1: pwm@10021000 { reg =3D <0x0 0x10021000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <46 47 48 49>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; #pwm-cells =3D <3>; status =3D "disabled"; }; @@ -279,7 +279,7 @@ gpio: gpio@10060000 { #gpio-cells =3D <2>; interrupt-controller; #interrupt-cells =3D <2>; - clocks =3D <&prci PRCI_CLK_TLCLK>; + clocks =3D <&prci FU540_PRCI_CLK_TLCLK>; status =3D "disabled"; }; }; diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/d= ts/sifive/fu740-c000.dtsi index abbb960f90a0..38fa29db8a90 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -166,7 +166,7 @@ uart0: serial@10010000 { reg =3D <0x0 0x10010000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <39>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; status =3D "disabled"; }; uart1: serial@10011000 { @@ -174,7 +174,7 @@ uart1: serial@10011000 { reg =3D <0x0 0x10011000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <40>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; status =3D "disabled"; }; i2c0: i2c@10030000 { @@ -182,7 +182,7 @@ i2c0: i2c@10030000 { reg =3D <0x0 0x10030000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <52>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; reg-shift =3D <2>; reg-io-width =3D <1>; #address-cells =3D <1>; @@ -194,7 +194,7 @@ i2c1: i2c@10031000 { reg =3D <0x0 0x10031000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <53>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; reg-shift =3D <2>; reg-io-width =3D <1>; #address-cells =3D <1>; @@ -207,7 +207,7 @@ qspi0: spi@10040000 { <0x0 0x20000000 0x0 0x10000000>; interrupt-parent =3D <&plic0>; interrupts =3D <41>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -218,7 +218,7 @@ qspi1: spi@10041000 { <0x0 0x30000000 0x0 0x10000000>; interrupt-parent =3D <&plic0>; interrupts =3D <42>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -228,7 +228,7 @@ spi0: spi@10050000 { reg =3D <0x0 0x10050000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <43>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -241,8 +241,8 @@ eth0: ethernet@10090000 { <0x0 0x100a0000 0x0 0x1000>; local-mac-address =3D [00 00 00 00 00 00]; clock-names =3D "pclk", "hclk"; - clocks =3D <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; + clocks =3D <&prci FU740_PRCI_CLK_GEMGXLPLL>, + <&prci FU740_PRCI_CLK_GEMGXLPLL>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; @@ -252,7 +252,7 @@ pwm0: pwm@10020000 { reg =3D <0x0 0x10020000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <44>, <45>, <46>, <47>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells =3D <3>; status =3D "disabled"; }; @@ -261,7 +261,7 @@ pwm1: pwm@10021000 { reg =3D <0x0 0x10021000 0x0 0x1000>; interrupt-parent =3D <&plic0>; interrupts =3D <48>, <49>, <50>, <51>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; #pwm-cells =3D <3>; status =3D "disabled"; }; @@ -287,7 +287,7 @@ gpio: gpio@10060000 { #gpio-cells =3D <2>; interrupt-controller; #interrupt-cells =3D <2>; - clocks =3D <&prci PRCI_CLK_PCLK>; + clocks =3D <&prci FU740_PRCI_CLK_PCLK>; status =3D "disabled"; }; pcie@e00000000 { @@ -316,7 +316,7 @@ pcie@e00000000 { <0x0 0x0 0x0 0x3 &plic0 59>, <0x0 0x0 0x0 0x4 &plic0 60>; clock-names =3D "pcie_aux"; - clocks =3D <&prci PRCI_CLK_PCIE_AUX>; + clocks =3D <&prci FU740_PRCI_CLK_PCIE_AUX>; pwren-gpios =3D <&gpio 5 0>; reset-gpios =3D <&gpio 8 0>; resets =3D <&prci 4>; --=20 2.31.1 From nobody Tue Jun 30 09:57:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3347C433F5 for ; Wed, 19 Jan 2022 09:29:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353170AbiASJ3K (ORCPT ); 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y8sm1415894pfl.207.2022.01.19.01.28.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jan 2022 01:28:53 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 3/4] clk: sifive: Add SoCs prefix in each SoCs-dependent data Date: Wed, 19 Jan 2022 17:28:40 +0800 Message-Id: <1c979637ffcb85f11e9dcb5c368e2f364cabfd11.1642582832.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch is prerequisite for moving SoCs C files into SoCs header files. Currently, fu540-prci.c and fu740-prci.c use same names for several macro definitions and variables, it would cause redefinition error when we trying to include all stuff in sifive-prci.c Signed-off-by: Zong Li Acked-by: Palmer Dabbelt # aside from breaking bisect --- drivers/clk/sifive/fu540-prci.c | 24 ++++++++--------- drivers/clk/sifive/fu740-prci.c | 46 ++++++++++++++++----------------- 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prc= i.c index 29bab915003c..d686f5cf3f71 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2018-2019 SiFive, Inc. + * Copyright (C) 2018-2021 SiFive, Inc. * Copyright (C) 2018-2019 Wesley Terpstra * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2021 Zong Li * * The FU540 PRCI implements clock and reset control for the SiFive * FU540-C000 chip. This driver assumes that it has sole control @@ -25,19 +25,19 @@ =20 /* PRCI integration data for each WRPLL instance */ =20 -static struct __prci_wrpll_data __prci_corepll_data =3D { +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data =3D { .cfg0_offs =3D PRCI_COREPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_COREPLLCFG1_OFFSET, .enable_bypass =3D sifive_prci_coreclksel_use_hfclk, .disable_bypass =3D sifive_prci_coreclksel_use_corepll, }; =20 -static struct __prci_wrpll_data __prci_ddrpll_data =3D { +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data =3D { .cfg0_offs =3D PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_DDRPLLCFG1_OFFSET, }; =20 -static struct __prci_wrpll_data __prci_gemgxlpll_data =3D { +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data =3D { .cfg0_offs =3D PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_GEMGXLPLLCFG1_OFFSET, }; @@ -63,25 +63,25 @@ static const struct clk_ops sifive_fu540_prci_tlclksel_= clk_ops =3D { =20 /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu540[] =3D { - [PRCI_CLK_COREPLL] =3D { + [FU540_PRCI_CLK_COREPLL] =3D { .name =3D "corepll", .parent_name =3D "hfclk", .ops =3D &sifive_fu540_prci_wrpll_clk_ops, - .pwd =3D &__prci_corepll_data, + .pwd =3D &sifive_fu540_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] =3D { + [FU540_PRCI_CLK_DDRPLL] =3D { .name =3D "ddrpll", .parent_name =3D "hfclk", .ops =3D &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd =3D &__prci_ddrpll_data, + .pwd =3D &sifive_fu540_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] =3D { + [FU540_PRCI_CLK_GEMGXLPLL] =3D { .name =3D "gemgxlpll", .parent_name =3D "hfclk", .ops =3D &sifive_fu540_prci_wrpll_clk_ops, - .pwd =3D &__prci_gemgxlpll_data, + .pwd =3D &sifive_fu540_prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] =3D { + [FU540_PRCI_CLK_TLCLK] =3D { .name =3D "tlclk", .parent_name =3D "corepll", .ops =3D &sifive_fu540_prci_tlclksel_clk_ops, diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prc= i.c index 53f6e00a03b9..bd66559fe2f8 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2020 SiFive, Inc. - * Copyright (C) 2020 Zong Li + * Copyright (C) 2020-2021 SiFive, Inc. + * Copyright (C) 2020-2021 Zong Li */ =20 #include @@ -13,38 +13,38 @@ =20 /* PRCI integration data for each WRPLL instance */ =20 -static struct __prci_wrpll_data __prci_corepll_data =3D { +static struct __prci_wrpll_data sifive_fu740_prci_corepll_data =3D { .cfg0_offs =3D PRCI_COREPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_COREPLLCFG1_OFFSET, .enable_bypass =3D sifive_prci_coreclksel_use_hfclk, .disable_bypass =3D sifive_prci_coreclksel_use_final_corepll, }; =20 -static struct __prci_wrpll_data __prci_ddrpll_data =3D { +static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data =3D { .cfg0_offs =3D PRCI_DDRPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_DDRPLLCFG1_OFFSET, }; =20 -static struct __prci_wrpll_data __prci_gemgxlpll_data =3D { +static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data =3D { .cfg0_offs =3D PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_GEMGXLPLLCFG1_OFFSET, }; =20 -static struct __prci_wrpll_data __prci_dvfscorepll_data =3D { +static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data =3D { .cfg0_offs =3D PRCI_DVFSCOREPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_DVFSCOREPLLCFG1_OFFSET, .enable_bypass =3D sifive_prci_corepllsel_use_corepll, .disable_bypass =3D sifive_prci_corepllsel_use_dvfscorepll, }; =20 -static struct __prci_wrpll_data __prci_hfpclkpll_data =3D { +static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data =3D { .cfg0_offs =3D PRCI_HFPCLKPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_HFPCLKPLLCFG1_OFFSET, .enable_bypass =3D sifive_prci_hfpclkpllsel_use_hfclk, .disable_bypass =3D sifive_prci_hfpclkpllsel_use_hfpclkpll, }; =20 -static struct __prci_wrpll_data __prci_cltxpll_data =3D { +static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data =3D { .cfg0_offs =3D PRCI_CLTXPLLCFG0_OFFSET, .cfg1_offs =3D PRCI_CLTXPLLCFG1_OFFSET, }; @@ -80,53 +80,53 @@ static const struct clk_ops sifive_fu740_prci_pcie_aux_= clk_ops =3D { =20 /* List of clock controls provided by the PRCI */ struct __prci_clock __prci_init_clocks_fu740[] =3D { - [PRCI_CLK_COREPLL] =3D { + [FU740_PRCI_CLK_COREPLL] =3D { .name =3D "corepll", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &__prci_corepll_data, + .pwd =3D &sifive_fu740_prci_corepll_data, }, - [PRCI_CLK_DDRPLL] =3D { + [FU740_PRCI_CLK_DDRPLL] =3D { .name =3D "ddrpll", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd =3D &__prci_ddrpll_data, + .pwd =3D &sifive_fu740_prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] =3D { + [FU740_PRCI_CLK_GEMGXLPLL] =3D { .name =3D "gemgxlpll", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &__prci_gemgxlpll_data, + .pwd =3D &sifive_fu740_prci_gemgxlpll_data, }, - [PRCI_CLK_DVFSCOREPLL] =3D { + [FU740_PRCI_CLK_DVFSCOREPLL] =3D { .name =3D "dvfscorepll", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &__prci_dvfscorepll_data, + .pwd =3D &sifive_fu740_prci_dvfscorepll_data, }, - [PRCI_CLK_HFPCLKPLL] =3D { + [FU740_PRCI_CLK_HFPCLKPLL] =3D { .name =3D "hfpclkpll", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &__prci_hfpclkpll_data, + .pwd =3D &sifive_fu740_prci_hfpclkpll_data, }, - [PRCI_CLK_CLTXPLL] =3D { + [FU740_PRCI_CLK_CLTXPLL] =3D { .name =3D "cltxpll", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &__prci_cltxpll_data, + .pwd =3D &sifive_fu740_prci_cltxpll_data, }, - [PRCI_CLK_TLCLK] =3D { + [FU740_PRCI_CLK_TLCLK] =3D { .name =3D "tlclk", .parent_name =3D "corepll", .ops =3D &sifive_fu740_prci_tlclksel_clk_ops, }, - [PRCI_CLK_PCLK] =3D { + [FU740_PRCI_CLK_PCLK] =3D { .name =3D "pclk", .parent_name =3D "hfpclkpll", .ops =3D &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, - [PRCI_CLK_PCIE_AUX] =3D { + [FU740_PRCI_CLK_PCIE_AUX] =3D { .name =3D "pcie_aux", .parent_name =3D "hfclk", .ops =3D &sifive_fu740_prci_pcie_aux_clk_ops, --=20 2.31.1 From nobody Tue Jun 30 09:57:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11761C4332F for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y8sm1415894pfl.207.2022.01.19.01.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Jan 2022 01:28:56 -0800 (PST) From: Zong Li To: mturquette@baylibre.com, sboyd@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, lee.jones@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH 4/4] clk: sifive: Move all stuff into SoCs header files from C files Date: Wed, 19 Jan 2022 17:28:41 +0800 Message-Id: <70c9317814b06c7ce37688b158178b188d3fd604.1642582832.git.zong.li@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Improve PRCI driver to reduce the complexity, we remove the SoCs C files by putting all stuff in each SoCs header files, and include these SoCs-specific header files in core of PRCI. It can also avoid the W=3D1 kernel build warnings about variable defined but not used [-Wunused-const-variable=3D], like commit 487dc7bb6a0c ("clk: sifive: fu540-prci: Declare static const variable 'prci_clk_fu540' where it's used") does. Signed-off-by: Zong Li Suggested-by: Lee Jones Acked-by: Palmer Dabbelt # aside from breaking bisect --- drivers/clk/sifive/Makefile | 2 +- drivers/clk/sifive/fu540-prci.c | 89 -------------------- drivers/clk/sifive/fu540-prci.h | 91 ++++++++++++++++++++- drivers/clk/sifive/fu740-prci.c | 134 ------------------------------- drivers/clk/sifive/fu740-prci.h | 130 +++++++++++++++++++++++++++++- drivers/clk/sifive/sifive-prci.c | 5 -- 6 files changed, 214 insertions(+), 237 deletions(-) delete mode 100644 drivers/clk/sifive/fu540-prci.c delete mode 100644 drivers/clk/sifive/fu740-prci.c diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 7b06fc04e6b3..efdf01f1c8d5 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_CLK_SIFIVE_PRCI) +=3D sifive-prci.o fu540-prci.o fu740-prci.o +obj-$(CONFIG_CLK_SIFIVE_PRCI) +=3D sifive-prci.o diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prc= i.c deleted file mode 100644 index d686f5cf3f71..000000000000 --- a/drivers/clk/sifive/fu540-prci.c +++ /dev/null @@ -1,89 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2018-2021 SiFive, Inc. - * Copyright (C) 2018-2019 Wesley Terpstra - * Copyright (C) 2018-2019 Paul Walmsley - * Copyright (C) 2020-2021 Zong Li - * - * The FU540 PRCI implements clock and reset control for the SiFive - * FU540-C000 chip. This driver assumes that it has sole control - * over all PRCI resources. - * - * This driver is based on the PRCI driver written by Wesley Terpstra: - * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d= 221b2ee56bb60 - * - * References: - * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" - */ - -#include - -#include - -#include "fu540-prci.h" -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu540_prci_corepll_data =3D { - .cfg0_offs =3D PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_COREPLLCFG1_OFFSET, - .enable_bypass =3D sifive_prci_coreclksel_use_hfclk, - .disable_bypass =3D sifive_prci_coreclksel_use_corepll, -}; - -static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data =3D { - .cfg0_offs =3D PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data =3D { - .cfg0_offs =3D PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops =3D { - .set_rate =3D sifive_prci_wrpll_set_rate, - .round_rate =3D sifive_prci_wrpll_round_rate, - .recalc_rate =3D sifive_prci_wrpll_recalc_rate, - .enable =3D sifive_prci_clock_enable, - .disable =3D sifive_prci_clock_disable, - .is_enabled =3D sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops =3D { - .recalc_rate =3D sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops =3D { - .recalc_rate =3D sifive_prci_tlclksel_recalc_rate, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu540[] =3D { - [FU540_PRCI_CLK_COREPLL] =3D { - .name =3D "corepll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu540_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu540_prci_corepll_data, - }, - [FU540_PRCI_CLK_DDRPLL] =3D { - .name =3D "ddrpll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu540_prci_wrpll_ro_clk_ops, - .pwd =3D &sifive_fu540_prci_ddrpll_data, - }, - [FU540_PRCI_CLK_GEMGXLPLL] =3D { - .name =3D "gemgxlpll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu540_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu540_prci_gemgxlpll_data, - }, - [FU540_PRCI_CLK_TLCLK] =3D { - .name =3D "tlclk", - .parent_name =3D "corepll", - .ops =3D &sifive_fu540_prci_tlclksel_clk_ops, - }, -}; diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prc= i.h index c220677dc010..e0173324f3c5 100644 --- a/drivers/clk/sifive/fu540-prci.h +++ b/drivers/clk/sifive/fu540-prci.h @@ -1,16 +1,99 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 SiFive, Inc. - * Zong Li + * Copyright (C) 2018-2021 SiFive, Inc. + * Copyright (C) 2018-2019 Wesley Terpstra + * Copyright (C) 2018-2019 Paul Walmsley + * Copyright (C) 2020-2021 Zong Li + * + * The FU540 PRCI implements clock and reset control for the SiFive + * FU540-C000 chip. This driver assumes that it has sole control + * over all PRCI resources. + * + * This driver is based on the PRCI driver written by Wesley Terpstra: + * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d= 221b2ee56bb60 + * + * References: + * - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset" */ =20 #ifndef __SIFIVE_CLK_FU540_PRCI_H #define __SIFIVE_CLK_FU540_PRCI_H =20 + +#include + +#include + #include "sifive-prci.h" =20 -#define NUM_CLOCK_FU540 4 +/* PRCI integration data for each WRPLL instance */ + +static struct __prci_wrpll_data sifive_fu540_prci_corepll_data =3D { + .cfg0_offs =3D PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_COREPLLCFG1_OFFSET, + .enable_bypass =3D sifive_prci_coreclksel_use_hfclk, + .disable_bypass =3D sifive_prci_coreclksel_use_corepll, +}; + +static struct __prci_wrpll_data sifive_fu540_prci_ddrpll_data =3D { + .cfg0_offs =3D PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_DDRPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu540_prci_gemgxlpll_data =3D { + .cfg0_offs =3D PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_GEMGXLPLLCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct clk_ops sifive_fu540_prci_wrpll_clk_ops =3D { + .set_rate =3D sifive_prci_wrpll_set_rate, + .round_rate =3D sifive_prci_wrpll_round_rate, + .recalc_rate =3D sifive_prci_wrpll_recalc_rate, + .enable =3D sifive_prci_clock_enable, + .disable =3D sifive_prci_clock_disable, + .is_enabled =3D sifive_clk_is_enabled, +}; + +static const struct clk_ops sifive_fu540_prci_wrpll_ro_clk_ops =3D { + .recalc_rate =3D sifive_prci_wrpll_recalc_rate, +}; + +static const struct clk_ops sifive_fu540_prci_tlclksel_clk_ops =3D { + .recalc_rate =3D sifive_prci_tlclksel_recalc_rate, +}; + +/* List of clock controls provided by the PRCI */ +static struct __prci_clock __prci_init_clocks_fu540[] =3D { + [FU540_PRCI_CLK_COREPLL] =3D { + .name =3D "corepll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu540_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu540_prci_corepll_data, + }, + [FU540_PRCI_CLK_DDRPLL] =3D { + .name =3D "ddrpll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu540_prci_wrpll_ro_clk_ops, + .pwd =3D &sifive_fu540_prci_ddrpll_data, + }, + [FU540_PRCI_CLK_GEMGXLPLL] =3D { + .name =3D "gemgxlpll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu540_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu540_prci_gemgxlpll_data, + }, + [FU540_PRCI_CLK_TLCLK] =3D { + .name =3D "tlclk", + .parent_name =3D "corepll", + .ops =3D &sifive_fu540_prci_tlclksel_clk_ops, + }, +}; =20 -extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540]; +static const struct prci_clk_desc prci_clk_fu540 =3D { + .clks =3D __prci_init_clocks_fu540, + .num_clks =3D ARRAY_SIZE(__prci_init_clocks_fu540), +}; =20 #endif /* __SIFIVE_CLK_FU540_PRCI_H */ diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prc= i.c deleted file mode 100644 index bd66559fe2f8..000000000000 --- a/drivers/clk/sifive/fu740-prci.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2020-2021 SiFive, Inc. - * Copyright (C) 2020-2021 Zong Li - */ - -#include - -#include - -#include "fu540-prci.h" -#include "sifive-prci.h" - -/* PRCI integration data for each WRPLL instance */ - -static struct __prci_wrpll_data sifive_fu740_prci_corepll_data =3D { - .cfg0_offs =3D PRCI_COREPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_COREPLLCFG1_OFFSET, - .enable_bypass =3D sifive_prci_coreclksel_use_hfclk, - .disable_bypass =3D sifive_prci_coreclksel_use_final_corepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data =3D { - .cfg0_offs =3D PRCI_DDRPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_DDRPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data =3D { - .cfg0_offs =3D PRCI_GEMGXLPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_GEMGXLPLLCFG1_OFFSET, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data =3D { - .cfg0_offs =3D PRCI_DVFSCOREPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_DVFSCOREPLLCFG1_OFFSET, - .enable_bypass =3D sifive_prci_corepllsel_use_corepll, - .disable_bypass =3D sifive_prci_corepllsel_use_dvfscorepll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data =3D { - .cfg0_offs =3D PRCI_HFPCLKPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_HFPCLKPLLCFG1_OFFSET, - .enable_bypass =3D sifive_prci_hfpclkpllsel_use_hfclk, - .disable_bypass =3D sifive_prci_hfpclkpllsel_use_hfpclkpll, -}; - -static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data =3D { - .cfg0_offs =3D PRCI_CLTXPLLCFG0_OFFSET, - .cfg1_offs =3D PRCI_CLTXPLLCFG1_OFFSET, -}; - -/* Linux clock framework integration */ - -static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops =3D { - .set_rate =3D sifive_prci_wrpll_set_rate, - .round_rate =3D sifive_prci_wrpll_round_rate, - .recalc_rate =3D sifive_prci_wrpll_recalc_rate, - .enable =3D sifive_prci_clock_enable, - .disable =3D sifive_prci_clock_disable, - .is_enabled =3D sifive_clk_is_enabled, -}; - -static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops =3D { - .recalc_rate =3D sifive_prci_wrpll_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops =3D { - .recalc_rate =3D sifive_prci_tlclksel_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops =3D { - .recalc_rate =3D sifive_prci_hfpclkplldiv_recalc_rate, -}; - -static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops =3D { - .enable =3D sifive_prci_pcie_aux_clock_enable, - .disable =3D sifive_prci_pcie_aux_clock_disable, - .is_enabled =3D sifive_prci_pcie_aux_clock_is_enabled, -}; - -/* List of clock controls provided by the PRCI */ -struct __prci_clock __prci_init_clocks_fu740[] =3D { - [FU740_PRCI_CLK_COREPLL] =3D { - .name =3D "corepll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu740_prci_corepll_data, - }, - [FU740_PRCI_CLK_DDRPLL] =3D { - .name =3D "ddrpll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_wrpll_ro_clk_ops, - .pwd =3D &sifive_fu740_prci_ddrpll_data, - }, - [FU740_PRCI_CLK_GEMGXLPLL] =3D { - .name =3D "gemgxlpll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu740_prci_gemgxlpll_data, - }, - [FU740_PRCI_CLK_DVFSCOREPLL] =3D { - .name =3D "dvfscorepll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu740_prci_dvfscorepll_data, - }, - [FU740_PRCI_CLK_HFPCLKPLL] =3D { - .name =3D "hfpclkpll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu740_prci_hfpclkpll_data, - }, - [FU740_PRCI_CLK_CLTXPLL] =3D { - .name =3D "cltxpll", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_wrpll_clk_ops, - .pwd =3D &sifive_fu740_prci_cltxpll_data, - }, - [FU740_PRCI_CLK_TLCLK] =3D { - .name =3D "tlclk", - .parent_name =3D "corepll", - .ops =3D &sifive_fu740_prci_tlclksel_clk_ops, - }, - [FU740_PRCI_CLK_PCLK] =3D { - .name =3D "pclk", - .parent_name =3D "hfpclkpll", - .ops =3D &sifive_fu740_prci_hfpclkplldiv_clk_ops, - }, - [FU740_PRCI_CLK_PCIE_AUX] =3D { - .name =3D "pcie_aux", - .parent_name =3D "hfclk", - .ops =3D &sifive_fu740_prci_pcie_aux_clk_ops, - }, -}; diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prc= i.h index 511a0bf7ba2b..f31cd30fc395 100644 --- a/drivers/clk/sifive/fu740-prci.h +++ b/drivers/clk/sifive/fu740-prci.h @@ -1,17 +1,139 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2020 SiFive, Inc. - * Zong Li + * Copyright (C) 2020-2021 SiFive, Inc. + * Copyright (C) 2020-2021 Zong Li */ =20 #ifndef __SIFIVE_CLK_FU740_PRCI_H #define __SIFIVE_CLK_FU740_PRCI_H =20 +#include + +#include + #include "sifive-prci.h" =20 -#define NUM_CLOCK_FU740 9 +/* PRCI integration data for each WRPLL instance */ + +static struct __prci_wrpll_data sifive_fu740_prci_corepll_data =3D { + .cfg0_offs =3D PRCI_COREPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_COREPLLCFG1_OFFSET, + .enable_bypass =3D sifive_prci_coreclksel_use_hfclk, + .disable_bypass =3D sifive_prci_coreclksel_use_final_corepll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_ddrpll_data =3D { + .cfg0_offs =3D PRCI_DDRPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_DDRPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_gemgxlpll_data =3D { + .cfg0_offs =3D PRCI_GEMGXLPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_GEMGXLPLLCFG1_OFFSET, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_dvfscorepll_data =3D { + .cfg0_offs =3D PRCI_DVFSCOREPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_DVFSCOREPLLCFG1_OFFSET, + .enable_bypass =3D sifive_prci_corepllsel_use_corepll, + .disable_bypass =3D sifive_prci_corepllsel_use_dvfscorepll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_hfpclkpll_data =3D { + .cfg0_offs =3D PRCI_HFPCLKPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_HFPCLKPLLCFG1_OFFSET, + .enable_bypass =3D sifive_prci_hfpclkpllsel_use_hfclk, + .disable_bypass =3D sifive_prci_hfpclkpllsel_use_hfpclkpll, +}; + +static struct __prci_wrpll_data sifive_fu740_prci_cltxpll_data =3D { + .cfg0_offs =3D PRCI_CLTXPLLCFG0_OFFSET, + .cfg1_offs =3D PRCI_CLTXPLLCFG1_OFFSET, +}; + +/* Linux clock framework integration */ + +static const struct clk_ops sifive_fu740_prci_wrpll_clk_ops =3D { + .set_rate =3D sifive_prci_wrpll_set_rate, + .round_rate =3D sifive_prci_wrpll_round_rate, + .recalc_rate =3D sifive_prci_wrpll_recalc_rate, + .enable =3D sifive_prci_clock_enable, + .disable =3D sifive_prci_clock_disable, + .is_enabled =3D sifive_clk_is_enabled, +}; =20 -extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740]; +static const struct clk_ops sifive_fu740_prci_wrpll_ro_clk_ops =3D { + .recalc_rate =3D sifive_prci_wrpll_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_tlclksel_clk_ops =3D { + .recalc_rate =3D sifive_prci_tlclksel_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_hfpclkplldiv_clk_ops =3D { + .recalc_rate =3D sifive_prci_hfpclkplldiv_recalc_rate, +}; + +static const struct clk_ops sifive_fu740_prci_pcie_aux_clk_ops =3D { + .enable =3D sifive_prci_pcie_aux_clock_enable, + .disable =3D sifive_prci_pcie_aux_clock_disable, + .is_enabled =3D sifive_prci_pcie_aux_clock_is_enabled, +}; + +/* List of clock controls provided by the PRCI */ +static struct __prci_clock __prci_init_clocks_fu740[] =3D { + [FU740_PRCI_CLK_COREPLL] =3D { + .name =3D "corepll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu740_prci_corepll_data, + }, + [FU740_PRCI_CLK_DDRPLL] =3D { + .name =3D "ddrpll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_wrpll_ro_clk_ops, + .pwd =3D &sifive_fu740_prci_ddrpll_data, + }, + [FU740_PRCI_CLK_GEMGXLPLL] =3D { + .name =3D "gemgxlpll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu740_prci_gemgxlpll_data, + }, + [FU740_PRCI_CLK_DVFSCOREPLL] =3D { + .name =3D "dvfscorepll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu740_prci_dvfscorepll_data, + }, + [FU740_PRCI_CLK_HFPCLKPLL] =3D { + .name =3D "hfpclkpll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu740_prci_hfpclkpll_data, + }, + [FU740_PRCI_CLK_CLTXPLL] =3D { + .name =3D "cltxpll", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_wrpll_clk_ops, + .pwd =3D &sifive_fu740_prci_cltxpll_data, + }, + [FU740_PRCI_CLK_TLCLK] =3D { + .name =3D "tlclk", + .parent_name =3D "corepll", + .ops =3D &sifive_fu740_prci_tlclksel_clk_ops, + }, + [FU740_PRCI_CLK_PCLK] =3D { + .name =3D "pclk", + .parent_name =3D "hfpclkpll", + .ops =3D &sifive_fu740_prci_hfpclkplldiv_clk_ops, + }, + [FU740_PRCI_CLK_PCIE_AUX] =3D { + .name =3D "pcie_aux", + .parent_name =3D "hfclk", + .ops =3D &sifive_fu740_prci_pcie_aux_clk_ops, + }, +}; =20 static const struct prci_clk_desc prci_clk_fu740 =3D { .clks =3D __prci_init_clocks_fu740, diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-p= rci.c index 80a288c59e56..916d2fc28b9c 100644 --- a/drivers/clk/sifive/sifive-prci.c +++ b/drivers/clk/sifive/sifive-prci.c @@ -12,11 +12,6 @@ #include "fu540-prci.h" #include "fu740-prci.h" =20 -static const struct prci_clk_desc prci_clk_fu540 =3D { - .clks =3D __prci_init_clocks_fu540, - .num_clks =3D ARRAY_SIZE(__prci_init_clocks_fu540), -}; - /* * Private functions */ --=20 2.31.1