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The AMD IOMMU driver currently caps this with pagetable level reported by EFR[HATS] when configuring paging domains (hw_max_vasz_lg2). On systems where firmware or VM advertises smaller or different limits, the driver may over-advertise capabilities and create domains outside the hardware=E2=80=99s actual bound= s. Signed-off-by: Ankit Soni --- drivers/iommu/amd/amd_iommu.h | 2 +- drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/init.c | 34 +++++++++++++++++++++++++---- drivers/iommu/amd/iommu.c | 3 +-- 4 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 1342e764a548..f915938a3a08 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -41,7 +41,7 @@ int amd_iommu_enable_faulting(unsigned int cpu); extern int amd_iommu_guest_ir; extern enum protection_domain_mode amd_iommu_pgtable; extern int amd_iommu_gpt_level; -extern u8 amd_iommu_hpt_level; +extern u8 amd_iommu_hpt_vasize; extern unsigned long amd_iommu_pgsize_bitmap; extern bool amd_iommu_hatdis; =20 diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index c685d3771436..6a85a38d34bd 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -395,6 +395,7 @@ #define IOMMU_IVINFO_OFFSET 36 #define IOMMU_IVINFO_EFRSUP BIT(0) #define IOMMU_IVINFO_DMA_REMAP BIT(1) +#define IOMMU_IVINFO_VASIZE GENMASK_ULL(21, 15) =20 /* IOMMU Feature Reporting Field (for IVHD type 10h */ #define IOMMU_FEAT_GASUP_SHIFT 6 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index f3fd7f39efb4..03013189b983 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -152,8 +152,8 @@ bool amd_iommu_dump; bool amd_iommu_irq_remap __read_mostly; =20 enum protection_domain_mode amd_iommu_pgtable =3D PD_MODE_V1; -/* Host page table level */ -u8 amd_iommu_hpt_level; +/* Virtual address size */ +u8 amd_iommu_hpt_vasize; /* Guest page table level */ int amd_iommu_gpt_level =3D PAGE_MODE_4_LEVEL; =20 @@ -3156,6 +3156,29 @@ static void __init ivinfo_init(void *ivrs) amd_iommu_ivinfo =3D *((u32 *)(ivrs + IOMMU_IVINFO_OFFSET)); } =20 +static u8 ivinfo_vasize_bits(void) +{ + u8 vasize; + + vasize =3D FIELD_GET(IOMMU_IVINFO_VASIZE, amd_iommu_ivinfo); + + /* + * IVINFO[VASIZE] encodes the log2 of the maximum virtual address + * processed by the IOMMU. + */ + switch (vasize) { + case 32: + case 40: + case 48: + case 64: + return vasize; + default: + pr_warn_once("IVRS: IVINFO[VASIZE]=3D0x%x is invalid, defaulting to 64= =E2=80=91bit VA\n", + vasize); + return 64; + } +} + /* * This is the hardware init function for AMD IOMMU in the system. * This function is called either from amd_iommu_init or from the interrupt @@ -3188,7 +3211,7 @@ static int __init early_amd_iommu_init(void) struct acpi_table_header *ivrs_base; int ret; acpi_status status; - u8 efr_hats; + u8 efr_hats, max_vasize; =20 if (!amd_iommu_detected) return -ENODEV; @@ -3218,6 +3241,8 @@ static int __init early_amd_iommu_init(void) =20 ivinfo_init(ivrs_base); =20 + max_vasize =3D ivinfo_vasize_bits(); + amd_iommu_target_ivhd_type =3D get_highest_supported_ivhd_type(ivrs_base); DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type); =20 @@ -3240,7 +3265,8 @@ static int __init early_amd_iommu_init(void) * efr[HATS] bits specify the maximum host translation level * supported, with LEVEL 4 being initial max level. */ - amd_iommu_hpt_level =3D efr_hats + PAGE_MODE_4_LEVEL; + amd_iommu_hpt_vasize =3D min(max_vasize, + (efr_hats + PAGE_MODE_4_LEVEL - 1) * 9 + 21); } else { pr_warn_once(FW_BUG "Disable host address translation due to invalid tra= nslation level (%#x).\n", efr_hats); diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 81c4d7733872..e8d15ac9b2bd 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2712,8 +2712,7 @@ static struct iommu_domain *amd_iommu_domain_alloc_pa= ging_v1(struct device *dev, else cfg.common.features |=3D BIT(PT_FEAT_FLUSH_RANGE); =20 - cfg.common.hw_max_vasz_lg2 =3D - min(64, (amd_iommu_hpt_level - 1) * 9 + 21); + cfg.common.hw_max_vasz_lg2 =3D amd_iommu_hpt_vasize; cfg.common.hw_max_oasz_lg2 =3D 52; cfg.starting_level =3D 2; domain->domain.ops =3D &amdv1_ops; --=20 2.43.0