From nobody Fri Oct 3 21:00:03 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAADE2D0C82; Mon, 25 Aug 2025 22:59:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756162763; cv=none; b=A6Ita3kWr6Vcpiu3wogfB56w65RJDHhOx9caCd/EDzzmVoCSSjyH2lVUFTcPyP0dLc1SmnyQdg0gfmfyaH0E+0AHYBn4EFlSmnwLWC8RxD2skRo1KIhRq2PTac4lapYdO/I3HK3G9/ctzogiigt7qMu7NSyW1adfJMt6MnziUB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756162763; c=relaxed/simple; bh=kEXKic3dGl+hZ/XHZEbeEXIlQqYcgxBCNPzqY8fwb4M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MFyY1JxNAup2ZTF1QW1ZuDSllTOmEu5kTQoZUykXWYvEf6SUuvONjbEyvYsC+hprAwooSgP9fdtzm6H9ajD/WkWjV8LAYpPZJ7qk09o0DWvRbK2sZ/pTbZJl31C3BIUoXrlbAG5ejGrpvqoj5qMdSqxNuZNbU3yW+C6VyXbAQWQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CgcKFXL2; arc=none smtp.client-ip=198.175.65.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CgcKFXL2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1756162762; x=1787698762; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kEXKic3dGl+hZ/XHZEbeEXIlQqYcgxBCNPzqY8fwb4M=; b=CgcKFXL2ahpk4znwesN+2l4KtGZms+Bop+idWpzGWXE5v6hn6i/LQFln blQQHOewYgkAGI92PqWVQrsNNeQ9mKbdwvxC/g0ufHa8Ztm2X704pid19 yrNEH6r+T4NJUJnFACvTZtJlzQ0C5rcTe7XST9mehrqQJIN1gTFfPAzvG /+/NWXg7XD50sDDje6fh1mBPxV2V3Wm25I3Md0HC4McY0d7IUn99/Zld1 nnheY6l3NzIjkRQKBkS4Rh81E4bcFTeSYuJ8xpt2uWrLBYaSUxs5MRbXY r1/b5Y8gnVLFS5nbQGIoYDK2Kt9wdPZLU01eS0aR6N3j7gmfgct4qMFJL Q==; X-CSE-ConnectionGUID: seL9qeBoQaWaRB95SQ+dPQ== X-CSE-MsgGUID: p5JgPOmZTc6PzHQzFNkfzw== X-IronPort-AV: E=McAfee;i="6800,10657,11533"; a="58533396" X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="58533396" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2025 15:59:22 -0700 X-CSE-ConnectionGUID: H2TppVnPSKOYQMrPCQsl4Q== X-CSE-MsgGUID: 6bbhAbTeTJq0juy0WuSBYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,214,1751266800"; d="scan'208";a="200308445" Received: from ldmartin-desk2.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.124.223.59]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Aug 2025 15:59:16 -0700 From: Kai Huang To: dave.hansen@intel.com, bp@alien8.de, tglx@linutronix.de, peterz@infradead.org, mingo@redhat.com, hpa@zytor.com, thomas.lendacky@amd.com Cc: x86@kernel.org, kas@kernel.org, rick.p.edgecombe@intel.com, dwmw@amazon.co.uk, linux-kernel@vger.kernel.org, pbonzini@redhat.com, seanjc@google.com, kvm@vger.kernel.org, reinette.chatre@intel.com, isaku.yamahata@intel.com, dan.j.williams@intel.com, ashish.kalra@amd.com, nik.borisov@suse.com, chao.gao@intel.com, sagis@google.com, farrah.chen@intel.com Subject: [PATCH v7 4/7] x86/kexec: Disable kexec/kdump on platforms with TDX partial write erratum Date: Tue, 26 Aug 2025 10:58:39 +1200 Message-ID: X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some early TDX-capable platforms have an erratum: A kernel partial write (a write transaction of less than cacheline lands at memory controller) to TDX private memory poisons that memory, and a subsequent read triggers a machine check. On those platforms, the old kernel must reset TDX private memory before jumping to the new kernel, otherwise the new kernel may see unexpected machine check. Currently the kernel doesn't track which page is a TDX private page. For simplicity just fail kexec/kdump for those platforms. Leverage the existing machine_kexec_prepare() to fail kexec/kdump by adding the check of the presence of the TDX erratum (which is only checked for if the kernel is built with TDX host support). This rejects kexec/kdump when the kernel is loading the kexec/kdump kernel image. The alternative is to reject kexec/kdump when the kernel is jumping to the new kernel. But for kexec this requires adding a new check (e.g., arch_kexec_allowed()) in the common code to fail kernel_kexec() at early stage. Kdump (crash_kexec()) needs similar check, but it's hard to justify because crash_kexec() is not supposed to abort. It's feasible to further relax this limitation, i.e., only fail kexec when TDX is actually enabled by the kernel. But this is still a half measure compared to resetting TDX private memory so just do the simplest thing for now. The impact to userspace is the users will get an error when loading the kexec/kdump kernel image: kexec_load failed: Operation not supported This might be confusing to the users, thus also print the reason in the dmesg: [..] kexec: Not allowed on platform with tdx_pw_mce bug. Signed-off-by: Kai Huang Tested-by: Farrah Chen Reviewed-by: Rick Edgecombe --- arch/x86/kernel/machine_kexec_64.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/x86/kernel/machine_kexec_64.c b/arch/x86/kernel/machine_k= exec_64.c index dfb91091f451..15088d14904f 100644 --- a/arch/x86/kernel/machine_kexec_64.c +++ b/arch/x86/kernel/machine_kexec_64.c @@ -347,6 +347,22 @@ int machine_kexec_prepare(struct kimage *image) unsigned long reloc_end =3D (unsigned long)__relocate_kernel_end; int result; =20 + /* + * Some early TDX-capable platforms have an erratum. A kernel + * partial write (a write transaction of less than cacheline + * lands at memory controller) to TDX private memory poisons that + * memory, and a subsequent read triggers a machine check. + * + * On those platforms the old kernel must reset TDX private + * memory before jumping to the new kernel otherwise the new + * kernel may see unexpected machine check. For simplicity + * just fail kexec/kdump on those platforms. + */ + if (boot_cpu_has_bug(X86_BUG_TDX_PW_MCE)) { + pr_info_once("Not allowed on platform with tdx_pw_mce bug\n"); + return -EOPNOTSUPP; + } + /* Setup the identity mapped 64bit page table */ result =3D init_pgtable(image, __pa(control_page)); if (result) --=20 2.50.1