From nobody Sat Oct 4 11:14:51 2025 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E30692D7D42; Mon, 18 Aug 2025 09:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508855; cv=none; b=Fpw4s6If237wLFpbW2NutRGI868X2JFlBXRJQdhafVoaFdtTCi2WqeCPeaoaJMdXNanQk31zcHTeuoAPAp+mYc7zzfqZ60mXuVkpt6BRpgtxkH4q91VnoIPwPHqJDPsR43mHBTqW8NI7hqlWCadlWNYyEQRi89PSjdhHYAZT3x0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508855; c=relaxed/simple; bh=KAXI/UdG1uKmQEqjT0xzFF6ZLrXwXMHk7giEW1/cpwI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iCwZqQZn0QgEghEM2vrUfU9VC7JfawFGnyB9gYE7i6xTYnuqzgghZ+VH8ez61+EzjWnfkXj7HaZ8o3lUi1XRD8H6M9BXa02u+BM77VaaNztkkNANueneyPJHJbtQT35SvtOHbramZGudEoc0CmTGKOIsoJpkcoaamd/PX9jF/qc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c55sd6fBxz9sX3; Mon, 18 Aug 2025 10:46:13 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lbLLFka9tjxC; Mon, 18 Aug 2025 10:46:13 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c55sZ11XFz9sWn; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 0D93C8B766; Mon, 18 Aug 2025 10:46:10 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id YFmZUm584ZmT; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id CF60C8B763; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 4/5] soc: fsl: qe: Add support of IRQ in QE GPIO Date: Mon, 18 Aug 2025 10:45:57 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=4414; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=KAXI/UdG1uKmQEqjT0xzFF6ZLrXwXMHk7giEW1/cpwI=; b=MW/ze3K9TK2iL0/rORULbghAvqryKWrfqy6TLbLvD5VVeZnLqeWtR7lBIzwSXSaoZHM8JT18w /wsaAaaP1BTDABTihOHtotOGJXdkcCKIOkhkfqAHIOgpIegdhqYENi+ X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the QE, a few GPIOs are IRQ capable. Similarly to commit 726bd223105c ("powerpc/8xx: Adding support of IRQ in MPC8xx GPIO"), add IRQ support to QE GPIO. Add property 'fsl,qe-gpio-irq-mask' similar to 'fsl,cpm1-gpio-irq-mask' that define which of the GPIOs have IRQs. Here is an exemple for port B of mpc8323 which has IRQs for GPIOs PB7, PB9, PB25 and PB27. qe_pio_b: gpio-controller@1418 { #gpio-cells =3D <2>; compatible =3D "fsl,mpc8323-qe-pario-bank"; reg =3D <0x1418 0x18>; interrupts =3D <4 5 6 7>; fsl,qe-gpio-irq-mask =3D <0x01400050>; interrupt-parent =3D <&qepic>; gpio-controller; }; Signed-off-by: Christophe Leroy --- v2: Document fsl,qe-gpio-irq-mask --- .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 19 ++++++++++++++++++ drivers/soc/fsl/qe/gpio.c | 20 +++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt= b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt index 09b1b05fa677..9cd6e5ac2a7b 100644 --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/par_io.txt @@ -32,6 +32,15 @@ Required properties: "fsl,mpc8323-qe-pario-bank". - reg : offset to the register set and its length. - gpio-controller : node to identify gpio controllers. +Optional properties: +- fsl,qe-gpio-irq-mask : For banks having interrupt capability this item t= ells + which ports have an associated interrupt (ports are listed in the same o= rder + QE ports registers) +- interrupts : This property provides the list of interrupt for each GPIO = having + one as described by the fsl,cpm1-gpio-irq-mask property. There should be= as + many interrupts as number of ones in the mask property. The first interr= upt in + the list corresponds to the most significant bit of the mask. +- interrupt-parent : Parent for the above interrupt property. =20 Example: qe_pio_a: gpio-controller@1400 { @@ -42,6 +51,16 @@ Example: gpio-controller; }; =20 + qe_pio_b: gpio-controller@1418 { + #gpio-cells =3D <2>; + compatible =3D "fsl,mpc8323-qe-pario-bank"; + reg =3D <0x1418 0x18>; + interrupts =3D <4 5 6 7>; + fsl,qe-gpio-irq-mask =3D <0x01400050>; + interrupt-parent =3D <&qepic>; + gpio-controller; + }; + qe_pio_e: gpio-controller@1460 { #gpio-cells =3D <2>; compatible =3D "fsl,mpc8360-qe-pario-bank", diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c index a338469cebe4..91d469403126 100644 --- a/drivers/soc/fsl/qe/gpio.c +++ b/drivers/soc/fsl/qe/gpio.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -32,6 +33,8 @@ struct qe_gpio_chip { =20 /* saved_regs used to restore dedicated functions */ struct qe_pio_regs saved_regs; + + int irq[32]; }; =20 static void qe_gpio_save_regs(struct qe_gpio_chip *qe_gc) @@ -135,6 +138,13 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsig= ned int gpio, int val) return 0; } =20 +static int qe_gpio_to_irq(struct gpio_chip *gc, unsigned int gpio) +{ + struct qe_gpio_chip *qe_gc =3D gpiochip_get_data(gc); + + return qe_gc->irq[gpio] ? : -ENXIO; +} + struct qe_pin { /* * The qe_gpio_chip name is unfortunate, we should change that to @@ -295,6 +305,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) struct device_node *np =3D dev->of_node; struct qe_gpio_chip *qe_gc; struct gpio_chip *gc; + u32 mask; =20 qe_gc =3D devm_kzalloc(dev, sizeof(*qe_gc), GFP_KERNEL); if (!qe_gc) @@ -302,6 +313,14 @@ static int qe_gpio_probe(struct platform_device *ofdev) =20 spin_lock_init(&qe_gc->lock); =20 + if (!of_property_read_u32(np, "fsl,qe-gpio-irq-mask", &mask)) { + int i, j; + + for (i =3D 0, j =3D 0; i < ARRAY_SIZE(qe_gc->irq); i++) + if (mask & (1 << (31 - i))) + qe_gc->irq[i] =3D irq_of_parse_and_map(np, j++); + } + gc =3D &qe_gc->gc; =20 gc->base =3D -1; @@ -311,6 +330,7 @@ static int qe_gpio_probe(struct platform_device *ofdev) gc->get =3D qe_gpio_get; gc->set =3D qe_gpio_set; gc->set_multiple =3D qe_gpio_set_multiple; + gc->to_irq =3D qe_gpio_to_irq; gc->parent =3D dev; gc->owner =3D THIS_MODULE; =20 --=20 2.49.0