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Fri, 5 Dec 2025 16:52:19 -0800 From: Nicolin Chen To: , , CC: , , , , , Subject: [PATCH rc v1 2/4] iommu/arm-smmu-v3: Ignore STE MEV when computing the update sequence Date: Fri, 5 Dec 2025 16:52:01 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529D:EE_|SA0PR12MB4416:EE_ X-MS-Office365-Filtering-Correlation-Id: c271487d-5866-4b4f-f8e1-08de3461ba42 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8xqyGgbdqm+oY6eJgnnY5ODWWA1VA2H51EaHY9sDP3PBhgmSOWLvqilfUNbG?= =?us-ascii?Q?Vv7MHAWMcTfwTm+lWPy+YRklzFoVS8UGHZYXLD7+qefrLdgknDRCpF6BGAi1?= =?us-ascii?Q?PAa6qpD2b3x+8fRsYRUwv9uGiVBS5vF4NUEbNsQecWqQkQJlzQZ4lJZGXtXz?= =?us-ascii?Q?6r3on1oaKtrihL6fkQLiw7PddJbYCkF31Yae8Zkgh65K6BW/w9+GAMaagOP7?= =?us-ascii?Q?1LURJd41R6U7Kyad+yjYzIkjI/IBBxIpXeGyRXropxdp9mbxvicSjCDBzvnp?= =?us-ascii?Q?rpXcgTRGq9y8NsTiIn89FFsi/A8Ba9iWFyYW72gtRnU2+4zv9V+SfWB2JRCB?= =?us-ascii?Q?qOZvxNk2CdSaXwNG9qqOUwOVGnCuiccSSXxeY07CewPSy+ShkA9Nge+KHMtl?= =?us-ascii?Q?awuGsfoB/Q4kHBQpQ7cQyoh0WrsmIpLSSYQdxRtbZ9Kw9ev5szgaTmtQzHYw?= =?us-ascii?Q?RcNNh6eFkh6tHRD76Qs6KT3ZicrZ4luokp51YvzW59/wNuf/t27xHMuzbFUh?= =?us-ascii?Q?D87kb3oXtBt3eUxUZNpOYFhs7cbAIe0ZHW1nO5BZafMpxyERMAZxqDdg3JqP?= =?us-ascii?Q?sBqAVWpw/IEXnxRbJTjak45xwTxKwabIs/RQjelS1IPtgGUeWv8gIqD+PoJ5?= =?us-ascii?Q?I+psWYGauYG7bIllUnBWf6AZz2ciZhNMpwlZ2+GQwcGvI//qaPUTZ+StxeoH?= =?us-ascii?Q?D82OFC0B7btp2zbTGEAtOsmk6MAcmaxSOsTSb3o5VC0ofW3V4yZ0Z8sW5IIt?= =?us-ascii?Q?Ky1dXxg+5XOWRdWJY+6so5s72lP2423cTVt3LpB6FfgyYdU1CgcJ1MVeEelb?= =?us-ascii?Q?olgr1/zMdK/MhzEoeM787At4nRDDwAPtMCumPYjD3dR2xs36IJ9OMi2jtFwV?= =?us-ascii?Q?gg1dZ6rAbY3pRNYqi8EWMx4r/43WBTwJ8SVIBmRkkxw1uTNBmLwY6tfSH7N1?= =?us-ascii?Q?QD7YrDjyRGy51KkepmSQovlDAPpkgN7w7BLcl0Oq/yWJPCVGtoZ4tMZ6LjeH?= =?us-ascii?Q?DydgmqiJrv15Bw8ueFo4fOVfXCw6D2jr2Lbpgbv9Ef/7VRwILFYVlhrdh2jg?= =?us-ascii?Q?7F3/6FLaORUlWe7zdpch3XAM4sN4lEh2NkvcybkxTDin0IRsRX2hM0S624FC?= =?us-ascii?Q?LFbCJoyLsv6rSpV5+MmWrYF5lr1sXAi+2x/vMcyv1CYJfre0W62741l2INKG?= =?us-ascii?Q?j/Onm5OG9bMU+KkEON+e1/mwnKH1q3djDNLEDhTvNM2sfcFirKWkPgSt74Cu?= =?us-ascii?Q?PRiqL0ZNPr1ORdlOMD1623Tn0TKWmBc66lF00oKP6/u1TTztI1NySW7KpMo0?= =?us-ascii?Q?Cb4nU3KKNHbtH7fWzW7LHXMqMj9DcOztTEM9PPH1l9oT1xL7LEokv6VJM8Fk?= =?us-ascii?Q?f3ahnd6u3NTKia7N4WVchllUTE6B9bpL0tiaFafXH1jTm65YJkaCFE7Q2wjf?= =?us-ascii?Q?YGz9yK6nTVgjw9hOOnEwFprWLZAr2K9LEqfjMkw8USIEp1nvzMcPWumkcBk8?= =?us-ascii?Q?+jjz5Gr8igSpPK7xQZ/fRxgUhWlzNqZKcXTGENcTiqv3CtcS5oWRsLJbHLWG?= =?us-ascii?Q?iZWlqJhzSCg6Bex6dPs=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2025 00:52:27.3289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c271487d-5866-4b4f-f8e1-08de3461ba42 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4416 Content-Type: text/plain; charset="utf-8" From: Jason Gunthorpe Nested CD tables set the MEV bit to try to reduce multi-fault spamming on the hypervisor. Since MEV is in STE word 1 this causes a breaking update sequence that is not required and impacts real workloads. For the purposes of STE updates the value of MEV doesn't matter, if it is set/cleared early or late it just results in a change to the fault reports that must be supported by the kernel anyhow. The spec says: Note: Software must expect, and be able to deal with, coalesced fault records even when MEV =3D=3D 0. So ignore MEV when computing the update sequence to avoid creating a breaking update. Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS = mitigations") Cc: stable@vger.kernel.org Signed-off-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 95a4cfc5882d..2df657c87abd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1052,7 +1052,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW | - STRTAB_STE_1_EATS | STRTAB_STE_1_MEV); + STRTAB_STE_1_EATS); used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID); =20 /* @@ -1068,7 +1068,7 @@ void arm_smmu_get_ste_used(const __le64 *ent, __le64 = *used_bits) if (cfg & BIT(1)) { used_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_S2FWB | STRTAB_STE_1_EATS | - STRTAB_STE_1_SHCFG | STRTAB_STE_1_MEV); + STRTAB_STE_1_SHCFG); used_bits[2] |=3D cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used); VISIBLE_IF_KUNIT void arm_smmu_get_ste_ignored(__le64 *ignored_bits) { + /* + * MEV does not meaningfully impact the operation of the HW, it only + * changes how many fault events are generated, thus we can ignore it + * when computing the ordering. The spec notes the device can act like + * MEV=3D1 anyhow: + * + * Note: Software must expect, and be able to deal with, coalesced + * fault records even when MEV =3D=3D 0. + */ + ignored_bits[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); } EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_ignored); =20 --=20 2.43.0