From nobody Sat Apr 11 13:01:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D8C2C6FA99 for ; Mon, 6 Mar 2023 14:17:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229936AbjCFORo (ORCPT ); Mon, 6 Mar 2023 09:17:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbjCFOR3 (ORCPT ); Mon, 6 Mar 2023 09:17:29 -0500 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C424A30E3; Mon, 6 Mar 2023 06:16:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678112189; x=1709648189; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VqcKARLycsk9x9FHwX2Ecm9BMNr+EPyvV4YYN1oDJ30=; b=TARL48+4n7wzHm8zR4RlQCmLn+0zqfxMPkQBCkG0Z+Wt+0X8iZ7dOdiM zobTrp2dEr866CYAFMCepkfOybHJ9xTQZfGDrXWZSvSBv7ACD1TmFvtIh AmMLrkijKe36EikhG2nTW30w7Xzm4ywzpS20eOvL4rBeLCBpXU6UVOvFl zNUpQ+W8g6+E9IeK+aTG3bR7qt8UD406SoDoQXAK7fvWK7m5qi1XkrIb/ YOt7DsA0diN27RtpN9XUZiwZeEM3gzf28p+UxSj1WKU/JRsOdtNUg1Tmb MZ/5dyq1pWaOclN9nwwXr/wOvb2G9iAoWoE6W0dBHo4Q7m87TZMyozGkV w==; X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="337079984" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="337079984" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10641"; a="765231976" X-IronPort-AV: E=Sophos;i="5.98,238,1673942400"; d="scan'208";a="765231976" Received: from jwhisle1-mobl2.amr.corp.intel.com (HELO khuang2-desk.gar.corp.intel.com) ([10.212.92.57]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Mar 2023 06:14:29 -0800 From: Kai Huang To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: linux-mm@kvack.org, dave.hansen@intel.com, peterz@infradead.org, tglx@linutronix.de, seanjc@google.com, pbonzini@redhat.com, dan.j.williams@intel.com, rafael.j.wysocki@intel.com, kirill.shutemov@linux.intel.com, ying.huang@intel.com, reinette.chatre@intel.com, len.brown@intel.com, tony.luck@intel.com, ak@linux.intel.com, isaku.yamahata@intel.com, chao.gao@intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, david@redhat.com, bagasdotme@gmail.com, sagis@google.com, imammedo@redhat.com, kai.huang@intel.com Subject: [PATCH v10 01/16] x86/tdx: Define TDX supported page sizes as macros Date: Tue, 7 Mar 2023 03:13:46 +1300 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" TDX supports 4K, 2M and 1G page sizes. The corresponding values are defined by the TDX module spec and used as TDX module ABI. Currently, they are used in try_accept_one() when the TDX guest tries to accept a page. However currently try_accept_one() uses hard-coded magic values. Define TDX supported page sizes as macros and get rid of the hard-coded values in try_accept_one(). TDX host support will need to use them too. Signed-off-by: Kai Huang Reviewed-by: Kirill A. Shutemov Reviewed-by: Dave Hansen Reviewed-by: David Hildenbrand --- v9 -> v10: - No change. v8 -> v9: - Added Dave's Reviewed-by v7 -> v8: - Improved the comment of TDX supported page sizes macros (Dave) v6 -> v7: - Removed the helper to convert kernel page level to TDX page level. - Changed to use macro to define TDX supported page sizes. --- arch/x86/coco/tdx/tdx.c | 6 +++--- arch/x86/include/asm/tdx.h | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index b593009b30ab..e27c3cd97fcb 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -777,13 +777,13 @@ static bool try_accept_one(phys_addr_t *start, unsign= ed long len, */ switch (pg_level) { case PG_LEVEL_4K: - page_size =3D 0; + page_size =3D TDX_PS_4K; break; case PG_LEVEL_2M: - page_size =3D 1; + page_size =3D TDX_PS_2M; break; case PG_LEVEL_1G: - page_size =3D 2; + page_size =3D TDX_PS_1G; break; default: return false; diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 28d889c9aa16..25fd6070dc0b 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -20,6 +20,11 @@ =20 #ifndef __ASSEMBLY__ =20 +/* TDX supported page sizes from the TDX module ABI. */ +#define TDX_PS_4K 0 +#define TDX_PS_2M 1 +#define TDX_PS_1G 2 + /* * Used to gather the output registers values of the TDCALL and SEAMCALL * instructions when requesting services from the TDX module. --=20 2.39.2