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Fri, 25 Aug 2023 03:31:40 -0700 From: Nicolin Chen To: , , CC: , , , , Subject: [PATCH v3 1/2] iommu/arm-smmu-v3: Add boolean bypass_ste and skip_cdtab flags Date: Fri, 25 Aug 2023 03:31:23 -0700 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F8:EE_|SJ0PR12MB6927:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ee07a61-e34b-4eb6-829b-08dba5567df1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HUsN8vvYi7CESkLJg4UDSVp4O0NPKhtfpHFn/hJpipnSAveURPrbrAgUANlAmZFWE/mh0ynn+kmeQ/R514j2cTTpNrxcIkGWMN8gkQZJ3/GCl9Fp6lPK7VKabMK8p29f57zixmcIvsa9JqxXKKdFt2glp3yA061cxM6FgnbFNLe9bz+jXdAnZUwcWVSvzwIHCTnSCilC7RieWGTFBpqPHuN6KjWa0PePrXXN80LLvBRzKGaO2/GP8mSEZpLmLYLYzk0Chl3sHSz04MvcWEv4VAVtxMcy6z4e6CsZMs2mbmus5zBvur7eTJuKCk0ZWWOqhNVXqilZKbV3zIutc2qD5OFCdyzEvUs8NTtOZztE9ceYURzg1zlAXbXdFvbJZx2q7wZI6td0tQM4g9fR3YI5Am6W6gvGa+b62RemciFtqRtyabZhNO21PTK335dXEfSgfR+7McZ2i2IEmSvbZaGW5o5koGbtcO+k7FQFbVWdmEKqiP/D9/05zWl5//brcw+Vuehpf8CAWeF0aEs8EPrDl775G38rX8bSlJfDAtSH8OLpOZUcQ+MsX1t4bZ8SmbaNH7CIUjk8Re6xuWT1afUL2qWwKLtsHscUaaGmpIwncbBuqZHDyIknrzW/PFx8/ZvhsG3EZRI/9X2FCzADk0Yr+7zKtBvZDG9IV3QoxOGMeh+nAFwxx3nfTtSpYzSjpy/NzBPnr2wU3nU9B0DKNmErhAlaY26gfxQuvA612JPthobDkwHI/bzHQCTc0Rh+mUlR X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(376002)(136003)(39860400002)(82310400011)(1800799009)(451199024)(186009)(36840700001)(46966006)(40470700004)(336012)(36860700001)(83380400001)(26005)(478600001)(47076005)(40480700001)(2616005)(5660300002)(426003)(2906002)(8936002)(4326008)(8676002)(356005)(7636003)(82740400003)(40460700003)(6636002)(110136005)(70206006)(70586007)(86362001)(41300700001)(54906003)(36756003)(7696005)(6666004)(316002);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Aug 2023 10:31:50.1026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ee07a61-e34b-4eb6-829b-08dba5567df1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F8.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6927 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If a master has only a default substream, it can skip CD/translation table allocations when being attached to an IDENTITY domain, by simply setting STE to the "bypass" mode (STE.Config[2:0] =3D=3D 0b100). If a master has multiple substreams, it will still need a CD table for the non-default substreams when being attached to an IDENTITY domain, in which case the STE.Config is set to the "stage-1 translate" mode while STE.S1DSS field instead is set to the "bypass" mode (STE.S1DSS[1:0] =3D=3D 0b01). If a master is attached to a stage-2 domain, it does not need a CD table, while the STE.Config is set to the "stage-2 translate" mode. Add boolean bypass_ste and skip_cdtab flags in arm_smmu_attach_dev(), to handle clearly the cases above, which also corrects the conditions at the ats_enabled setting and arm_smmu_alloc_cd_tables() callback to cover the second use case. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 ++++++++++++++++----- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index ffd430948e9e..de8bc4c3ad7a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2406,6 +2406,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev) struct arm_smmu_device *smmu; struct arm_smmu_domain *smmu_domain =3D to_smmu_domain(domain); struct arm_smmu_master *master; + bool byapss_ste, skip_cdtab; =20 if (!fwspec) return -ENOENT; @@ -2441,6 +2442,24 @@ static int arm_smmu_attach_dev(struct iommu_domain *= domain, struct device *dev) =20 master->domain =3D smmu_domain; =20 + /* + * When master attaches ARM_SMMU_DOMAIN_BYPASS to its single substream, + * set STE.Config to "bypass" and skip a CD table allocation. Otherwise, + * set STE.Config to "stage-1 translate" and allocate a CD table for its + * multiple stage-1 substream support, unless with a stage-2 domain in + * which case set STE.config to "stage-2 translate" and skip a CD table. + */ + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_BYPASS && !master->ssid_bit= s) { + byapss_ste =3D true; + skip_cdtab =3D true; + } else { + byapss_ste =3D false; + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S2) + skip_cdtab =3D true; + else + skip_cdtab =3D false; + } + /* * The SMMU does not support enabling ATS with bypass. When the STE is * in bypass (STE.Config[2:0] =3D=3D 0b100), ATS Translation Requests and @@ -2448,22 +2467,22 @@ static int arm_smmu_attach_dev(struct iommu_domain = *domain, struct device *dev) * stream (STE.EATS =3D=3D 0b00), causing F_BAD_ATS_TREQ and * F_TRANSL_FORBIDDEN events (IHI0070Ea 5.2 Stream Table Entry). */ - if (smmu_domain->stage !=3D ARM_SMMU_DOMAIN_BYPASS) + if (!byapss_ste) master->ats_enabled =3D arm_smmu_ats_supported(master); =20 spin_lock_irqsave(&smmu_domain->devices_lock, flags); list_add(&master->domain_head, &smmu_domain->devices); spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); =20 - if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { - if (!master->cd_table.cdtab) { - ret =3D arm_smmu_alloc_cd_tables(master); - if (ret) { - master->domain =3D NULL; - goto out_list_del; - } + if (!skip_cdtab && !master->cd_table.cdtab) { + ret =3D arm_smmu_alloc_cd_tables(master); + if (ret) { + master->domain =3D NULL; + goto out_list_del; } + } =20 + if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { /* * Prevent SVA from concurrently modifying the CD or writing to * the CD entry --=20 2.42.0