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charset="utf-8" From: Chen Wang Add PCIe controller nodes in DTS for Sophgo SG2042. Default they are disabled. Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/s= ophgo/sg2042.dtsi index e62ac51ac55a..dca51fa9381b 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -195,6 +195,88 @@ clkgen: clock-controller@7030012000 { #clock-cells =3D <1>; }; =20 + pcie_rc0: pcie@7060000000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range =3D <0x0 0x3f>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + sophgo,link-id =3D <0>; + sophgo,syscon-pcie-ctrl =3D <&cdns_pcie0_ctrl>; + interrupt-parent =3D <&msi>; + status =3D "disabled"; + }; + + cdns_pcie0_ctrl: syscon@7061800000 { + compatible =3D "sophgo,sg2042-pcie-ctrl", "syscon"; + reg =3D <0x70 0x61800000 0x0 0x800000>; + }; + + pcie_rc1: pcie@7062000000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000= >, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range =3D <0x80 0xbf>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + sophgo,link-id =3D <0>; + sophgo,syscon-pcie-ctrl =3D <&cdns_pcie1_ctrl>; + sophgo,internal-msi; + interrupt-parent =3D <&intc>; + interrupts =3D <123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "msi"; + status =3D "disabled"; + }; + + pcie_rc2: pcie@7062800000 { + compatible =3D "sophgo,sg2042-pcie-host"; + device_type =3D "pci"; + reg =3D <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names =3D "reg", "cfg"; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000= >, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range =3D <0xc0 0xff>; + vendor-id =3D <0x1f1c>; + device-id =3D <0x2042>; + cdns,no-bar-match-nbits =3D <48>; + sophgo,link-id =3D <1>; + sophgo,syscon-pcie-ctrl =3D <&cdns_pcie1_ctrl>; + interrupt-parent =3D <&msi>; + status =3D "disabled"; + }; + + cdns_pcie1_ctrl: syscon@7063800000 { + compatible =3D "sophgo,sg2042-pcie-ctrl", "syscon"; + reg =3D <0x70 0x63800000 0x0 0x800000>; + }; + clint_mswi: interrupt-controller@7094000000 { compatible =3D "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; reg =3D <0x00000070 0x94000000 0x00000000 0x00004000>; --=20 2.34.1