From nobody Sun Feb 8 16:12:12 2026 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3680627934B; Thu, 22 Jan 2026 16:39:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769099986; cv=none; b=aO1pFQ7Zl2c7pO9u4Jyz283KwUP1Z0KTF1aElhI2mx2W/QEopZN+JHT921Mx4sq067FxyFbKIXQKoeXmGPQmdwA2bF1/gSAdmhJZgJPNi25t95uFxRU0w/J8sIwj9P7eQaEWahJuA3sShwmXf/0hAAfMocS8/8TtdBNneDTBTX8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1769099986; c=relaxed/simple; bh=9/wOEAP9Z70YlA94ausVaW4pw/bf8VxiowP0V8TIO9U=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ZrD8TFIbgIxOjVTpadf0UYZI6WzuhO8yPpFa0fZh/F2Sp/eawtaIjyeIJuy1IBeceJ4jHorZHS9hSQU553AnkTxHFUIhv8OHTyKX4AMv4HDYkpxnt2z4H0UAm5dmlHo25gWC042CaZJKPBqdJMSXTBZBGD9cHikfyDaPG4+WjVc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1vixiX-000000001S0-0svo; Thu, 22 Jan 2026 16:39:33 +0000 Date: Thu, 22 Jan 2026 16:39:30 +0000 From: Daniel Golle To: Hauke Mehrtens , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Chen Minqiang , Xinfa Deng Subject: [PATCH net-next v6 6/6] net: dsa: mxl-gsw1xx: add support for Intel GSW150 Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the Intel GSW150 (aka. Lantiq PEB7084) switch IC to the mxl-gsw1xx driver. This switch comes with 5 Gigabit Ethernet copper ports (Intel XWAY PHY11G (xRX v1.2 integrated) PHYs) as well as one GMII/RGMII and one RGMII port. Signed-off-by: Daniel Golle --- v6: * rebase on top of current net-next * update Kconfig to mention GSW150 * allow configuring RGMII slewrate introduced by commit dbf24ab58fec3 ("net: dsa: mxl-gsw1xx: Support R(G)MII slew rate configuration") v5: no changes v4: spell out mii_cfg and mii_pcdu values in struct gswip_hw_info instead of using default initializer which requires diag exception v3: enclose the gswip_hw_info initializers in compiler diag exception to prevent triggering -Woverride-init v2: clean-up phylink_get_caps drivers/net/dsa/lantiq/Kconfig | 4 +- drivers/net/dsa/lantiq/mxl-gsw1xx.c | 67 ++++++++++++++++++++++++++--- drivers/net/dsa/lantiq/mxl-gsw1xx.h | 2 + 3 files changed, 67 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/lantiq/Kconfig b/drivers/net/dsa/lantiq/Kconfig index 4a9771be5d588..bad13817af257 100644 --- a/drivers/net/dsa/lantiq/Kconfig +++ b/drivers/net/dsa/lantiq/Kconfig @@ -16,9 +16,11 @@ config NET_DSA_MXL_GSW1XX select NET_DSA_TAG_MXL_GSW1XX select NET_DSA_LANTIQ_COMMON help - This enables support for the MaxLinear GSW1xx family of 1GE switches + This enables support for the Intel/MaxLinear GSW1xx family of 1GE + switches. GSW120 4 port, 2 PHYs, RGMII & SGMII/2500Base-X GSW125 4 port, 2 PHYs, RGMII & SGMII/2500Base-X, industrial temperatu= re GSW140 6 port, 4 PHYs, RGMII & SGMII/2500Base-X GSW141 6 port, 4 PHYs, RGMII & SGMII GSW145 6 port, 4 PHYs, RGMII & SGMII/2500Base-X, industrial temperatu= re + GSW150 7 port, 5 PHYs, 1x GMII/RGMII, 1x RGMII diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.c b/drivers/net/dsa/lantiq/m= xl-gsw1xx.c index c6fa93229349a..79cf72cc77be9 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.c +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.c @@ -502,6 +502,14 @@ static const struct phylink_pcs_ops gsw1xx_pcs_ops =3D= { .pcs_link_up =3D gsw1xx_pcs_link_up, }; =20 +static void gsw1xx_phylink_get_lpi_caps(struct phylink_config *config) +{ + config->lpi_capabilities =3D MAC_100FD | MAC_1000FD; + config->lpi_timer_default =3D 20; + memcpy(config->lpi_interfaces, config->supported_interfaces, + sizeof(config->lpi_interfaces)); +} + static void gsw1xx_phylink_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -535,10 +543,32 @@ static void gsw1xx_phylink_get_caps(struct dsa_switch= *ds, int port, break; } =20 - config->lpi_capabilities =3D MAC_100FD | MAC_1000FD; - config->lpi_timer_default =3D 20; - memcpy(config->lpi_interfaces, config->supported_interfaces, - sizeof(config->lpi_interfaces)); + gsw1xx_phylink_get_lpi_caps(config); +} + +static void gsw150_phylink_get_caps(struct dsa_switch *ds, int port, + struct phylink_config *config) +{ + config->mac_capabilities =3D MAC_ASYM_PAUSE | MAC_SYM_PAUSE | + MAC_10 | MAC_100 | MAC_1000; + + switch (port) { + case 0 ... 4: /* built-in PHYs */ + __set_bit(PHY_INTERFACE_MODE_INTERNAL, + config->supported_interfaces); + break; + + case 5: /* GMII or RGMII */ + __set_bit(PHY_INTERFACE_MODE_GMII, + config->supported_interfaces); + fallthrough; + + case 6: /* RGMII */ + phy_interface_set_rgmii(config->supported_interfaces); + break; + } + + gsw1xx_phylink_get_lpi_caps(config); } =20 static struct phylink_pcs *gsw1xx_phylink_mac_select_pcs(struct phylink_co= nfig *config, @@ -809,11 +839,38 @@ static const struct gswip_hw_info gsw141_data =3D { .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, }; =20 +static const struct gswip_hw_info gsw150_data =3D { + .max_ports =3D GSW150_PORTS, + .allowed_cpu_ports =3D BIT(5) | BIT(6), + .mii_cfg =3D { + [0 ... 4] =3D -1, + [5] =3D 0, + [6] =3D 10, + }, + .mii_pcdu =3D { + [0 ... 4] =3D -1, + [5] =3D 1, + [6] =3D 11, + }, + .phylink_get_caps =3D gsw150_phylink_get_caps, + /* There is only a single RGMII_SLEW_CFG register in GSW150 and it is + * unknown if RGMII slew configuration affects both RGMII ports + * or only port 5. Use .port_setup which assumes it affects port 5 + * for now. + */ + .port_setup =3D gsw1xx_port_setup, + .pce_microcode =3D &gsw1xx_pce_microcode, + .pce_microcode_size =3D ARRAY_SIZE(gsw1xx_pce_microcode), + .tag_protocol =3D DSA_TAG_PROTO_MXL_GSW1XX, +}; + /* * GSW125 is the industrial temperature version of GSW120. * GSW145 is the industrial temperature version of GSW140. */ static const struct of_device_id gsw1xx_of_match[] =3D { + { .compatible =3D "intel,gsw150", .data =3D &gsw150_data }, + { .compatible =3D "lantiq,peb7084", .data =3D &gsw150_data }, { .compatible =3D "maxlinear,gsw120", .data =3D &gsw12x_data }, { .compatible =3D "maxlinear,gsw125", .data =3D &gsw12x_data }, { .compatible =3D "maxlinear,gsw140", .data =3D &gsw140_data }, @@ -837,5 +894,5 @@ static struct mdio_driver gsw1xx_driver =3D { mdio_module_driver(gsw1xx_driver); =20 MODULE_AUTHOR("Daniel Golle "); -MODULE_DESCRIPTION("Driver for MaxLinear GSW1xx ethernet switch"); +MODULE_DESCRIPTION("Driver for Intel/MaxLinear GSW1xx Ethernet switch"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/dsa/lantiq/mxl-gsw1xx.h b/drivers/net/dsa/lantiq/m= xl-gsw1xx.h index 8c0298b2b7663..d1fded56e9678 100644 --- a/drivers/net/dsa/lantiq/mxl-gsw1xx.h +++ b/drivers/net/dsa/lantiq/mxl-gsw1xx.h @@ -10,6 +10,8 @@ #include =20 #define GSW1XX_PORTS 6 +#define GSW150_PORTS 7 + /* Port used for RGMII or optional RMII */ #define GSW1XX_MII_PORT 5 /* Port used for SGMII */ --=20 2.52.0