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Mon, 01 Dec 2025 05:08:36 -0800 (PST) Date: Mon, 1 Dec 2025 16:08:33 +0300 From: Dan Carpenter To: Chester Lin Cc: Matthias Brugger , Ghennadi Procopciuc , NXP S32 Linux Team , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-s32@linaro.org Subject: [PATCH 4/4] dts: s32g: Add GPR syscon region Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 8 ++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts= /freescale/s32g2.dtsi index 51d00dac12de..3c9472f6c174 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,13 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -731,6 +738,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts= /freescale/s32g3.dtsi index eff7673e7f34..0ceca3caf133 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,13 @@ usdhc0-200mhz-grp4 { }; }; =20 + gpr: syscon@4007c000 { + compatible =3D "nxp,s32-gpr", "syscon"; + reg =3D <0x4007c000 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; + ocotp: nvmem@400a4000 { compatible =3D "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; reg =3D <0x400a4000 0x400>; @@ -808,6 +815,7 @@ gmac0: ethernet@4033c000 { compatible =3D "nxp,s32g2-dwmac"; reg =3D <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + phy-sel =3D <&gpr 0x4>; interrupt-parent =3D <&gic>; interrupts =3D ; interrupt-names =3D "macirq"; --=20 2.51.0