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[72.189.67.6]) by smtp.gmail.com with ESMTPSA id h7-20020a0561220b6700b0047dbd48bc44sm238059vkf.17.2023.07.20.11.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Jul 2023 11:50:00 -0700 (PDT) From: William Breathitt Gray To: Bartosz Golaszewski , Linus Walleij Cc: Lars-Peter Clausen , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, William Breathitt Gray Subject: [RESEND PATCH 2/2] iio: addac: stx104: Add 8254 Counter/Timer support Date: Thu, 20 Jul 2023 14:49:44 -0400 Message-ID: X-Mailer: git-send-email 2.41.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The STX104 features an 8254 Counter/Timer chip providing three counter/timers which can be used for frequency measurement, frequency output, pulse width modulation, pulse width measurement, event count, etc. The STX104 provides a register bank selection to bank select between the 8254 Bank and the Indexed Register Array Bank; the Indexed Register Array is not utilized by this driver, so the 8254 Bank is selected unconditionally. Signed-off-by: William Breathitt Gray --- drivers/iio/addac/Kconfig | 1 + drivers/iio/addac/stx104.c | 61 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 60 insertions(+), 2 deletions(-) diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig index 877f9124803c..b2623881f0ec 100644 --- a/drivers/iio/addac/Kconfig +++ b/drivers/iio/addac/Kconfig @@ -38,6 +38,7 @@ config STX104 select REGMAP_MMIO select GPIOLIB select GPIO_REGMAP + select I8254 help Say yes here to build support for the Apex Embedded Systems STX104 integrated analog PC/104 card. diff --git a/drivers/iio/addac/stx104.c b/drivers/iio/addac/stx104.c index d1f7ce033b46..6946a65512ca 100644 --- a/drivers/iio/addac/stx104.c +++ b/drivers/iio/addac/stx104.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -55,6 +56,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base= addresses"); #define STX104_ADC_STATUS (STX104_AIO_BASE + 0x8) #define STX104_ADC_CONTROL (STX104_AIO_BASE + 0x9) #define STX104_ADC_CONFIGURATION (STX104_AIO_BASE + 0x11) +#define STX104_I8254_BASE (STX104_AIO_BASE + 0x12) =20 #define STX104_AIO_DATA_STRIDE 2 #define STX104_DAC_OFFSET(_channel) (STX104_DAC_BASE + STX104_AIO_DATA_STR= IDE * (_channel)) @@ -77,6 +79,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base= addresses"); /* ADC Configuration */ #define STX104_GAIN GENMASK(1, 0) #define STX104_ADBU BIT(2) +#define STX104_RBK GENMASK(7, 4) #define STX104_BIPOLAR 0 #define STX104_GAIN_X1 0 #define STX104_GAIN_X2 1 @@ -168,6 +171,32 @@ static const struct regmap_config dio_regmap_config = =3D { .io_port =3D true, }; =20 +static const struct regmap_range pit_wr_ranges[] =3D { + regmap_reg_range(0x0, 0x3), +}; +static const struct regmap_range pit_rd_ranges[] =3D { + regmap_reg_range(0x0, 0x2), +}; +static const struct regmap_access_table pit_wr_table =3D { + .yes_ranges =3D pit_wr_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_wr_ranges), +}; +static const struct regmap_access_table pit_rd_table =3D { + .yes_ranges =3D pit_rd_ranges, + .n_yes_ranges =3D ARRAY_SIZE(pit_rd_ranges), +}; + +static const struct regmap_config pit_regmap_config =3D { + .name =3D "i8254", + .reg_bits =3D 8, + .reg_stride =3D 1, + .reg_base =3D STX104_I8254_BASE, + .val_bits =3D 8, + .io_port =3D true, + .wr_table =3D &pit_wr_table, + .rd_table =3D &pit_rd_table, +}; + static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { @@ -339,6 +368,21 @@ static const char *stx104_names[STX104_NGPIO] =3D { "DIN0", "DIN1", "DIN2", "DIN3", "DOUT0", "DOUT1", "DOUT2", "DOUT3" }; =20 +static int bank_select_i8254(struct regmap *map) +{ + const u8 select_i8254[] =3D { 0x3, 0xB, 0xA }; + size_t i; + int err; + + for (i =3D 0; i < ARRAY_SIZE(select_i8254); i++) { + err =3D regmap_write_bits(map, STX104_ADC_CONFIGURATION, STX104_RBK, sel= ect_i8254[i]); + if (err) + return err; + } + + return 0; +} + static int stx104_init_hw(struct stx104_iio *const priv) { int err; @@ -361,7 +405,7 @@ static int stx104_init_hw(struct stx104_iio *const priv) if (err) return err; =20 - return 0; + return bank_select_i8254(priv->aio_ctl_map); } =20 static int stx104_probe(struct device *dev, unsigned int id) @@ -369,6 +413,7 @@ static int stx104_probe(struct device *dev, unsigned in= t id) struct iio_dev *indio_dev; struct stx104_iio *priv; struct gpio_regmap_config gpio_config; + struct i8254_regmap_config pit_config; void __iomem *stx104_base; struct regmap *aio_ctl_map; struct regmap *aio_data_map; @@ -406,6 +451,11 @@ static int stx104_probe(struct device *dev, unsigned i= nt id) return dev_err_probe(dev, PTR_ERR(dio_map), "Unable to initialize dio register map\n"); =20 + pit_config.map =3D devm_regmap_init_mmio(dev, stx104_base, &pit_regmap_co= nfig); + if (IS_ERR(pit_config.map)) + return dev_err_probe(dev, PTR_ERR(pit_config.map), + "Unable to initialize i8254 register map\n"); + priv =3D iio_priv(indio_dev); priv->aio_ctl_map =3D aio_ctl_map; priv->aio_data_map =3D aio_data_map; @@ -449,7 +499,13 @@ static int stx104_probe(struct device *dev, unsigned i= nt id) .drvdata =3D dio_map, }; =20 - return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); + err =3D PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config)); + if (err) + return err; + + pit_config.parent =3D dev; + + return devm_i8254_regmap_register(dev, &pit_config); } =20 static struct isa_driver stx104_driver =3D { @@ -464,3 +520,4 @@ module_isa_driver(stx104_driver, num_stx104); MODULE_AUTHOR("William Breathitt Gray "); MODULE_DESCRIPTION("Apex Embedded Systems STX104 IIO driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS(I8254); --=20 2.41.0