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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2025 02:28:52.2317 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cbe31454-cb41-4f9d-ceb9-08dddba379a7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7900 Content-Type: text/plain; charset="utf-8" resctrl_arch_rmid_read() adjusts the value obtained from MSR_IA32_QM_CTR to account for the overflow for MBM events and apply counter scaling for all the events. This logic is common to both reading an RMID and reading a hardware counter directly. Refactor the hardware value adjustment logic into get_corrected_val() to prepare for support of reading a hardware counter. Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v17: Added Reviewed-by tag. v16: Rephrased the changelog. Fixed allignment. Renamed mbm_corrected_val() -> get_corrected_val(). v15: New patch to add arch calls resctrl_arch_cntr_read() and resctrl_arch_= reset_cntr() with mbm_event mode. https://lore.kernel.org/lkml/b4b14670-9cb0-4f65-abd5-39db996e8da9@inte= l.com/ --- arch/x86/kernel/cpu/resctrl/monitor.c | 38 ++++++++++++++++----------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index ed295a6c5e66..1f77fd58e707 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -217,24 +217,13 @@ static u64 mbm_overflow_count(u64 prev_msr, u64 cur_m= sr, unsigned int width) return chunks >> shift; } =20 -int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, - u32 unused, u32 rmid, enum resctrl_event_id eventid, - u64 *val, void *ignored) +static u64 get_corrected_val(struct rdt_resource *r, struct rdt_mon_domain= *d, + u32 rmid, enum resctrl_event_id eventid, u64 msr_val) { struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); - int cpu =3D cpumask_any(&d->hdr.cpu_mask); struct arch_mbm_state *am; - u64 msr_val, chunks; - u32 prmid; - int ret; - - resctrl_arch_rmid_read_context_check(); - - prmid =3D logical_rmid_to_physical_rmid(cpu, rmid); - ret =3D __rmid_read_phys(prmid, eventid, &msr_val); - if (ret) - return ret; + u64 chunks; =20 am =3D get_arch_mbm_state(hw_dom, rmid, eventid); if (am) { @@ -246,7 +235,26 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, str= uct rdt_mon_domain *d, chunks =3D msr_val; } =20 - *val =3D chunks * hw_res->mon_scale; + return chunks * hw_res->mon_scale; +} + +int resctrl_arch_rmid_read(struct rdt_resource *r, struct rdt_mon_domain *= d, + u32 unused, u32 rmid, enum resctrl_event_id eventid, + u64 *val, void *ignored) +{ + int cpu =3D cpumask_any(&d->hdr.cpu_mask); + u64 msr_val; + u32 prmid; + int ret; + + resctrl_arch_rmid_read_context_check(); + + prmid =3D logical_rmid_to_physical_rmid(cpu, rmid); + ret =3D __rmid_read_phys(prmid, eventid, &msr_val); + if (ret) + return ret; + + *val =3D get_corrected_val(r, d, rmid, eventid, msr_val); =20 return 0; } --=20 2.34.1