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Mon, 24 Jul 2023 16:54:25 +0800 (CST) MIME-Version: 1.0 Date: Mon, 24 Jul 2023 16:54:25 +0800 From: sunran001@208suo.com To: alexander.deucher@amd.com Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amd/pm: Clean up errors in smu_v11_0_7_pptable.h In-Reply-To: <20230724085303.9607-1-xujianghui@cdjrlc.com> References: <20230724085303.9607-1-xujianghui@cdjrlc.com> User-Agent: Roundcube Webmail Message-ID: X-Sender: sunran001@208suo.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8"; format="flowed" Fix the following errors reported by checkpatch: ERROR: trailing whitespace ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun --- .../amd/pm/swsmu/inc/smu_v11_0_7_pptable.h | 41 +++++++++---------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h=20 b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h index 1cb399dbc7cc..64d60d48846a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h @@ -42,23 +42,23 @@ #define SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION 0x01 =20 // Power Saving Clock Table Version 1.00 enum SMU_11_0_7_ODFEATURE_CAP { - SMU_11_0_7_ODCAP_GFXCLK_LIMITS =3D 0, - SMU_11_0_7_ODCAP_GFXCLK_CURVE, - SMU_11_0_7_ODCAP_UCLK_LIMITS, - SMU_11_0_7_ODCAP_POWER_LIMIT, - SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, - SMU_11_0_7_ODCAP_FAN_SPEED_MIN, - SMU_11_0_7_ODCAP_TEMPERATURE_FAN, - SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, - SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, - SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, - SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, - SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, - SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, + SMU_11_0_7_ODCAP_GFXCLK_LIMITS =3D 0, + SMU_11_0_7_ODCAP_GFXCLK_CURVE, + SMU_11_0_7_ODCAP_UCLK_LIMITS, + SMU_11_0_7_ODCAP_POWER_LIMIT, + SMU_11_0_7_ODCAP_FAN_ACOUSTIC_LIMIT, + SMU_11_0_7_ODCAP_FAN_SPEED_MIN, + SMU_11_0_7_ODCAP_TEMPERATURE_FAN, + SMU_11_0_7_ODCAP_TEMPERATURE_SYSTEM, + SMU_11_0_7_ODCAP_MEMORY_TIMING_TUNE, + SMU_11_0_7_ODCAP_FAN_ZERO_RPM_CONTROL, + SMU_11_0_7_ODCAP_AUTO_UV_ENGINE, + SMU_11_0_7_ODCAP_AUTO_OC_ENGINE, + SMU_11_0_7_ODCAP_AUTO_OC_MEMORY, SMU_11_0_7_ODCAP_FAN_CURVE, SMU_11_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, - SMU_11_0_7_ODCAP_POWER_MODE, - SMU_11_0_7_ODCAP_COUNT, + SMU_11_0_7_ODCAP_POWER_MODE, + SMU_11_0_7_ODCAP_COUNT, }; enum SMU_11_0_7_ODFEATURE_ID { @@ -130,8 +130,7 @@ enum SMU_11_0_7_PWRMODE_SETTING { }; #define SMU_11_0_7_MAX_PMSETTING 32 //Maximum Number of=20 PowerMode Settings -struct smu_11_0_7_overdrive_table -{ +struct smu_11_0_7_overdrive_table { uint8_t revision; =20 //Revision =3D SMU_11_0_7_PP_OVERDRIVE_VERSION uint8_t reserve[3]; //Zero=20 filled field reserved for future use uint32_t feature_count; //Total=20 number of supported features @@ -160,8 +159,7 @@ enum SMU_11_0_7_PPCLOCK_ID { }; #define SMU_11_0_7_MAX_PPCLOCK 16 //Maximum Number of PP=20 Clocks -struct smu_11_0_7_power_saving_clock_table -{ +struct smu_11_0_7_power_saving_clock_table { uint8_t revision; =20 //Revision =3D SMU_11_0_7_PP_POWERSAVINGCLOCK_VERSION uint8_t reserve[3]; //Zero=20 filled field reserved for future use uint32_t count; =20 //power_saving_clock_count =3D SMU_11_0_7_PPCLOCK_COUNT @@ -169,8 +167,7 @@ struct smu_11_0_7_power_saving_clock_table uint32_t min[SMU_11_0_7_MAX_PPCLOCK]; =20 //PowerSavingClock Mode Clock Minimum array In MHz }; -struct smu_11_0_7_powerplay_table -{ +struct smu_11_0_7_powerplay_table { struct atom_common_table_header header; //For=20 sienna_cichlid, header.format_revision =3D 15, header.content_revision =3D 0 uint8_t table_revision; //For=20 sienna_cichlid, table_revision =3D 2 uint16_t table_size; //Driver portion=20 table size. The offset to smc_pptable including header size @@ -178,7 +175,7 @@ struct smu_11_0_7_powerplay_table uint32_t golden_revision; //PPGen use only:=20 PP Table Revision on the Golden Data Base uint16_t format_id; //PPGen use only:=20 PPTable for different ASICs. For sienna_cichlid this should be 0x80 uint32_t platform_caps; =20 //POWERPLAYABLE::ulPlatformCaps - + uint8_t thermal_controller_type; //one of=20 SMU_11_0_7_PP_THERMALCONTROLLER uint16_t small_power_limit1;